KR101221611B1 - Stereoscopic image display device, and driving method the same - Google Patents

Abstract

The present invention relates to a stereoscopic image display apparatus and a driving method thereof capable of improving image quality of a 3D image by improving an aperture ratio of a pixel and improving a luminance of a 2D image, and a stereoscopic image display apparatus includes a 2D display mode. And a display panel having a pixel for displaying a two-dimensional image in accordance with a three-dimensional display mode, wherein the pixel displays the two-dimensional image in the two-dimensional display mode and displays the three-dimensional image. A first subpixel which displays the 3D image in mode; And a second subpixel displaying the same 2D image as the first subpixel in the 2D display mode and displaying a black image in the 3D display mode.

Description

STEREOSCOPIC IMAGE DISPLAY DEVICE, AND DRIVING METHOD THE SAME

The present invention relates to a stereoscopic image display apparatus, and more particularly, to a stereoscopic image display apparatus and a driving method thereof, which can improve the image quality of a 3D image and improve the brightness of a 2D image by improving an aperture ratio of a pixel. It is about.

As the modern society is highly informationized, display devices face the market demand for larger size and thinner, and according to such demand, there is a demand for various types of flat panel display devices having advantages of thinning, light weight, and low power consumption. Is exploding.

The liquid crystal display device, the plasma display panel, the field emission display device, and the light emitting display device are actively researched as the flat display device. However, liquid crystal display devices have been in the spotlight due to mass production technology, ease of driving means, and high quality.

In recent years, a stereoscopic image display apparatus that enables a viewer to view a stereoscopic three-dimensional image from a two-dimensional image displayed on a display apparatus has been developed.

The stereoscopic image display device is a device for showing a left eye image and a right eye image having a binocular parallax separately in each of the viewer's left and right eyes. That is, the stereoscopic image display apparatus enables the viewer to watch a 3D image having a stereoscopic sense by allowing the left eye image to be recognized only in the left eye of the viewer and the right eye image only to the viewer's right eye.

However, in the conventional stereoscopic image display apparatus, the left eye image is recognized only in the viewer's left eye and the right eye image should be recognized only in the viewer's right eye. The image is recognized. Accordingly, the conventional stereoscopic image display apparatus has a problem in that the image quality is degraded due to cross talk between the left eye image and the right eye image.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and to provide a stereoscopic image display apparatus and a driving method thereof capable of improving the image quality of a 3D image by improving the aperture ratio of a pixel and improving the luminance of the 2D image. It is a technical problem.

The stereoscopic image display apparatus according to the present invention for achieving the above technical problem includes a display panel having a pixel for displaying a two-dimensional image in accordance with the two-dimensional display mode and a three-dimensional image in accordance with the three-dimensional display mode The pixel may include: a first subpixel configured to display the 2D image in the 2D display mode and to display the 3D image in the 3D display mode; And a second subpixel displaying the same 2D image as the first subpixel in the 2D display mode and displaying a black image in the 3D display mode.

The display panel may include a first gate line formed between the first and second subpixels to supply a first gate signal to the first and second subpixels; A second gate line formed adjacent to the second subpixel to supply a second gate signal to the second subpixel; A data line intersecting the first and second gate lines to supply a two-dimensional data voltage according to the two-dimensional display mode or a three-dimensional data voltage according to the three-dimensional display mode to the first and second subpixels. ; A first common voltage line for supplying a first common voltage to the first and second subpixels; A second common voltage line for supplying a second common voltage to the second subpixel; A mode driving signal line supplied with a mode driving signal corresponding to the two-dimensional display mode or the three-dimensional display mode; And a switching device configured to switch according to the mode driving signal to supply the second common voltage to the second subpixel such that the black image is displayed on the second subpixel in the 3D display mode. It features.

A first gate line formed between the first and second subpixels to supply a first gate signal to the first and second subpixels; A second gate line formed adjacent to the second subpixel to supply a second gate signal to the second subpixel; A data line intersecting the first and second gate lines to supply a two-dimensional data voltage according to the two-dimensional display mode or a three-dimensional data voltage according to the three-dimensional display mode to the first and second subpixels. ; A first common voltage line for supplying a first common voltage to the first and second subpixels; A second common voltage line for supplying a second common voltage to the second subpixel; A mode driving signal line supplied with a mode driving signal corresponding to the two-dimensional display mode or the three-dimensional display mode; And a switching device configured to switch according to the mode driving signal to supply the second common voltage to the second subpixel such that the black image is displayed on the second subpixel in the 3D display mode. It features.

The stereoscopic image display apparatus according to the present invention for achieving the above technical problem includes a display panel having a pixel for displaying a two-dimensional image in accordance with the two-dimensional display mode and a three-dimensional image in accordance with the three-dimensional display mode The pixel displays the 2D image using the 2D data voltage and the first common voltage in the 2D display mode, and uses the 3D data voltage and the first common voltage 3 in the 3D display mode. The black image may be displayed using the second common voltage and the first common voltage which are the same as the first common voltage while displaying the dimensional image.

The pixel may include: a first subpixel configured to display the 2D image in the 2D display mode and to display the 3D image in the 3D display mode; And a second subpixel configured to display the same 2D image as the first subpixel in the 2D display mode and to display the black image in the 3D display mode.

According to an aspect of the present invention, there is provided a method of driving a stereoscopic image display apparatus, the method including displaying a 2D image on a pixel using a 2D data voltage and a first common voltage according to a 2D display mode; And displaying a 3D image using a 3D data voltage and the first common voltage according to a 3D display mode, and simultaneously using the second common voltage and the first common voltage that are the same as the first common voltage. Characterized in that it comprises a step of displaying.

The displaying of the 2D image may include supplying a first gate signal to first and second subpixels commonly connected to a first gate line; And displaying the two-dimensional image on the first and second subpixels by supplying the two-dimensional data voltage to the first and second subpixels so as to be synchronized with the first gate signal. .

The displaying of the 3D image may include supplying a first gate signal to a first gate line commonly connected to first and second subpixels; Displaying the three-dimensional image on the first and second subpixels by supplying the three-dimensional data voltage to the first and second subpixels so as to be synchronized with the first gate signal; Supplying a second gate signal to a second gate line connected to the second subpixel; And supplying the second common voltage to the second subpixel according to the second gate signal to display the black image on the second subpixel.

The displaying of the 3D image may include supplying a first gate signal to first and second subpixels commonly connected to a first gate line and simultaneously supplying a second gate signal to a second gate line connected to the second subpixel. Supplying; And supplying the three-dimensional data voltage to the first and second subpixels so as to be synchronized with the first gate signal to display the three-dimensional image on the first subpixel and simultaneously with the second gate signal. And supplying the common voltage to the second subpixel to display the black image on the second subpixel.

As described above, the 3D image display apparatus and the driving method thereof according to the present invention have the following effects by forming the first and second subpixels in each pixel displaying an image.

First, by displaying the same two-dimensional image on the first and second sub-pixels in the two-dimensional display mode, it is possible to increase the aperture ratio of the pixel and to increase the luminance of the two-dimensional image.

Second, by displaying a 3D image on the first subpixel and a black image on the second subpixel in the 3D display mode, the left and right eye images of the 3D image displayed adjacent to each other through the black image are separated from each other. The image quality of the 3D image can be improved.

FIG. 1 is a diagram schematically illustrating a stereoscopic image display apparatus according to an exemplary embodiment.
FIG. 2 is a diagram for describing a pixel structure according to the first embodiment of the present invention illustrated in FIG. 1.
3 is a diagram for describing a pixel structure according to a second embodiment of the present invention illustrated in FIG. 1.
4 is a diagram for schematically describing a timing controller illustrated in FIG. 1.
FIG. 5 is a waveform diagram illustrating a mode driving signal generated by the mode driving signal generator shown in FIG. 4.
6A and 6B are waveform diagrams for explaining the gate signal supplied to the gate line from the gate driving circuit shown in FIG.
7A and 7B are diagrams for describing a pixel structure, according to another exemplary embodiment of the present invention illustrated in FIG. 1.
8A and 8B are waveform diagrams schematically illustrating a method of driving a stereoscopic image display apparatus according to a first embodiment of the present invention.
9A and 9B are waveform diagrams schematically illustrating a method of driving a stereoscopic image display apparatus according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram schematically illustrating a stereoscopic image display apparatus according to an exemplary embodiment.

Referring to FIG. 1, a stereoscopic image display apparatus according to an exemplary embodiment of the present invention may include a display panel 100, a common voltage generator 200, a timing controller 300, a gate driver circuit unit 400, and a data driver circuit unit ( 500).

The display panel 100 displays a 2D image using a 2D data voltage and a first common voltage according to a 2D display mode, and uses a 3D data voltage and a first common voltage 3 according to a 3D display mode. And a plurality of pixels P for displaying the black image by using the second common voltage and the first common voltage which are the same as the first common voltage while displaying the dimensional image.

The plurality of pixels P display a first subpixel SP1 for displaying a 2D image in a 2D display mode and a 3D image for a 3D display mode, and a first subpixel SP1 in a 2D display mode. And a second sub-pixel SP2 for displaying the same 2D image as that shown in FIG. 3 and displaying the black image in the 3D display mode.

Meanwhile, as illustrated in FIG. 2, the display panel 110 defines the pixels P including the first and second subpixels SP1 and SP2, and the first and second gate lines 1GL1, 2GL1), a data line DL, first and second common voltage lines VCL1 and VCL2, a mode driving signal line MDSL, and a switching element SW.

The first gate line 1GL1 is formed between the first and second subpixels SP1 and SP2 to receive the first gate signal supplied from the gate driving circuit unit 400 to the first and second subpixels SP1 and SP2. To feed.

The second gate line 2GL1 is formed to be adjacent to the second subpixel SP2 to supply the second gate signal supplied from the gate driving circuit unit 400 to the second subpixel SP2.

The data line DL is formed to intersect the first and second gate lines 1GL1 and 2GL1 to define the first and second subpixels SP1 and SP2. The data line DL may be configured to supply the first and second subpixels SP1 and SP2 to the two-dimensional data voltage according to the two-dimensional display mode or the three-dimensional data voltage supplied to the data driving circuit unit 500. Supplies).

The first common voltage line VCL1 is formed to be parallel to the first gate line 1GL1 to receive the first and second subpixels SP1 and SP2 from the first common voltage Vcom1 supplied from the common voltage generator 200. Supplies). In this case, the first common voltage line VCL1 is formed at one side of the display panel 100 to be parallel to the first gate line 1GL1 and electrically connected to the plurality of pixels P, or the first gate line 1GL1. The plurality of pixels P may be electrically connected to the plurality of pixels P in parallel with each other.

The second common voltage line VCL2 is formed to be parallel to the data line DL to switch the second common voltage Vcom2 that is the same as the first common voltage Vcom1 supplied from the common voltage generator 200. Supplies). In this case, the second common voltage line VCL2 is formed in the non-display area provided on one side of the display panel 100.

The mode driving signal line MDSL is formed in the non-display area of the display panel 100 to supply the mode driving signal MDS supplied from the timing controller 300 to the switching element SW.

The switching element SW is switched according to the mode driving signal MDS supplied to the mode driving signal line MDSL to receive the second common voltage Vcom2 supplied to the second common voltage line VCL2. SP2). To this end, the switching element SW includes a gate electrode connected to the mode driving signal line MDSL, a source electrode connected to the second common voltage line VCL2, and a drain electrode connected to the second subpixel SP2. It is configured to include. Such a switching element SW may be formed of a thin film transistor.

The first subpixel SP1 includes a plurality of first common electrodes CE1, a plurality of first pixel electrodes PE1, and a first thin film transistor T1.

The plurality of first common electrodes CE1 are formed to be spaced apart at predetermined intervals so as to be connected to the first common voltage line VCL1. In this case, the plurality of first common electrodes CE1 is formed in a straight form (−). The first common voltage Vcom1 is supplied to the plurality of first common electrodes CE1 from the first common voltage line VCL1.

The plurality of first pixel electrodes PE1 are formed between the plurality of first common electrodes CE1 to be parallel to the plurality of first common electrodes CE1 at predetermined intervals. In this case, the plurality of first pixel electrodes PE1 may be formed in a straight form (−). The two-dimensional data voltage or the three-dimensional data voltage is supplied to the plurality of first pixel electrodes PE1 through the first thin film transistor T1.

The first thin film transistor T1 is switched according to the first gate signal supplied to the first gate line 1GL1 to receive a two-dimensional data voltage or a three-dimensional data voltage supplied to the data line DL. It is supplied to (PE1). To this end, the first thin film transistor T1 may include a gate electrode connected to the first gate line 1GL1, a source electrode connected to the data line DL, and a drain electrode connected to the plurality of first pixel electrodes PE1. It is configured to include. The gate electrode of the first thin film transistor T1 is formed to protrude from the first gate line 1GL1.

The first subpixel SP1 displays the 2D image using the 2D data voltage and the first common voltage in the 2D display mode, or the 3D data voltage and the first common voltage in the 3D display mode. Display a 3D image using.

The first subpixel SP2 includes a plurality of second common electrodes CE2, a plurality of second pixel electrodes PE2, a second thin film transistor T2, and a third thin film transistor T3.

The plurality of second common electrodes CE2 are formed to be spaced apart at predetermined intervals so as to be connected to the first common voltage line VCL1. In this case, the plurality of second common electrodes CE2 is formed in a straight form (−). The first common voltage Vcom1 is supplied to the plurality of second common electrodes CE2 from the first common voltage line VCL1.

The plurality of second pixel electrodes PE2 are formed between the plurality of second common electrodes CE2 to be parallel to the plurality of second common electrodes CE2 at predetermined intervals. In this case, the plurality of second pixel electrodes PE2 is formed in a straight form (−). The two-dimensional data voltage or the three-dimensional data voltage is supplied to the plurality of second pixel electrodes PE2 through the second thin film transistor T2.

The second thin film transistor T2 is switched according to the first gate signal supplied to the first gate line 1GL1 to receive a two-dimensional data voltage or a three-dimensional data voltage supplied to the data line DL. It is supplied to (PE2). To this end, the second thin film transistor T2 may include a gate electrode connected to the first gate line 1GL1, a source electrode connected to the data line DL, and a drain electrode connected to the plurality of second pixel electrodes PE2. It is configured to include. Here, the gate electrode of the second thin film transistor T2 is formed to protrude from the first gate line 1GL1. In this case, the gate electrodes of the first and second thin film transistors T1 and T2 protrude from the first gate line 1GL1 so as to be shared by the first and second thin film transistors T1 and T2.

The third thin film transistor T3 is switched according to the second gate signal supplied to the second gate line 2GL1 to receive the second common voltage Vcom2 supplied from the switching element SW. Supplies). To this end, the third thin film transistor T3 is connected to a gate electrode connected to the second gate line 2GL1, a source electrode connected to the drain electrode of the switching element SW, and a plurality of second pixel electrodes PE2. It is configured to include a drain electrode.

The display panel 100 may further include a dummy line (not shown) formed to be parallel to the second gate line 2GL1 and connected to the drain electrode of the switching device SW. In this case, the source electrode of the third thin film transistor T3 formed in each of the second subpixels SP2 is connected to the dummy line. Accordingly, the third thin film transistor T3 is switched according to the second gate signal to supply the second common voltage Vcom2 supplied through the switching element SW and the dummy line to the plurality of second pixel electrodes PE2. do.

The second subpixel SP2 displays the same two-dimensional image as the two-dimensional image displayed on the first subpixel SP1 using the two-dimensional data voltage and the first common voltage in the two-dimensional display mode. On the other hand, the second subpixel SP2 displays a black image by using the first and second common voltages Vcom1 and Vcom2 in the 3D display mode, thereby displaying 3 displayed on the first subpixel SP1 vertically adjacent to each other. Separate dimensional images. For example, in the 3D display mode, the first subpixel SP1 adjacent to the upper side of the second subpixel SP2 displays the left eye image of the 3D image, and is adjacent to the lower side of the second subpixel SP2. The first subpixel SP1 displays the right eye image of the 3D image. Accordingly, in the 3D display mode, the second subpixel SP2 separates the left eye image and the right eye image displayed on the upper and lower sides by displaying the black image.

The plurality of pixels P includes the first and second subpixels SP1 and SP2 that are adjacent to each other in the vertical direction, and are arranged in the first and second subpixels SP1 and SP2 in the two-dimensional display mode. The two-dimensional image is simultaneously displayed, while in the three-dimensional display mode, the three-dimensional image is displayed on the first subpixel SP1 and the black image is displayed on the second subpixel SP2. Accordingly, the first and second subpixels SP1 and SP2 have different area ratios in order to improve the aperture ratio of the pixel P to improve the brightness of the 2D image and to improve the image quality of the 3D image. It is formed to. For example, it is preferable that the area of the first subpixel SP1 is formed to be relatively larger than the second subpixel SP2. In this case, the area of the second subpixel SP2 may be optimized within a range capable of preventing crosstalk by separating the left eye image and the right eye image through the black image.

Meanwhile, in the above-described first and second subpixels SP1 and SP2, the data line DL, the plurality of first and second common electrodes CE1 and CE2, and the plurality of first and second pixel electrodes PE1 are described. , PE2) has been described as being formed in a straight form (-), but is not limited to this may be formed in various forms. For example, each of the data line DL, the plurality of first and second common electrodes CE1 and CE2, and the plurality of first and second pixel electrodes PE1 and PE2, according to an embodiment of the present disclosure, As shown in FIG. 3, it may be formed to have a curved shape (<). Similarly, the mode driving signal line MDSL and the second common voltage line VCL2 may also be formed to include a curved shape (<).

Meanwhile, the display panel 100 described above includes a left eye retarder (not shown) for changing an optical axis of a left eye image in a 3D display mode so that a viewer can recognize a 3D image, and a right eye for changing an optical axis of a right eye image. It further comprises a dragon retarder (not shown). Here, the left eye and right eye retarders may be formed on the substrate or the film and disposed on the display panel 100 or on an upper polarizer (not shown) attached to the display panel 100.

The left eye and right eye retarders are alternately formed to have a stripe shape along the length direction of the gate line GL. Accordingly, the left eye retarder is formed to overlap the plurality of pixels P displaying the left eye image of the 3D image to change the optical axis of the left eye image displayed on the plurality of pixels P, and the right eye retarder The optical axis of the right eye image displayed on the plurality of pixels P is formed to overlap the plurality of pixels P for displaying the right eye image of the 3D image.

In FIG. 1, the common voltage generator 200 generates a first common voltage Vcom1 using an input power Vin input from an external source, and forms a first common voltage line VCL1 formed on the display panel 100. Supply. In addition, the common voltage generator 200 generates a second common voltage Vcom2 by using the input power source Vin and supplies it to the second common voltage line VCL2 formed in the display panel 100. In this case, the second common voltage Vcom2 may be a DC voltage having the same voltage level as the first common voltage Vcom1.

The timing controller 300 generates a mode driving signal corresponding to the 2D display mode or the 3D display mode, and generates 2D image data according to the 2D display mode or 3D image data according to the 3D display mode. do. In addition, the timing controller 300 generates timing control signals GCS and DCS for controlling the driving timing of the gate driving circuit unit 400 and the data driving circuit unit 400. To this end, the timing controller 400 includes a mode driving signal generator 310, a data processor 320, and a timing control signal generator 330, as shown in FIG. 4.

The mode driving signal generator 310 generates a mode driving signal MDS corresponding to the two-dimensional display mode or the three-dimensional display mode according to the input data Idata input from the outside, or the mode driving signal according to the user's input. (MDS). At this time, as shown in FIG. 5, the mode driving signal MDS has a first logic state Low for turning off the above-described switching element SW in the two-dimensional display mode, while the three-dimensional display is performed. The mode has a second logic state High for turning on the switching element SW described above.

The data processor 320 generates 2D image data 2D_RGB or 3D image data 3D_RGB based on the input data Idata. In this case, the data processor 320 generates 2D image data 2D_RGB or 3D image data 3D_RGB according to an input method of the mode driving signal MDS or the input data Idata.

In detail, the data processor 320 generates the 2D image data 2D_RGB by aligning the input data Idata to be suitable for driving the display panel 100 in the 2D display mode, and generates the generated 2D image data ( 2D_RGB) is supplied to the data driving circuit unit 500.

On the other hand, the data processor 320 converts the input data Idata into 3D image data 3D_RGB and also converts the 3D image to fit the pixel P set in the display panel 100 in the 3D display mode. The image data 3D_RGB is aligned with the left eye image data and the right eye image data in units of horizontal lines, and the aligned left eye image data and the right eye image data are supplied to the data driver circuit 500 so as to be alternated in units of horizontal lines.

The timing control signal generator 330 may include a gate using a timing synchronization signal TSS such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable DE, and a clock DCLK. The gate control signal GCS for controlling the driving timing of the driving circuit unit 400 and the data control signal DCS for controlling the driving timing of the data driving circuit 500 are generated. The gate control signal GCS may be a gate start pulse, a plurality of gate clock signals, or the like. The data control signal DCS may be a source start pulse, a source sampling clock, a source output enable, a polarity control signal POL, or the like.

The gate driving circuit unit 400 generates first and second gate signals sequentially shifted according to the gate control signal GCS supplied from the timing controller 300, and illustrates the generated first and second gate signals. As shown in FIG. 6A, the plurality of first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 are sequentially supplied.

Meanwhile, the gate driving circuit unit 400 simultaneously generates the first and second gate signals according to the gate control signal GCS supplied from the timing controller 300, and generates the generated first and second gate signals, FIG. 6B. As shown in FIG. 2, the first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 are simultaneously supplied. At this time, the first and second gate signals simultaneously generated are shifted in units of the first and second gate lines 1GL1 and 2GL1.

The data driving circuit unit 500 may provide a data voltage corresponding to the two-dimensional data 2D_RGB or the three-dimensional data 3D_RGB supplied from the timing controller 300 according to the data control signal DCS supplied from the timing controller 300. Vdata) is generated, and the generated data voltage Vdata is supplied to the data line DL to be synchronized with the first gate signal. That is, the data driving circuit unit 500 sequentially latches 2D data (2D_RGB) or 3D data (3D_RGB), and then latches the latched 2D data (2D_RGB) or 3D data (3D_RGB) in analog data voltage. The data is converted to Vdata and supplied to the data line DL. Here, in the 3D display mode, the data driving circuit unit 500 alternately generates the left eye data voltage and the right eye data voltage in units of horizontal sections corresponding to the source output enable of the data control signal DCS, thereby generating a data line DL. To feed.

On the other hand, the stereoscopic image display apparatus according to an embodiment of the present invention is disposed on the back of the display panel 100 further comprises a backlight unit (not shown) for irradiating light to the display panel 100. Accordingly, the display panel 100 adjusts the transmittance of light emitted from the backlight unit by using the data voltage Vdata and the common voltages Vcom1 and Vcom2 described above, thereby displaying a two-dimensional image or a three-dimensional image according to a display mode. And a black image.

The stereoscopic image display apparatus according to the embodiment of the present invention improves the aperture ratio of the pixel P by forming the first and second subpixels SP1 and SP2 in each pixel P displaying an image, thereby improving two-dimensional display. In addition to improving the luminance of the image, the image quality of the 3D image may be improved. That is, according to the present invention, the same two-dimensional image is displayed on the first and second subpixels SP1 and SP2 in the two-dimensional display mode, thereby increasing the aperture ratio of the pixel P and increasing the luminance of the two-dimensional image. have. In addition, the present invention displays a three-dimensional image on the first subpixel SP1 in a three-dimensional display mode and simultaneously displays a black image on the second subpixel SP2 to display the three-dimensional image adjacently through the black image. The image quality of the 3D image may be improved by separating the left eye image and the right eye image.

Meanwhile, in the above description, the switching element SW, the mode driving signal line MDSL, and the second common voltage line VCL2 are described as being formed in the non-display area of the display panel 100, but the present invention is not limited thereto. Instead, as illustrated in FIG. 7A or 7B, the pixel P may be included in each pixel P. When the switching element SW is formed in each pixel P, deterioration of the switching element SW can be prevented.

8A and 8B are waveform diagrams schematically illustrating a method of driving a stereoscopic image display apparatus according to a first embodiment of the present invention.

8A and 8B will be described with reference to FIGS. 1 and 2 schematically illustrating a driving method of a stereoscopic image display apparatus according to a first embodiment of the present invention.

First, in the two-dimensional display mode, as shown in FIG. 8A, the display panel 100 includes the mode driving signal MDS in the first logic state Low, and the same first and second common voltages Vcom1,. Vcom2) is supplied. Accordingly, the switching element SW formed in the display panel 100 is maintained in the off state or turned off according to the mode driving signal MDS of the first logic state Low.

Thereafter, the first and second gate signals are sequentially supplied from the gate driver circuit 400 to the plurality of first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 formed in the display panel 100. . In synchronization with this, the two-dimensional data voltage Vdata corresponding to the two-dimensional data 2D_RGB is supplied from the data driving circuit unit 500 to the plurality of data lines DL formed on the display panel 100.

Accordingly, the first subpixel SP1 of each pixel P is supplied through the first thin film transistor T1 which is turned on by the first gate signal supplied to the first gate lines 1GL1 and 1GL2. A second thin film transistor T2 in which a two-dimensional image corresponding to the two-dimensional data voltage Vdata is displayed, and at the same time, the second subpixel SP2 of each pixel P is turned on by the first gate signal. A two-dimensional image corresponding to the two-dimensional data voltage Vdata supplied through the display is displayed. At this time, the third thin film transistor T2 formed in the second subpixel SP2 of each pixel P is turned on by the second gate signal. However, since the switching element SW is off, any voltage is applied to the second subpixel SP2. It is not supplied to the pixel electrode PE2.

Accordingly, in the two-dimensional display mode, each of the first and second subpixels SP1 and SP2 of each pixel P uses the two-dimensional data voltage Vdata and the first common voltage Vcom1 to generate a two-dimensional image. Will be displayed.

On the other hand, in the 3D display mode, as shown in FIG. 8B, the display panel 100 includes the mode driving signal MDS in the second logic state High and the same first and second common voltages Vcom1. , Vcom2). Accordingly, the switching element SW formed on the display panel 100 is turned on according to the mode driving signal MDS of the second logic state High, and thus the second common voltage Vcom2 is applied to each pixel P. It supplies to 2nd subpixel SP2.

Thereafter, the first and second gate signals are sequentially supplied from the gate driver circuit 400 to the plurality of first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 formed in the display panel 100. . In synchronization with this, the left eye image data Ldata and the right eye image data Rdata of the 3D data 2D_RGB in the horizontal section unit are included in the plurality of data lines DL formed on the display panel 100. The left eye data voltage Vdata and the right eye data voltage Vdata corresponding to each are alternately supplied.

Accordingly, the first subpixel SP1 of each pixel P is supplied through the first thin film transistor T1 which is turned on by the first gate signal supplied to the first gate lines 1GL1 and 1GL2. A second thin film transistor T2 which displays a 3D image corresponding to the left eye or right eye data voltage Vdata, and at the same time the second subpixel SP2 of each pixel P is turned on by the first gate signal. The 3D image corresponding to the left eye or right eye data voltage Vdata supplied through FIG. Here, the second subpixel SP2 of each pixel P displays the 3D image only while the first gate signal is supplied, and then moves to the second gate lines 2GL1 and 2GL2 to be shifted to the first gate signal. The second thin film transistor T3 is turned on by the supplied second gate signal so that the second thin film transistor T3 is supplied to the second pixel electrode PE2 through the switching element SW and the third thin film transistor T3. The black image is displayed by the common voltage Vcom2. That is, the second subpixel SP2 is second common by the first common voltage Vcom1 supplied to the second common electrode CE2 and the second common voltage Vcom2 supplied to the second pixel electrode PE2. As the voltage levels of the electrode CE2 and the second pixel electrode PE2 become equal to each other, a black image is displayed.

Therefore, in the 3D display mode, the first subpixel SP1 of each pixel P displays the 3D image using the left eye or right eye data voltage Vdata and the first common voltage Vcom1. The second subpixel SP2 of each pixel P displays the black image using the first and second common voltages Vcom1 and Vcom2.

9A and 9B are waveform diagrams schematically illustrating a method of driving a stereoscopic image display apparatus according to a second embodiment of the present invention.

9A and 9B will be described in brief with reference to FIGS. 1 and 2, which illustrate a method of driving a stereoscopic image display apparatus according to a second embodiment of the present invention.

First, in the two-dimensional display mode, as shown in FIG. 9A, the display panel 100 includes the mode driving signal MDS in the first logic state Low, and the same first and second common voltages Vcom1,. Vcom2) is supplied. Accordingly, the switching element SW formed in the display panel 100 is maintained in the off state or turned off according to the mode driving signal MDS of the first logic state Low.

Thereafter, the first and second gate signals are simultaneously supplied from the gate driving circuit unit 400 to the plurality of first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 formed in the display panel 100. In this case, the first and second gate signals are simultaneously shifted in units of the first and second gate lines 1GL and 2GL. In synchronization with this, the two-dimensional data voltage Vdata corresponding to the two-dimensional data 2D_RGB is supplied from the data driving circuit unit 500 to the plurality of data lines DL formed on the display panel 100.

Accordingly, the first subpixel SP1 of each pixel P is supplied through the first thin film transistor T1 which is turned on by the first gate signal supplied to the first gate lines 1GL1 and 1GL2. A second thin film transistor T2 in which a two-dimensional image corresponding to the two-dimensional data voltage Vdata is displayed, and at the same time, the second subpixel SP2 of each pixel P is turned on by the first gate signal. A two-dimensional image corresponding to the two-dimensional data voltage Vdata supplied through the display is displayed. At this time, the third thin film transistor T2 formed in the second subpixel SP2 of each pixel P is turned on by the second gate signal. However, since the switching element SW is off, any voltage is applied to the second subpixel SP2. It is not supplied to the pixel electrode PE2.

Accordingly, in the two-dimensional display mode, each of the first and second subpixels SP1 and SP2 of each pixel P uses the two-dimensional data voltage Vdata and the first common voltage Vcom1 to generate a two-dimensional image. Will be displayed.

On the other hand, in the 3D display mode, as shown in FIG. 9B, the display panel 100 includes the mode driving signal MDS in the second logic state High, and the same first and second common voltages Vcom1. , Vcom2). Accordingly, the switching element SW formed on the display panel 100 is turned on according to the mode driving signal MDS of the second logic state High, and thus the second common voltage Vcom2 is applied to each pixel P. It supplies to 2nd subpixel SP2.

Thereafter, the first and second gate signals are simultaneously supplied from the gate driving circuit unit 400 to the plurality of first and second gate lines 1GL1, 2GL1, 1GL2, and 2GL2 formed in the display panel 100. In this case, the first and second gate signals are simultaneously shifted in units of the first and second gate lines 1GL and 2GL. In synchronization with this, the left eye image data Ldata and the right eye image data Rdata of the 3D data 2D_RGB in the horizontal section unit are included in the plurality of data lines DL formed on the display panel 100. The left eye data voltage Vdata and the right eye data voltage Vdata corresponding to each are alternately supplied.

Accordingly, the first subpixel SP1 of each pixel P is supplied through the first thin film transistor T1 which is turned on by the first gate signal supplied to the first gate lines 1GL1 and 1GL2. While the 3D image corresponding to the left eye or right eye data voltage Vdata is displayed, the second subpixel SP2 of each pixel P is provided with the second gate signal supplied to the second gate lines 2GL1 and 2GL2. The third thin film transistor T3 is turned on by the second common voltage Vcom2 supplied to the second pixel electrode PE2 through the turned-on switching element SW and the third thin film transistor T3. The black image is displayed. That is, the second subpixel SP2 is second common by the first common voltage Vcom1 supplied to the second common electrode CE2 and the second common voltage Vcom2 supplied to the second pixel electrode PE2. As the voltage levels of the electrode CE2 and the second pixel electrode PE2 become equal to each other, a black image is displayed.

Therefore, in the 3D display mode, the first subpixel SP1 of each pixel P displays the 3D image using the left eye or right eye data voltage Vdata and the first common voltage Vcom1. The second subpixel SP2 of each pixel P displays the black image using the first and second common voltages Vcom1 and Vcom2.

The driving method of the stereoscopic image display apparatus according to the embodiments of the present invention displays a 2D image on the first and second subpixels SP1 and SP2 of each pixel P in the 2D display mode. In the three-dimensional display mode, the pixel P is displayed by displaying a three-dimensional image on the first subpixel SP1 of each pixel P and displaying a black image on the second subpixel SP2 of each pixel P. By improving the aperture ratio of the 3D image, the luminance of the 2D image can be improved and the image quality of the 3D image can be improved.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: display panel 200: common voltage generator
300: timing controller 400: gate driving circuit unit
500: data driving circuit unit 310: mode driving signal generation unit
320: data processor 330: timing control signal generator

Claims (14)

A display panel having pixels for displaying a two-dimensional image in accordance with a two-dimensional display mode and displaying a three-dimensional image in accordance with a three-dimensional display mode,
The pixel includes:
A first subpixel configured to display the 2D image in the 2D display mode and to display the 3D image in the 3D display mode; And
And a second subpixel configured to display the same two-dimensional image as the first subpixel in the two-dimensional display mode, and to display a black image in the three-dimensional display mode. The method of claim 1,
The display panel includes:
A first gate line formed between the first and second subpixels to supply a first gate signal to the first and second subpixels;
A second gate line formed adjacent to the second subpixel to supply a second gate signal to the second subpixel;
A data line intersecting the first and second gate lines to supply a two-dimensional data voltage according to the two-dimensional display mode or a three-dimensional data voltage according to the three-dimensional display mode to the first and second subpixels. ;
A first common voltage line for supplying a first common voltage to the first and second subpixels;
A second common voltage line for supplying a second common voltage to the second subpixel;
A mode driving signal line supplied with a mode driving signal corresponding to the two-dimensional display mode or the three-dimensional display mode; And
And switching according to the mode driving signal to supply the second common voltage to the second subpixel such that the black image is displayed on the second subpixel in the 3D display mode. Stereoscopic image display device. The method of claim 1,
The pixel includes:
A first gate line formed between the first and second subpixels to supply a first gate signal to the first and second subpixels;
A second gate line formed adjacent to the second subpixel to supply a second gate signal to the second subpixel;
A data line intersecting the first and second gate lines to supply a two-dimensional data voltage according to the two-dimensional display mode or a three-dimensional data voltage according to the three-dimensional display mode to the first and second subpixels. ;
A first common voltage line for supplying a first common voltage to the first and second subpixels;
A second common voltage line for supplying a second common voltage to the second subpixel;
A mode driving signal line supplied with a mode driving signal corresponding to the two-dimensional display mode or the three-dimensional display mode; And
And switching according to the mode driving signal to supply the second common voltage to the second subpixel such that the black image is displayed on the second subpixel in the 3D display mode. Stereoscopic image display device. The method according to claim 2 or 3,
The second subpixel is,
Displaying the 2D image according to the first common voltage and the 2D data voltage in the 2D display mode,
And displaying the black image according to the same first and second common voltages in the three-dimensional display mode. The method according to claim 2 or 3,
The first subpixel is,
A plurality of first common electrodes formed at predetermined intervals to be connected to the first common voltage line and supplied with the first common voltage;
A plurality of first pixel electrodes formed between the plurality of first common electrodes; And
And a first thin film transistor configured to switch according to the first gate signal to supply the two-dimensional data voltage or the three-dimensional data voltage to the plurality of first pixel electrodes. The method of claim 5, wherein
The second subpixel is,
A plurality of second common electrodes formed at predetermined intervals so as to be connected to the first common voltage line;
A plurality of second pixel electrodes formed between the plurality of second common electrodes;
A second thin film transistor switched in accordance with the first gate signal to supply the two-dimensional data voltage or the three-dimensional data voltage to the plurality of second pixel electrodes; And
And a third thin film transistor configured to switch according to the second gate signal to supply the second common voltage supplied from the switching element to the second pixel electrode. The method according to claim 6,
And the first and second thin film transistors share a gate electrode formed on the first gate line. The method according to claim 2 or 3,
A timing for generating the mode driving signal corresponding to the two-dimensional display mode or the three-dimensional display mode and generating two-dimensional image data according to the two-dimensional display mode or three-dimensional image data according to the three-dimensional display mode. Control unit;
A gate driving circuit unit which generates the first and second gate signals and sequentially supplies the first and second gate signals to the first and second gate lines under the control of the timing controller; And
Under the control of the timing controller, the 2D image data is converted into the 2D data voltage or the 3D image data is converted into the 3D data voltage, and the converted data voltage is synchronized with the first gate signal. And a data driving circuit unit for supplying the data line. A display panel having pixels for displaying a two-dimensional image in accordance with a two-dimensional display mode and displaying a three-dimensional image in accordance with a three-dimensional display mode,
The pixel includes:
In the two-dimensional display mode to display the two-dimensional image by using a two-dimensional data voltage and a first common voltage,
In the 3D display mode, a 3D image is displayed using a 3D data voltage and the first common voltage, and a black image is displayed using the second common voltage and the first common voltage which are the same as the first common voltage. And displaying the stereoscopic image display device. The method of claim 9,
The pixel includes:
A first subpixel configured to display the 2D image in the 2D display mode and to display the 3D image in the 3D display mode; And
And a second subpixel configured to display the same 2D image as the first subpixel in the 2D display mode and to display the black image in the 3D display mode. Displaying a 2D image on the pixel using the 2D data voltage and the first common voltage according to the 2D display mode; And
According to the 3D display mode, a 3D image is displayed using a 3D data voltage and the first common voltage, and a black image is displayed using the second common voltage and the first common voltage which are the same as the first common voltage. And driving the stereoscopic image display apparatus. The method of claim 11,
The displaying of the 2D image may include:
Supplying a first gate signal to first and second subpixels commonly connected to the first gate line;
And displaying the two-dimensional image on the first and second subpixels by supplying the two-dimensional data voltage to the first and second subpixels so as to be synchronized with the first gate signal. Method of driving a stereoscopic image display device. The method of claim 11,
The displaying of the 3D image may include:
Supplying a first gate signal to a first gate line commonly connected to the first and second subpixels;
Displaying the three-dimensional image on the first and second subpixels by supplying the three-dimensional data voltage to the first and second subpixels so as to be synchronized with the first gate signal;
Supplying a second gate signal to a second gate line connected to the second subpixel; And
And displaying the black image on the second subpixel by supplying the second common voltage to the second subpixel according to the second gate signal. The method of claim 11,
The displaying of the 3D image may include:
Supplying a first gate signal to first and second subpixels commonly connected to a first gate line and simultaneously supplying a second gate signal to a second gate line connected to the second subpixel; And
The 3D image voltage is supplied to the first and second subpixels so as to be synchronized with the first gate signal to display the 3D image on the first subpixel, and simultaneously with the second gate signal. And supplying a common voltage to the second subpixel to display the black image on the second subpixel.

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