JP2009217142A - Liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of reducing cross talk when displaying a plurality of screens by means of the time division drive. <P>SOLUTION: The liquid display device includes: a display panel DP arranged in a matrix with liquid crystal pixels PX constituted using OCB mode liquid crystals; a plurality of gate lines Y for supplying gate signals for controlling a plurality of switching elements W arranged along the line of the liquid crystal pixels and connected to the liquid crystal pixel of each corresponding line; a light control means 14 for switching a plurality of light sources BL illuminating the display panel by time division so as to emit light to a plurality of directions; and a display control means 10 for displaying respective gradation image and non-video image for a plurality of directions by time shearing, wherein the driving sequence of the gate signal which is supplied sequentially to the gate line when displaying the non-video image is different from the driving sequence of the gate signal when displaying the gradation image. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device capable of displaying a plurality of screens having different directivities by time-division driving, and more particularly to a liquid crystal display device with reduced video crosstalk.

Liquid crystal display devices are widely used as display devices for personal computers, portable information terminals, televisions, car navigation systems, and the like by taking advantage of features such as light weight, thinness, and low power consumption.
This liquid crystal display device normally displays one two-dimensional information. However, there is a proposal for a liquid crystal display device that can display three-dimensional display or screens with different directivities simultaneously on the same screen. . For example, a two-screen display device in which the images seen in the driver's seat and the passenger seat are different for in-vehicle use, and a three-dimensional display device that performs stereoscopic display by displaying a right-eye image and a left-eye image, respectively, have been proposed. .

A parallax barrier method is known as a technique that enables such display (see, for example, Patent Documents 1 and 2).
FIG. 13 is a conceptual diagram of the parallax barrier method. In the liquid crystal panel DP, pixels for the right direction and pixels for the left direction are individually formed. Then, from the oblique direction, the parallax barrier layer 51 is formed so that one of the lights that are transmitted through each of the pixels and emitted can be observed. A lenticular lens can be provided as the parallax barrier 51 to enhance directivity.

On the other hand, a method of switching the directivity of light by distributing light in the left and right directions by time division driving has been proposed.
As a result, a plurality of screens can be displayed without reducing the spatial resolution or the aperture ratio.
JP-A-5-107663 Japanese Patent Laid-Open No. 10-161061

  In this time-division driving method, a special driving method is required because two screens are displayed within a conventional period for displaying one screen. For example, since the time for writing and holding the video is shortened, the brightness of the panel is impaired as a result. For this reason, a driving timing that can ensure the lighting period of the backlight is necessary.

On the other hand, in this time-division driving method, it is necessary to solve the so-called video crosstalk problem. Video crosstalk is a phenomenon in which an image of the previous subframe (for example, for the left visual field) is displayed so as to overlap with an image of the next subframe (for example, for the right visual field).
The present invention has been made to solve this problem, and an object of the present invention is to provide a liquid crystal display device that reduces video crosstalk when a plurality of screens are displayed by time-division driving.

  In order to solve the above-described problems, the present invention provides a display panel in which liquid crystal pixels configured using OCB mode liquid crystals are arranged in a matrix, and liquid crystal pixels arranged in rows corresponding to the liquid crystal pixels. A plurality of gate lines for supplying gate signals for controlling a plurality of connected switching elements, and a light control means for switching a plurality of light sources for illuminating the display panel so that light is emitted in a plurality of directions in a time division manner, respectively. And a display control means for displaying the grayscale image and the non-video image on the display panel in a time-sharing manner for the plurality of directions, and sequentially supplying the non-video image to the gate line when displaying the non-video image. In the liquid crystal display device, the gate signal drive sequence is different from the gate signal drive sequence when displaying the gradation image.

  According to the present invention, it is possible to obtain a liquid crystal display device that reduces video crosstalk when a plurality of screens having different directivities are displayed by time-division driving.

[First Embodiment]
FIG. 1 is a diagram for explaining the outline of the present invention.
In the liquid crystal display device according to the present invention, the backlight BL is provided below the transmissive liquid crystal panel DP. The backlight BL includes a backlight BLa having a light source 52a and a backlight light guide plate 53a, and a backlight BLb having a light source 52b and a backlight light guide plate 53b. Here, when the light source 52a is turned on, light is emitted in the right direction of the figure by the backlight light guide plate 53a, and when the light source 52b is turned on, light is emitted in the left direction of the figure by the backlight light guide plate 53b. The

  When the two-screen display is performed, the light source 52a is turned on during the period when the right image is displayed on the liquid crystal panel DP, and the light source 52b is turned on while the light source is switched during the period when the left image is displayed on the liquid crystal panel DP. In this way, the left and right field-of-view images are sequentially displayed on the liquid crystal panel DP in a time-sharing manner, and the two images can be viewed from the left and right by switching the directivity of the light source that illuminates in synchronization therewith. In addition, stereoscopic display can be realized by controlling the directivity of light emitted from the backlight BL.

  FIG. 1 shows a schematic configuration of the liquid crystal display device. In an actual display device, an optical element that adjusts the directivity of light, such as a collimator lens and a prism film, can be appropriately provided between the liquid crystal panel DP and the backlight BL.

  By the way, in order to display different images by time-dividing one frame period, it is an indispensable condition to use a liquid crystal with a high response speed. For this reason, in the present embodiment, OCB mode (Optically Compensated Bend) liquid crystal having high-speed liquid crystal response required for moving image display and capable of realizing a wide viewing angle is used.

FIG. 2 is a diagram schematically showing a circuit configuration of the liquid crystal display device.
The liquid crystal display device includes a liquid crystal panel DP, a backlight BL (BLa, BLb) that illuminates the liquid crystal panel DP, and a display control circuit CNT that controls the liquid crystal panel DP and the backlight BL.

  The liquid crystal panel DP has a structure in which a liquid crystal layer 3 is sandwiched between an array substrate 1 and a counter substrate 2 which are a pair of electrode substrates. The liquid crystal layer 3 includes, as a liquid crystal material, liquid crystal that is previously transitioned from spray alignment to bend alignment and blocked by a voltage applied to reverse transition from bend alignment to spray alignment for normally white display operation, for example. .

  The display control circuit CNT controls the transmittance of the liquid crystal panel DP by the liquid crystal driving voltage applied from the array substrate 1 and the counter substrate 2 to the liquid crystal layer 3. The transition from the spray alignment to the bend alignment is obtained by applying a relatively large electric field to the liquid crystal by a predetermined initialization process performed by the display control circuit CNT when the power is turned on.

In the OCB mode liquid crystal display panel DP, the reason why the liquid crystal is in the spray orientation before the power is turned on is that the spray orientation is energetically more stable than the bend orientation in a state where no liquid crystal driving voltage is applied. Even if this liquid crystal alignment once transitions to bend alignment, it reversely transitions back to spray alignment when a voltage application state below the level at which the spray alignment energy and bend alignment energy antagonize or when no voltage is applied for a long period of time. It has the property of end up.
Conventionally, in order to prevent reverse transition from bend alignment to spray alignment, for example, a driving method is adopted in which a large voltage is applied to the liquid crystal for each frame for displaying an image of one frame. In a normally white liquid crystal display panel, since this voltage corresponds to a pixel voltage for black display, this is called black insertion driving.

  In the array substrate 1, a plurality of pixel electrodes PE are arranged in a substantially matrix shape on the transparent insulating substrate GL. In addition, a plurality of gate lines Y (Y1 to Ym) are arranged along the rows of the plurality of pixel electrodes PE, and a plurality of source lines X (X1 to Xn) are arranged along the columns of the plurality of pixel electrodes PE. .

  A plurality of pixel switching elements W are arranged in the vicinity of the intersection position of the gate line Y and the source line X. Each pixel switching element W is formed of a thin film transistor in which a gate is connected to the gate line Y and a source-drain path is connected between the source line X and the pixel electrode PE, and corresponds to when driven through the corresponding gate line Y. Conduction is established between the source line X and the corresponding pixel electrode PE.

  Each pixel electrode PE and common electrode CE is made of a transparent electrode material such as ITO, for example, and is covered with an alignment film AL and controlled to a liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE. A liquid crystal pixel PX is configured together with a pixel region that is a part of the pixel area.

  Each of the plurality of liquid crystal pixels PX has a liquid crystal capacitance CLC between the pixel electrode PE and the common electrode CE. The plurality of auxiliary capacitance lines C1 to Cm are each capacitively coupled to the pixel electrode PE of the liquid crystal pixel PX in the corresponding row to form an auxiliary capacitance Cs. The auxiliary capacitor Cs has a sufficiently large capacitance value with respect to the parasitic capacitance of the pixel switching element W.

The display control circuit CNT includes a gate driver YD, a source driver XD, a backlight driving unit LD, a driving voltage generation circuit 4, and a controller circuit 5.
The gate driver YD sequentially drives the plurality of gate lines Y1 to Ym so that the plurality of switching elements W are conducted in units of rows. The source driver XD outputs the pixel voltage Vs to the plurality of source lines X1 to Xn in a period in which the switching elements W in each row are turned on by driving the corresponding gate line Y. The backlight driver LD drives the backlight BL. The drive voltage generation circuit 4 generates a drive voltage for the liquid crystal panel DP. The controller circuit 5 controls the gate driver YD, the source driver XD, and the backlight driver LD.

  The drive voltage generation circuit 4 may include capacitive coupling drive including a compensation voltage generation circuit 6 that generates a compensation voltage Ve applied to the auxiliary capacitance line C. In addition, a gradation reference voltage generation circuit 7 that generates a predetermined number of gradation reference voltages VREF used by the source driver XD and a common voltage generation circuit 8 that generates a common voltage Vcom applied to the counter electrode CT are included.

  The controller circuit 5 includes a control circuit 10, a vertical timing control circuit 11, a horizontal timing control circuit 12, an image data conversion circuit 17, and a backlight control circuit 14.

The control circuit 10 generates a new synchronization signal SYNC (VSYNC, DE) based on the synchronization signal SYNC ′ input from the external signal source SS, and generates a signal for controlling the operation of each part of the display control circuit CNT.
The vertical timing control circuit 11 generates a control signal CTY for the gate driver YD and the like based on the synchronization signal SYNC (VSYNC, DE) input from the control circuit 10. The horizontal timing control circuit 12 generates a control signal CTX for the source driver XD based on the synchronization signal SYNC (VSYNC, DE) input from the control circuit 10.

  The image data conversion circuit 17 temporarily stores image data DI (left image data, right image data) input from the external signal source SS for a plurality of pixels PX, and outputs it to the source driver XD at a predetermined timing. The image data conversion circuit 17 generates black image data for performing black insertion conversion in addition to the above-described image data. The backlight control circuit 14 controls the backlight driver LD based on the control signal CTY output from the vertical timing control circuit 11.

  The image data DI includes a plurality of pixel data for a plurality of liquid crystal pixels PX, black image data as a non-video image, left image data, black image data as a non-video image in one frame period (vertical scanning period V), and It is updated 4 times with the right image data. The control signal CTY is supplied to the gate driver YD, and the control signal CTX is supplied to the source driver XD together with the pixel data DO obtained from the image data conversion circuit 17. The control signal CTY is used to cause the gate driver YD to sequentially drive the plurality of gate lines Y as described above, and the control signal CTX is obtained for each liquid crystal pixel PX of the image data conversion circuit 17 and output in series. The pixel data DO is assigned to a plurality of source lines X and used to cause the source driver XD to perform an operation for designating the output polarity.

The gate driver YD is configured using, for example, a shift register circuit in order to select the gate line Y. Here, the gate pulse is output four times in one frame period so that the black image data, the left image data, the black image data, and the right image data are read into the liquid crystal pixel PX for each gate line.
The display operation of the left image data, the right image data, and the black image data according to this embodiment will be described in detail later.

  The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 and converts the pixel data DO into pixel voltages Vs, respectively, and in parallel with the plurality of source lines X1 to Xn. Output to.

  The pixel voltage Vs is a voltage applied to the pixel electrode PE on the basis of the common voltage Vcom of the common electrode CE, and the polarity is inverted with respect to the common voltage Vcom so as to perform, for example, frame inversion driving and line inversion driving.

  The compensation voltage Ve is applied via the gate driver YD to the auxiliary capacitance line C corresponding to the gate line Y connected to the switching elements W when the switching elements W for one row are turned off. Capacitive coupling driving that compensates for variations in the pixel voltage Vs generated in the pixels PX for one row by the parasitic capacitance of the element W may be used.

  When the gate driver YD drives, for example, the gate line Y1 with the on-voltage to make all the pixel switching elements W connected to the gate line Y1 conductive, the pixel voltage Vs on the source lines X1 to Xn is changed to these pixel switching elements W. To the corresponding pixel electrode PE and one end of the auxiliary capacitor Cs.

  Further, the gate driver YD outputs the compensation voltage Ve from the compensation voltage generation circuit 6 to the auxiliary capacitance line C1 corresponding to the gate line Y1, and applies all the pixel switching elements W connected to the gate line Y1 to one horizontal scanning period. Immediately after being turned on, an off voltage that makes these pixel switching elements W non-conductive is output to the gate line Y1. The compensation voltage Ve reduces the electric charge drawn from the pixel electrode PE by these parasitic capacitances when these pixel switching elements W become non-conductive, and substantially cancels the fluctuation of the pixel voltage Vs, that is, the punch-through voltage ΔVp.

FIG. 3 is a diagram schematically showing the configuration of the source driver XD.
The source driver XD includes a shift register 21, a sampling / load latch 22, a digital / analog (D / A) conversion circuit 23, and an output buffer circuit 24.
The control signal CTX includes a horizontal start signal STH for controlling the start timing of fetching pixel data for one row and a horizontal clock signal CKH for shifting the horizontal start signal STX in the shift register 21.

  The shift register 21 shifts the horizontal start signal STH in synchronization with the horizontal clock signal CKH, and controls the timing at which the pixel data DO is sequentially serial-to-parallel converted. The sampling / load latch 22 sequentially latches the pixel data DO for the pixels PX for one line under the control of the shift register 21 and outputs them in parallel. The digital / analog (D / A) conversion circuit 23 converts the pixel data DO into an analog pixel voltage. The output buffer circuit 24 outputs the analog pixel voltage obtained from the D / A conversion circuit 23 to the source lines X1,. The D / A conversion circuit 23 is configured to refer to a plurality of gradation reference voltages VREF generated from the gradation reference voltage generation circuit 7. The gradation reference voltage generation circuit 7 switches the gradation reference voltage VREF for left image data, right image data, and black image data in response to a switching signal from the control circuit 10 in one frame period and outputs it. It doesn't matter if you do.

Next, the cause of video crosstalk will be described.
FIG. 4 is a time chart showing a method of driving a conventional liquid crystal display device. In this driving method, a left image display period and a right image display period are provided in one frame period, and pixel voltages for the left image and the right image are supplied to the liquid crystal pixels in each period. Further, since black insertion driving is employed, a black image is written during each display period.

The driving method will be described with reference to FIGS. As described above, the gate pulse for selecting the gate line Y output from the gate driver YD causes the black image data, the left image data, the black image data, and the right image data to be supplied to the liquid crystal pixel PX for each gate line. It is output four times in one frame period for reading.
The control signal CTY includes a start signal (image display start signal) STH, a clock signal, an output enable signal, and the like.

  The start signal (image display start signal) STH controls the display start timing of the black image, the left image, the black image, and the right image. The clock signal shifts the start signal STH in the shift register circuit. The output enable signal controls the output of drive signals to the gate lines Y1 to Ym that are sequentially or together selected by the shift register circuit corresponding to the holding position of the start signal STH.

On the other hand, the control signal CTX includes a start signal, a clock signal, a load signal, a polarity signal, and the like.
According to the description at the top of FIG. 4, the data L representing the left image and the data R representing the right image are input from the external signal source SS to the image data conversion circuit 17 and temporarily stored. . Then, the image data conversion circuit 17 generates display data B for the black image and stores it together with the data L and the data R.

  Next, the gate driver YD sequentially selects the gate lines Y1 to Ym for displaying a black image in the ¼ period of one frame period under the control of the control signal CTY, and the pixel switching elements W in each row are selected for one horizontal scanning period H. An on-voltage is supplied to the selection gate line Y as a drive signal for conducting. The input pixel data DI for one row is converted into black image display pixel data B for one row. One row of black image display pixel data B is output from the image data conversion circuit 17 in series. In the middle part of FIG. 4, the state in which the gate pulses are sequentially scanned in the black writing period is represented by black diagonal lines.

  The control circuit 10 outputs a switching signal to the gradation reference voltage generation circuit 7 in accordance with the timing when the black image display pixel data B is output from the image data conversion circuit 17. The gradation reference voltage generation circuit 7 switches the gradation reference voltage VREF for black image display and outputs it.

  The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data B into pixel voltages Vs, and supplies them to a plurality of source lines X1 to Xn. Output in parallel.

  Next, the left image display operation will be described. The gate driver YD is a drive that sequentially selects the gate lines Y1 to Ym for left image display in the ¼ period of one frame period under the control of the control signal CTY, and conducts the pixel switching elements W in each row for one horizontal scanning period H. An ON voltage is supplied to the selection gate line Y as a signal. The input pixel data DI for one row is converted into left image display pixel data L for one row. The left image display pixel data L for one row is output from the image data conversion circuit 17 in series. In the middle part of FIG. 4, the state in which the gate pulses are sequentially scanned in the video writing period is represented by black diagonal lines.

  The control circuit 10 outputs a switching signal to the gradation reference voltage generation circuit 7 in accordance with the timing at which the pixel data L is output from the image data conversion circuit 17. The gradation reference voltage generation circuit 7 switches the gradation reference voltage VREF for left image display and outputs it.

The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data L into pixel voltages Vs, respectively, and supplies them to a plurality of source lines X1 to Xn. Output in parallel.
In accordance with the left image display period, the control circuit 10 outputs a light on / off signal to the backlight control circuit 14 at a predetermined timing. The backlight control circuit 14 controls the lighting of the backlight BLb by driving the backlight driver LD to turn off the backlight BLa.
Next, a black image display operation following the left image display operation will be described. The gate driver YD is a drive that sequentially selects the gate lines Y1 to Ym for black image display in the ¼ period of one frame period under the control of the control signal CTY, and conducts the pixel switching elements W in each row for one horizontal scanning period H. An ON voltage is supplied to the selection gate line Y as a signal. The input pixel data DI for one row is converted into black image display pixel data B for one row. One row of black image display pixel data B is output from the image data conversion circuit 17 in series. In the middle part of FIG. 4, the state in which the gate pulses are sequentially scanned in the black writing period is represented by black diagonal lines.

  The control circuit 10 outputs a switching signal to the gradation reference voltage generation circuit 7 in accordance with the timing when the black image display pixel data B is output from the image data conversion circuit 17. The gradation reference voltage generation circuit 7 switches the gradation reference voltage VREF for black image display and outputs it.

  The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data B into pixel voltages Vs, and supplies them to a plurality of source lines X1 to Xn. Output in parallel.

  Next, the right image display operation will be described. The gate driver YD is a drive that sequentially selects the gate lines Y1 to Ym for the right image display in the ¼ period of one frame period under the control of the control signal CTY, and conducts the pixel switching elements W in each row for one horizontal scanning period H. An ON voltage is supplied to the selection gate line Y as a signal. The input pixel data DI for one row is converted into the right image display pixel data R for one row. The right image display pixel data R for one row is output in series from the image data conversion circuit 17. In the middle part of FIG. 4, the state in which the gate pulses are sequentially scanned in the video writing period is represented by black diagonal lines.

  The control circuit 10 outputs a switching signal to the gradation reference voltage generation circuit 7 in accordance with the timing at which the pixel data R is output from the image data conversion circuit 17. The gradation reference voltage generation circuit 7 switches the gradation reference voltage VREF for right image display and outputs it.

The source driver XD refers to a predetermined number of gradation reference voltages VREF supplied from the gradation reference voltage generation circuit 7 to convert the pixel data L into pixel voltages Vs, respectively, and supplies them to a plurality of source lines X1 to Xn. Output in parallel.
In accordance with the right image display period, the control circuit 10 outputs a light on / off signal to the backlight control circuit 14 at a predetermined timing. The backlight control circuit 14 controls the lighting of the backlight BLa by driving the backlight driver LD to turn off the backlight BLb.

FIG. 5 is a diagram illustrating video crosstalk.
Originally, an image representing two horizontal stripes is displayed in the left visual field, and an image representing the entire white color is displayed in the right visual field. However, since video crosstalk has occurred, an image obtained by synthesizing both images is displayed, and two horizontal stripes appear lightly in the image of the right field of view.

  By the way, in the above-described driving method, since black insertion driving is adopted, the image of the left visual field is reset by this black insertion, and video crosstalk should not occur. From this, one of the causes of video crosstalk is that the gate pulse time is shortened by displaying a plurality of images in one frame period, and as a result, the image reset by black insertion drive is insufficient. Conceivable.

  On the other hand, as another cause, it is considered that video crosstalk occurs due to the sense of the viewer such as an afterimage. However, even when the backlight BLb is turned off and the left image cannot be seen, video crosstalk occurs. Therefore, it is unlikely that the cause of the crosstalk is due to the viewer's senses such as afterimages. The liquid crystal molecular arrangement itself of the liquid crystal pixel PX is considered to cause crosstalk. Therefore, there is a high possibility that the reset of the image is insufficient.

  From the above consideration, as a measure for preventing the occurrence of video crosstalk, it is possible to change the driving method so that the reset by black insertion is sufficiently performed.

FIG. 6 is a time chart showing a driving method of the liquid crystal display device according to the present embodiment.
In this driving method, the gate pulse width for writing a black image is increased to ensure that the image is reset. The middle part of FIG. 6 shows that the width of the diagonal black line in the black writing period is thicker than the width of the diagonal black line in the video writing period, indicating that the gate pulse width is longer. .

FIG. 7 is a time chart schematically showing the gate pulse.
Conventionally, the pulse width of the gate pulse is a pulse width of one horizontal period (1H), but in this embodiment, it is expanded to a width of a plurality of horizontal periods. As a result of expanding the pulse width in this way, a plurality of gate lines Y are simultaneously selected at a certain point in time, but the pixel voltage Vs supplied from the source driver XD is black pixel data L and each gate line Y is selected. Is a common value. Therefore, this method does not cause a display problem.

  Note that the influence of video crosstalk can be reduced if the pulse width of the gate pulse is 2H or more, but it is preferably 5H or more in order to make the reduction effect remarkable. However, if all the gate pulses are overlapped, an instantaneous large current flows, so that a large power source capacity is required and the circuit load increases. For this reason, the overlapping gate pulses are 1/10 or less of the number of scanning lines, more preferably 1/12 or less, and it is necessary that one or more scanning lines are sequentially scanned.

  In this embodiment, since the gate pulse width is increased, a longer black writing period is required than in the prior art. That is, the lengths of the black writing period and the video writing period are different. Therefore, if the effective writing period can be long, the scanning speed in the black writing period may be faster than the scanning speed in the video writing period.

[Variation 1]
FIG. 8 is a time chart showing a driving method of the liquid crystal display device according to the variation of the present embodiment. In this driving method, a gate pulse for writing a black image is output again at a predetermined time interval so that the reset operation is enhanced. In the middle part of FIG. 8, diagonal black lines in the black writing period are represented in double.

FIG. 9 is a time chart schematically showing the gate pulse.
Conventionally, one gate pulse is output in one subframe period. In this embodiment, after a gate pulse is output once, a gate pulse is added and output when a plurality of horizontal periods (nH) have elapsed. To do. In this way, the black writing operation can be enhanced by executing the black insertion operation twice. Note that the number of gate pulses in one subframe period is not limited to two, and may be a plurality of times. As a result of increasing the number of gate pulses in this way, a plurality of gate lines Y are simultaneously selected at a certain point in time, but the pixel voltage Vs supplied from the source driver XD is black pixel data L. This value is common to the gate line Y. Therefore, this method does not cause a display problem.

  Note that the influence of video crosstalk can be reduced if the interval between the gate pulses is 1H or more, but it is preferably 4H or more in order to make the reduction effect remarkable.

  In this embodiment, since two gate pulses are output, a longer black writing period is required than in the prior art. Therefore, if the effective writing period can be long, the scanning speed in the black writing period may be faster than the scanning speed in the video writing period.

[Variation 2]
FIG. 10 is a time chart showing a driving method of the liquid crystal display device according to the variation of the present embodiment. In the first embodiment, from the relationship of the lighting timing of the backlight, it is considered that black writing becomes insufficient at the lower end portion of the panel in consideration of the response of the liquid crystal. In this variation of the driving method, the backlight is divided into, for example, up and down for example along the scanning order, and each is independently controlled to solve the problem.

When writing of the left image is started, the upper backlight BLb-1 is turned on. The backlight BLb-1 is turned off when a gate pulse rises on the gate line at the lower end of the panel in the subsequent black writing period and a predetermined period, for example, 1H elapses. On the other hand, when the left image is written up to the center of the panel, the lower backlight BLb-2 is turned on. The backlight BLb-2 continues to be lit even when a gate pulse is output to the gate line at the lower end of the panel in the subsequent black writing period and the gate pulse falls after a predetermined time has elapsed.
Therefore, in this variation, black writing does not become insufficient at the lower end of the panel due to the lighting timing of the backlight.

  Note that the method of driving the backlight by dividing it vertically is applicable not only when the pulse width of the gate pulse is expanded, but also when it is output following the gate pulse. Further, the number of divisions of the backlight may be divided into three or more along the scanning order.

The liquid crystal display device according to the present embodiment described above relates to a liquid crystal display capable of projecting images in two directions. As shown in FIG. 11, the images projected in the driver's seat and the passenger seat are for in-vehicle use. It may be a display to be changed, and as shown in FIG. 12, it may be used for a battle game with an arcade game machine, a portable game machine, or the like.
In addition, the liquid crystal display device according to the present invention may be used as a stereoscopic display device that alternately switches between right-eye and left-eye images.
In this embodiment, an example in which two screens are displayed by switching illumination in two directions has been described. However, the present invention is not limited to two directions, and the illumination is switched in multiple directions of three or more directions and three or more screens are displayed. The present invention can also be applied when displaying a large number of screens.

  In general, the liquid crystal display element introduces “alternating current” that prevents the accumulation of a DC electric field by switching the display polarity for each writing. In the case of the present invention, the driving is effectively performed at 120 Hz, but AC may be used at 60 Hz. If the A screen and the B screen are different from each other, there is a possibility that the display is synchronized with the DC. Therefore, 60 Hz alternating current is adopted so that alternating current can be realized on both the A screen and the B screen.

  Of course, this display device is not limited to 60 Hz. You may drive at 150 Hz effectively with an input waveform of 75 Hz. In that case, there is an advantage that flicker is further reduced.

Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.
Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

The figure explaining the outline | summary of this invention. 1 is a diagram schematically showing a circuit configuration of a liquid crystal display device. The figure which shows the structure of a source driver roughly. 6 is a time chart showing a method for driving a conventional liquid crystal display device. The figure showing video crosstalk. 4 is a time chart showing a driving method of the liquid crystal display device according to the present embodiment. The time chart which shows a gate pulse typically. The time chart which shows the drive method of the liquid crystal display device which concerns on a variation. The time chart which shows a gate pulse typically. The time chart which shows the drive method of the liquid crystal display device which concerns on a variation. The figure which shows the display which changes the image | video projected on a driver's seat and a passenger seat. The figure which shows a competitive game. The conceptual diagram of a parallax barrier system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Array substrate, 2 ... Opposite substrate, 3 ... Liquid crystal layer, 4 ... Driving voltage generation circuit, 5 ... Controller circuit, 7 ... Gradation reference voltage generation circuit, 10 ... Control circuit, 14 ... Backlight control circuit, YD ... Gate driver, DI ... Image data, DO, R, L, B ... Pixel data, XD ... Source driver, PE ... Pixel electrode, CE ... Common electrode, PX ... Liquid crystal pixel, DP ... Display panel, BL, BLa, BLb ... Backlight, CNT ... Display control circuit, X ... Source line, Y ... Gate line, W ... Switching element.

Claims (6)

A display panel in which liquid crystal pixels configured using OCB mode liquid crystal are arranged in a matrix;
A plurality of gate lines for supplying a gate signal for controlling a plurality of switching elements disposed along the row of the liquid crystal pixels and connected to the liquid crystal pixels in the corresponding row;
A light control means for switching a plurality of light sources for illuminating the display panel to emit light in a plurality of directions in a time-sharing manner;
Display control means for displaying each gradation image and non-video image on the display panel in a time-sharing manner for the plurality of directions,
A liquid crystal display device, wherein a drive sequence of the gate signal sequentially supplied to the gate lines when displaying the non-video image is different from a drive sequence of the gate signal when displaying the gradation image .   The liquid crystal display device according to claim 1, wherein a gate width of the gate signal when displaying the non-video image is larger than a gate width of the gate signal when displaying the gradation image.   3. The liquid crystal according to claim 2, wherein a gate width of the gate signal when displaying the non-video image is not less than five times a gate width of the gate signal when displaying the gradation image. Display device.   The liquid crystal display device according to claim 1, wherein a plurality of gate pulses are output at predetermined intervals as the gate signal for displaying the non-video image.   5. The liquid crystal display device according to claim 4, wherein the predetermined interval is at least four times the pulse width of the gate pulse. The plurality of light sources further includes a divided light source divided into at least two or more in a direction intersecting with the gate line of the display panel,
6. The split light source that illuminates the lower portion of the display panel continues illumination even after the drive sequence of the gate signal when displaying the non-video image is completed. 2. A liquid crystal display device according to item 1.

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