KR101931010B1 - Hermetically sealed package having stress reducing layer - Google Patents

Abstract

A wafer structure and a device and apparatus disposed thereon. A sealed package having a lead structure bonded to a wafer. The apparatus wafer includes: a substrate; A metal ring disposed on a surface portion of the substrate around the device, and a bonding material disposed on the metal ring. The first layer of the metal ring has a higher ductility than the ductility of the surface portion of the substrate and includes a stress relaxation buffer layer having a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The thermal expansion coefficient of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material.

Description

[0001] HELMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER [0002]

The present disclosure relates generally to electronic packaging, specifically microelectromechanical systems (MEMS) packaging.

Microelectromechanical systems (MEMS) are integrated microdevices or systems that combine electronic components and mechanical components, as is known in the art. MEMS devices can be fabricated, for example, using standard integrated circuit batch processing techniques. An exemplary application of a MEMS device includes sensing, controlling, and driving with a microscale. These MEMS devices may function individually or in multiple arrays to effect macro scale.

Many MEMS devices require a hermetically sealed environment to achieve maximum performance, as is known in the art. Such an environment may be a vacuum environment, a controlled pressure environment, or a controlled gas environment. The package environment also provides an optimal operating environment for the MEMS device and protection of the MEMS device. Examples of such MEMS devices include, but are not limited to, infrared MEMS such as a bolometer (sometimes referred to as a microbolometer), inertial MEMS such as gyros and accelerometers, and optomechanical Device. Conventionally, MEMS devices have been individually packaged in a commercially available package of vacuum after fabricating and cutting MEMS device wafers. However, the cost of packaging a MEMS device in a conventional metal or ceramic package can often be about 10 to 100 times the cost of manufacturing the device. This is particularly the case when a vacuum is required in the package.

Various types of infrared detectors have been developed over the years. Most include a substrate having a focal plane array, wherein the focal plane array includes a plurality of detector elements (detector devices) corresponding to each pixel. The substrate includes an integrated circuit and the integrated circuit is electrically coupled to the detector element and is generally known as a read out integrated circuit (ROIC), which integrates signals from each detector element and provides suitable signal control And is used to multiplex signals from the chip by processing.

The bolometer may need to be hermetically packaged in vacuum or other controlled environmental conditions for good performance, as in the case of any microelectromechanical (MEMS) device. Exemplary requirements for packaging the bolometer array include reliable hermetic seals that can maintain a high vacuum for extended periods, integration of the IR window material with good infrared transmission, and high yield / low cost packaging. Both the reliability and cost of the MEMS device depend on the selected encapsulation (packaging) technique. Packaging for MEMS-based bolometers can be done at the chip level or wafer level. A typical method of packaging in this example is to fabricate a protective IR-transparent cap wafer or window cap wafer (WCW), and to clean the wafer so that the wafer is cleaned with a device wafer or semiconductor To the exposed surface of the substrate. A cap wafer (sometimes referred to as a window or lead structure, as the case may be), when flipping the cap wafer over and bonding it to the device wafer, is described in U.S. Patent 5701008 (" Integrated infrared microlens and gas molecule grating in a vacuum package " Quot ;, inventor Ray et al., Dec. 23, 1997), the cavity provides sufficient clearance to receive and protect the MEMS device. 1 and 2, the package assembly is shown having a lead-out integrated circuit (ROIC) substrate 2 of semiconductor material (preferably silicon). The IR detector array 14 is located on the substrate 2 and includes a plurality of discrete detector elements (also referred to as pixels) 6. Although only a 5x6 rectangular array of detector pixels 6 is shown in Figure 2 in the detector region 10, a typical IR integrated circuit typically has a planar surface with a maximum of hundreds or even thousands, or even hundreds or even thousands of pixels 6 IR detector array. In the most common applications, IR detectors detect the intensity of IR radiation by sensing the temperature-induced rise in the heart, which is generally non-cooled and imparted to the detector by IR radiation. A typical example of a non-cooled IR detector is a vanadium oxide (VOx) microbolometer (MB), and a plurality of individual detectors are formed into one array on the ROIC substrate 2 by conventional semiconductor manufacturing processes. The MB array detects IR radiation by sensing IR-generated heat and is also referred to as a focal plane array (FPA) or a sensor chip assembly (SCA). The substrate 2 is an integrated circuit used to process signals generated by a bolometer. In this case, the bolometer is a microbridge resistor whose resistance changes when the temperature changes. The incident radiation changes the temperature of the microbridge. Although other semiconductor materials such as Si may be used, VOx is generally available and is a cost effective material used in commercial IR detection applications.

As described in the above referenced U. S. Patent No. 570,1008, a vacuum-sealed assembly includes a hermetic seal 8 surrounding the IR detector array to seal the detector array from the atmosphere. The seal 8 can be, for example, indium, gold-tin, or other solder, and the height of the seal is precisely controlled when placed on the substrate 2 or preferably on the wafer 10. The seal 8 supports the second substrate, the cap wafer, here the IR transmission window 10, for example silicon, and the wafer level at which the window wafer 10 is packaged has a thermal expansion coefficient compatible with FPA silicon Should have. The wafer 10 may include a gettering material (not shown) on a predetermined area of the surface of the wafer 10 having a predetermined surface area as described in the above-mentioned U.S. Patent No. 5,701,1008.

As is known in the art, wafer level packaging (WLP) has been developed to address the high packaging costs of MEMS by eliminating common packages. One such WLP package is described in U.S. Patent No. 6,521,477 entitled " Vacuum package fabrication of integrated circuit components ", inventor Gooch et al., Registered on February 18, 2003. In one WLP process, two wafers may be bonded together using a bonding material to create bonded wafers. For example, one of the wafers is a semiconductor (e.g., silicon) device wafer having a detector device in the detector region of the wafer and the detector region is disposed within the central interior region of the device wafer with a lead-out integrated circuit (ROIC) , The integrated circuit is bonded to the other wafers, the lead wafers, using a sealing metal ring disposed against the detector area of the device wafer. After forming the device on a semiconductor wafer, the wafer comprises a thin over-glass layer, for example silicon nitride or silicon oxynitride (SiON). (To serve as a substrate adhesion layer for the ROIC over glass), an intermediate layer of nickel (which serves as a diffusion barrier), followed by conventional photolithography to form a layer of gold to prevent oxide formation and improve solder bonding Process is used to form a seal ring metal (hereinafter referred to as "seal ring"). A similar series of layers is formed on the lead wafer that provides a mating surface for solder sealing between the device and the lead wafer. After formation of the seal ring, solder, for example 80% Au and 20% Sn, is applied to either the device or the lead wafer or both.

Although the WLP technique described above provides an effective package, the inventors have found that because of the difference in the coefficient of thermal expansion between the AuSn solder and the semiconductor device wafer, stress can be accumulated in the high stress region as shown in Fig. 3, The edge was found to contact the device or the ROIC wafer. Such stresses can cause undesired cracks in the over glass and substructure of the device or ROIC wafer as shown in FIG. Such cracks can lead to failure and destruction of metal interconnecting traces and interlayer dielectric layers (ILD) in the interlayer dielectric layer (ILD) of the ROIC.

Specifically, the present inventors have recognized that the seal ring metal stack (about 0.5 탆 thick) and the solder (up to 11 탆 thick) have a coincident edge in the prior art. As the solder cools below the melting temperature of ~ 280 ° C, the solder shrinks faster than the bottom seal ring and ROIC (solder CTE ~ 16 ppm, silicon CTE ~ 3 ppm) and solder becomes very hard (AuSn solder has high Young's modulus ), It can not be deformed to relieve stress. Due to the contraction of the solder layer, the solder joint edges tend to pull, which causes cracks and stress points (r) created at the edges of the joint. As the thickness of the titanium (Ti) portion of the lower portion of the seal ring increases, the solder remains pulled at the edge of the seal ring, which leads to stress points and thus has little effect on stress. An abrupt edge that reduces the stress on the local region on the ROIC surface by terminating the solder shot of the edge of the metal bonded to the ROIC surface and providing an intermediate layer, e. G., A stress relaxation buffer layer of titanium, It is terminated on the ROIC surface and is covered with many soft materials. Further, the present inventors have found that when the matching edge is removed, the stress relieving buffer layer is thickened in one embodiment, or thickening the lower titanium layer by thickening the titanium bonding material adhesive layer in another embodiment, But only when the edge is first removed.

According to the present disclosure, there is provided a structure, comprising: a substrate; A metal ring disposed on a surface portion of the substrate about a surface region of the substrate; A bonding material disposed on the metal ring and having an inner edge and an outer edge, the metal ring extending laterally beyond at least one of an inner edge and an outer edge of the bonding material.

In one embodiment, the first layer of the metal ring comprises a stress relaxation buffer layer disposed on a surface portion of the substrate, the first layer having a higher ductility than the ductility of the surface portion at a predetermined temperature, Wherein the stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the thermal expansion coefficient of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material.

 In one embodiment, the outer region of the upper surface of the metal ring includes a material that inhibits adhesion of the bonding material to the upper surface, and wherein the portion of the metal ring includes at least one of an inner edge and an outer edge of the bonding material Lt; / RTI >

 In one embodiment, a topsurface of the metal ring includes a bonding material masking layer, the bonding material being transferred through the window into the masking layer exposing a portion of the top surface of the metal layer, A portion is transferred onto the exposed portion of the top surface of the metal layer.

In one embodiment, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

In one embodiment, the substrate includes a lead, and the bonding material bonds the substrate to the lead.

The stress relaxation buffer layer effectively bonds to the substrate and is not wetted by the bonding material. The coefficient of thermal expansion of the stress relieving buffer layer is preferably in the middle between the CTE of the surface portion of the substrate bonded to the stress relaxation buffer layer and the CTE of the solder or the bonding material, and in the case of brittle materials such as SiON and silicon And has a characteristic of a soft material which is locally produced in a region of high stress without being broken. An exemplary stress relaxation buffer layer material is titanium.

With this arrangement, the stress generated between the substrate, for example, the semiconductor wafer and the adhesive layer is shifted from the point where the edge of the bonding material contacts the semiconductor wafer to the point where the edge of the bonding material contacts the stress relaxation buffer layer , Thus moving away from the semiconductor wafer and any associated over-glass or brittle substrate material. Therefore, the stress relieving buffer layer functions as a stress reducing layer, in which a region of high stress moves from a brittle over glass to a soft underlying layer.

Specifically, when using a solder having a high heat shrinkage ratio to bond and hermitically seal two wafers to form a package, the solder shrinks as it cools from the melting temperature, and the solder shrinks at the edge of the solder joint, Derive the stress level. The use of the stress relieving buffer layer (1) separates high stress areas at the edge of the solder joint from the underlying brittle semiconductor wafer, and has a higher ductility level than the ductility of the semiconductor wafer and a heat shrinkage Material of the stress relieving buffer layer. The stress relaxation buffer layer has a thermal expansion between the surface of the wafer and the solder layer and reduces the stress in the brittle wafer. Thus, the present disclosure allows high CTE solder or other bonding material to be integrated with the brittle over glass layer on the semiconductor structure. This process can also be used on device wafers, leads, or both.

"Annular shape" means and includes a shape including a space, which may be circular, rectangular, rectangular ellipsoidal, or may have irregular shape, e.g., serpentine or curved shape.

One or more embodiments of the present disclosure are described in the accompanying drawings and detailed description. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

1 is a schematic, cross-sectional view of a vacuum package of an IR detector array in accordance with the prior art;
Figure 2 is a schematic plan view of an IR detector array used in the assembly of Figure 1 according to the prior art;
3 is a cross-sectional view of the IR detector array of FIG. 2 taken along line 3-3 of FIG. 2 in accordance with the prior art;
Figure 4 is a cross-sectional top view of the hermetically sealed package according to the present disclosure taken along line 4-4 in Figure 5;
FIG. 5 is a cross-sectional elevational view of the package of FIG. 4 taken along line 5-5 in FIG. 4;
5A is an enlarged view of the cross-sectional elevation view of FIG. 5, taken by arrow 5A-5A in FIG. 5; FIG.
Figure 6 is a cross-sectional elevational view of a hermetically sealed package in accordance with another embodiment of the present disclosure;
6A is an enlarged view of the cross-sectional elevation view of FIG. 6, which is an enlarged view of FIG. 6, taken by way of arrows 6A-6A.
Like numbers refer to like elements throughout.

Referring to FIGS. 4 and 5, a hermetically sealed package 100 is shown for hermetically sealing the device 102. The package 100 includes a substrate 104 having a device 102 in a central region 106; Cap wafer 108 (Figure 5); And a metal ring 107DW is formed around the surface region 106 of the substrate 104. The metal ring 107DW includes a plurality of metal rings, 104 and the other metal ring 107CW is disposed on the surface of the cap wafer 108 around the central region 106. [ It should be understood that in some applications, the metal ring 107CW may not be needed. The metal ring 107DW is disposed in direct contact with the surface of the substrate 104 (specifically contacting directly on the over glass layer 116 of the substrate 104), as is clearly shown in Figure 5A, An annular stress relaxation buffer layer 109DW, and a seal ring structure 110DW (FIG. 5) on the upper surface of the annular stress relaxation buffer layer 109DW. The metal ring 107CW includes an annular stress relaxation buffer layer 109CW on the surface of the cap wafer 108 and a seal ring structure 110CW on the upper surface of the annular stress relaxation buffer layer 109CW around the central region 106 . The bonding material 118 is disposed between the two sealing ring structures 110DW and 110CW shown in Fig. Thus, as described in detail below, the annular stress relief buffer layer 109CW is the lower material of the annular seal structure 110CW, and the annular stress relief buffer layer 109DW is the lower material of the annular seal structure 110DW. Each of the stress relaxation buffer layers 109CW and 109DW functions as a stress relaxation buffer layer of the annular bonding material to the cap wafer 108 and the device wafer (or substrate 104).

In particular, the substrate 104 may be a semiconductor device wafer 112, such as silicon, which provides a read only integrated circuit (ROIC), as shown. An interlayer dielectric layer (ILD) 114 on the top surface of the device wafer 112 having a metal connecting the electrically conductive traces of the ROIC component; And an over glass layer 116 disposed on the layer 114. The apparatus 102 is, for example, an array of infrared (IR) detectors, for example, a bolometer is placed in a central region 106 on an over glass 116 as shown. The cap wafer 108 is any IR transparent material and may have a cavity disposed on the device 102 as shown and may include a getter material (not shown).

Each of the pair of annular stress relieving buffer layers 109DW and 109CW is a very soft material, for example, titanium, for the reasons described. The annular stress relaxation buffer layer 109DW is disposed on the over glass layer 116 as described above. Each of the two seal ring structures 110DW and 110CW is formed on the stress relaxation buffer layer 109 on the over glass 116 and the cap wafer 108 as shown in Figure 5A with respect to the seal ring structure 110DW A lower substrate bonding layer 122, e.g., titanium; A diffusion barrier layer 124 disposed on the substrate adhesion layer 122, for example, Ni or Ni, may be formed on the substrate adhesion layer 122 to prevent diffusion (or interaction) Pt; And an oxidative blocking / bonding material adhesive layer 126, for example, gold (AU), disposed on the diffusion barrier layer 124, as shown, to prevent oxide formation and promote solder wetting.

Note that each of the pair of annular stress relieving buffer layers 109CW and 109DW has a width wider than that of each of the seal ring structures 110CW and 110DW and the bonding material 118. [ In this embodiment, the inner edge and the outer edge 109a, 109b of the annular stress relieving buffer layer 109CW, 109DW are formed as shown in Fig. 5A for the stress relaxation buffer layer 109DW and the seal ring structure 110DW Likewise, in order to form the step 224 on one side of the seal ring structures 110CW and 110DW, at least one of the inside and the outside, here the inner edge of the seal ring structures 110CW and 110DW and the outer edges 110a, 110b. ≪ / RTI >

Specifically, in the present embodiment, the over glass layer 116 is, for example, a 2000 Å thick silicon oxynitride (SiON) layer, and each of the pair of annular stress relieving buffer layers 109CW and 109DW, For example, a titanium layer having a thickness greater than 500 angstroms (e.g., 2500 angstroms thick). For example, each of the annular stress relaxation buffer layers 109CW and 109DW is formed using a photolithography lift-off process. Considering the formation of the stress relieving layer 109DW, the stress relieving layer 109CW is formed in a similar manner, and the annular stress relieving buffer layer 109DW is formed, for example, on the over glass layer 116 And then forming a photoresist layer. The region of the photoresist layer is held inside and outside the region of the apparatus where the annular stress relieving buffer layer 109DW is held so that the annular region of the wafer surface where the annular stress relieving buffer layer 109DW is formed is exposed . The entire surface of the wafer is then coated with titanium using either evaporation or physical vapor deposition (PVD) processes, where a portion of the titanium phase is deposited on the patterned photoresist and the other portion is exposed to the exposed annular portion of the wafer Lt; / RTI > The photoresist then lifts off the wafer by removing portions of the titanium on the photoresist and leaving the annular strain relief buffer layer 109DW on the wafer. The material can be prepared using a mechanical mask without a photolithographic process. Next, another lift-off process is performed to form a 2000 Å thick seal ring structure (110DW), such as titanium, which is then deposited using an evaporation or physical vapor deposition (PVD) process, followed by evaporation or physical vapor deposition (PVD) Process is used to deposit nickel with a thickness of 2500 angstroms and evaporation or physical vapor deposition (PVD) process to deposit gold with a thickness of 2500 angstroms. The width of the annular stress relieving buffer layer 109DW is within a range of 300 占 퐉 and the width of the annular seal annular structural body 110DW is narrower than the width of the annular stress relieving buffer layer 109DW ), The inner edge of the annular stress relieving buffer layer 109DW and the set edge 109b (FIG. 5A) from the outer edges 109a and 109b. For example, the inner and outer edges 110a and 110b of the annular ring structure 110DW may each have an inner annular shape, as shown in FIG. 5A, in the annular stress relief buffer layer 109DW to form the step 224, (For example, 50 占 퐉) from the edge and outer edges 109a and 109b. For example, a wide step 224 of 50 占 퐉 is formed. Thus, for example, solder (e.g., gold / tin (e.g., Au 80% SN 20%)) can be used as an edge of the annular stress relief buffer layer 109DW And is lifted onto the surface of the substrate 104 and the cap wafer 108. Thus, the high stress points described in FIG. 3 are moved (elevated away from the over glass layer 116); The stress relieving buffer layer 109DW is effectively inserted into the path of the high stress point to reduce the stress in the brittle SiON over glass layer 116. [ The stress relaxation buffer layer 109DW is formed on the SiON over glass layer 116 at a predetermined temperature, for example, at room temperature (20-23 DEG C) or at the temperature of the package 100 when the lid 108 is bonded to the substrate 118 And the thermal expansion coefficient CTE of the stress relaxation buffer layer 109DW inserted between the solder 118 and the substrate 118 is higher than the CTE of the solder 118 and the CTE of the over glass layer 116 ≪ / RTI > The stress relieving buffer layer 109DW, which has a higher ductility than the SiON over glass layer 116, enables a level of small local strain and further reduces the stress of the brittle SiON over glass layer 116. [

Therefore, the high stress point SP is moved from the brittle SiON layer 116 to the many soft stress relaxation buffer layers 109DW. The stress point associated with the rupture end of the stress relaxation buffer layer 109DW is increased by the relative thickness of the stress relaxation buffer layer 109DW (e.g., 2500A) and the CTE of the lower substrate 104 Due to the stress relaxation buffer layer (109DW) having a similar CTE, it is reduced to a meaningless point. In addition, the small step 224 (Fig. 5A) acts as a solder dam that somewhat avoids solder and thus resists diffusion of solder 118 melted from the joint, since it is surface treated with titanium oxide after exposure to air. That is, on the surfaces of 109 CW and 109 DW, titanium is rapidly oxidized to titanium oxide, and titanium oxide is a substance that inhibits adhesion of the bonding material 118.

The CTE of the AuSn solder is 16 ppm / K, the CTE of Ti is about 8.5 ppm / K; Note that the CTE of silicon is about 2.6 ppm / K and the CTE of SiON is about 2 ppm / K. The coefficient of thermal expansion (approximately 8.5 ppm / K) of the annular stress relieving buffer layer 109DW is approximately equal to the CTE (2 ppm / K) of the surface portion of the substrate bonded to the stress relaxation buffer layer 109DW (i.e., the over glass layer 116) ) And the CTE (16 ppm / K) of the bonding material 118 of the sealing ring structure 110DW.

Therefore, the CTE difference between AuSn solder 118 and Si is very large (Factor 6). The two main materials are stress problems. As the solder cools from the melted state, it is hoped that the solder shrinks more than the attached silicon (factor> 6). The coefficient of thermal expansion (CTE) of the stress relieving buffer layer 109DW is preferably intermediate between the CTE of the over glass layer 116 and the CTE of the solder or bonding material 118 and the soft stress relaxation buffer layer 109DW is between the SiON and silicon ≪ / RTI > can be generated locally in regions of high stress without fracturing, as in the case of brittle materials such as < RTI ID = 0.0 > The stress relaxation buffer layer 109CW has a higher ductility than the ductility of the silicon cap wafer 108 and has a thermal expansion coefficient CTE of the stress relaxation buffer layer 109CW inserted between the solder 118 and the silicon cap wafer 108 .

Referring to Figure 6, a hermetically sealed package 100 'in accordance with yet another embodiment of the present disclosure is shown. 6A) (effectively, the layer 122 'is comprised of the diffusion barrier layer 122 and the stress relieving layer 109DW), the sealing annular structure 110DW' has a titanium substrate adhesion / diffusion barrier layer 122 ' . Thus, the substrate adhesion / diffusion barrier layer 122 'is effectively titanium, thickened to a thickness of approximately 400 A thick, in order to function both as the substrate adhesion layer 122 and the stress relief layer 109DW. For example, a solder mask 150, e.g., titanium or titanium nitride, has a window formed using a lift-off lithography or photolithographic etching process to expose a lower portion of the bond material adhesion layer 126. Note that when titanium is used in the solder mask 150, titanium rapidly oxidizes to titanium oxide, and titanium oxide is a substance that inhibits adhesion of the bonding material 118. Likewise, titanium nitride is a substance that inhibits adhesion of a bonding material.

The bonding material 118, e.g., solder, is placed in a window on the exposed portion of the bonding material adhesive layer 126. It should be noted that the sealing material 118 is narrower than the metal ring 107DW 'and the metal ring includes the sealing ring 110DW' and the solder mask 150, 'Is to set back the edge of the bonding material 118 from the edge of the bonding material 118'. It should also be noted that this retraction is associated with Figures 5 and 5a to form a solder dam corresponding to the step 224 described above. It should be understood that a similar structure is used for the metal ring on the cap wafer 108 in this example.

A structure according to the present disclosure includes a substrate; A metal ring disposed on a surface portion of the substrate about a surface region of the substrate; And a bonding material disposed on the metal ring and having an inner edge and an outer edge, wherein the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. One or more of the following features may be included with the features separately or in combination, wherein the first layer of the metal ring comprises a stress relaxation buffer layer disposed on a surface portion of the substrate, Has a higher ductility than the ductility of the surface portion at a predetermined temperature and has a width greater than the width of the bonding material and the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material Being; The thermal expansion coefficient of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material; Wherein the area of the top surface of the metal ring includes a material that inhibits adhesion of the bonding material to the top surface and wherein the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material ; Wherein the structure includes a bonding material masking layer on the top surface of the metal ring and the bonding material is transferred through the window in the masking layer exposing a portion of the top surface of the metal layer, Onto an exposed portion of an upper surface of the metal layer; The portion of the metal ring extending laterally beyond at least one of an inner edge and an outer edge of the bonding material; The structure comprising: a lead; And an apparatus disposed on the substrate, wherein the bonding material bonds the substrate to the lead; The thermal expansion coefficient of the stress relaxation buffer layer is larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material; The structure comprising a bonding material masking layer on the top surface; Wherein the bonding material is transferred in the masking layer that exposes a portion of the top surface of the metal layer through a window and wherein a portion of the bonding material through the window contacts the top surface of the metal layer To an exposed portion of the upper surface; Wherein the stress relieving buffer layer is disposed in direct contact on a surface portion of the substrate; Wherein the first layer of metal ring comprises a stress relaxation buffer layer disposed on a surface portion of the substrate; The first metal of the metal ring is titanium; The first metal of the metal ring is copper or aluminum; The top surface of the substrate is silicon oxynitride; the substrate comprises silicon; The first layer of the metal ring is titanium with a thickness greater than 500 ANGSTROM.

The stress relieving buffer layer may be formed on the stress relieving buffer layer, the stress relieving buffer layer being formed on the stress relieving buffer layer such that the stress relieving buffer layer is higher than the ductility of the surface portion of the substrate at a predetermined temperature. Having ductility; A bonding material disposed on the sealing ring and having an inner edge and an outer edge; And the stress relief buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Further, the coefficient of thermal expansion (CTE) of the annular stress relieving layer is between the CTE of the surface portion of the substrate and the CTE of the bonding material on the sealing ring.

Also, a structure according to the present disclosure includes a substrate, an apparatus disposed on the substrate, a sealing ring disposed on the substrate around the apparatus, A bonding material disposed on the sealing ring; A layer disposed between the bonding material and the substrate, the layer extending laterally beyond at least one of an inner edge and an outer edge of the bonding material; And the bonding material should be aware of bonding the substrate to the lead. In addition, the coefficient of thermal expansion (CTE) of the layer can be between the CTE of the surface portion of the substrate and the CTE of the bonding material on the sealing ring.

Also, a package according to the present disclosure includes a substrate; A device on the surface of the package; a metal ring disposed on a surface portion of the substrate around the device; lead; A bonding material disposed on an opposite end of the metal ring, the metal ring extending laterally beyond at least one of the inner and outer edges of the bonding material; It should be appreciated that the bonding material bonds the leads to the substrate. One or more of the following features may be included individually or in combination with other features, wherein the first layer of metal rings comprises a stress relaxation buffer layer disposed on a surface portion of the substrate, The stress relief buffer layer having a higher ductility than the ductility of the surface portion at a predetermined temperature and a width greater than the width of the bonding material, the stress relaxation buffer layer extending laterally beyond at least one of the inner and outer edges of the bonding material; The thermal expansion coefficient of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material; Wherein a region of the top surface of the metal ring includes a material that inhibits adhesion of the bonding material to the top surface and wherein the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material; Wherein the bonding material is transferred in a masking layer that exposes a portion of the top surface of the metal layer through a window and a portion of the bonding material is bonded to the top surface of the metal layer via the window, As shown in FIG.

Many embodiments of the present disclosure are disclosed. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, a hermetically sealed package can be made of any inertial MEMS, such as infrared MEMS, gyros and accelerometers, such as a bolometer (sometimes referred to as a microbolometer), a junction May be used for a variety of devices, including individual devices, non-vacuum applications (e.g. DLP) or wafer bonded MEMS in vacuum packaging. Further, other materials may be used for the stress relaxation buffer layer 109DW and / or 109CW, for example, copper or aluminum. In addition, other materials may be used for the substrate bonding layer 122, for example, TiN. In this case, Ti and Ni act as diffusion barriers for different steps of the manufacturing process. Other materials may also be used for the diffusion barrier, for example Pt. In addition, other materials may be used for the bonding material, for example, CuSn. As another over glass material, for example, SiN may be used. Accordingly, other embodiments are within the scope of the following claims.

Claims (28)

As a structure,
Board;
A metal ring disposed on a surface portion of the substrate about a surface region of the substrate;
A bonding material disposed on the metal ring and having an inner edge and an outer edge,
The metal ring extending laterally beyond at least one of an inner edge and an outer edge of the bonding material,
Wherein the first layer of metal rings comprises a stress relaxation buffer layer disposed on a surface portion of the substrate and the first layer has a higher ductility than the ductility of the surface portion at a predetermined temperature, Wherein the stress relieving buffer layer extends laterally beyond at least one of an inner edge and an outer edge of the bonding material,
Wherein the structure further comprises a bonding material masking layer on the top surface of the metal ring, wherein the bonding material masking layer is configured to set back the edge of the bonding material from the edge of the metal ring. .
delete The method according to claim 1,
Wherein the thermal expansion coefficient of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material.
The method according to claim 1,
Wherein a region of the upper surface of the metal ring includes a material that inhibits adhesion of the bonding material to the upper surface and wherein the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material , Structure.
The method according to claim 1,
Wherein the bonding material is conducted through the window in the masking layer exposing a portion of the top surface of the metal ring and a portion of the bonding material is transferred onto the exposed portion of the top surface of the metal ring through the window.
delete The method according to claim 1,
lead; And a device disposed on the substrate, wherein the bonding material bonds the substrate to the lead.
delete delete delete The method according to claim 1,
Wherein the stress relaxation buffer layer is disposed in direct contact on a surface portion of the substrate.
delete delete As a package,
Board;
An apparatus disposed on the substrate;
A sealing ring disposed on the substrate around the device;
A bonding material disposed on the sealing ring;
A stress relaxation buffer layer disposed between the bonding material and the substrate; The layer extends laterally beyond at least one of the inner edge and the outer edge of the bonding material;
Lead, < / RTI >
The bonding material joining the substrate to the lead,
Wherein the stress relaxation buffer layer has a higher ductility than a ductility of a surface portion of the substrate at a predetermined temperature and has a width larger than a width of the bonding material,
Wherein the package further comprises a bonding material masking layer on the top surface of the sealing ring wherein the bonding material masking layer is configured such that an edge of the bonding material retracts from an edge of the sealing ring.
15. The method of claim 14,
Wherein the coefficient of thermal expansion (CTE) of the stress relaxation buffer layer is between the CTE of the surface portion of the substrate and the CTE of the bonding material on the sealing ring.
As a package,
Board;
An apparatus on the surface of the substrate;
A metal ring disposed on a surface portion of the substrate about the apparatus;
lead;
And a bonding material disposed on an opposite end of the metal ring,
The metal ring extending laterally beyond at least one of an inner edge and an outer edge of the bonding material;
The bonding material joining the lead to the substrate,
Wherein the first layer of metal rings comprises a stress relaxation buffer layer disposed on a surface portion of the substrate and the first layer has a higher ductility than the ductility of the surface portion at a predetermined temperature, Wherein the stress relieving buffer layer extends laterally beyond at least one of an inner edge and an outer edge of the bonding material,
Wherein the package further comprises a bonding material masking layer on an upper surface of the metal ring, wherein the bonding material masking layer is configured such that an edge of the bonding material retracts from an edge of the metal ring.
delete 17. The method of claim 16,
Wherein the coefficient of thermal expansion of the stress relaxation buffer layer is larger than the expansion coefficient of the surface portion of the substrate and smaller than the expansion coefficient of the bonding material.
17. The method of claim 16,
Wherein a region of the upper surface of the metal ring includes a material that inhibits adhesion of the bonding material to the upper surface and wherein a portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. package.
17. The method of claim 16,
Wherein the bonding material is conducted through a window in a masking layer that exposes a portion of the top surface of the metal ring and a portion of the bonding material is transferred onto the exposed portion of the top surface of the metal ring through the window.
delete The method according to claim 1,
Wherein one of the metals in the metal ring is titanium.
The method according to claim 1,
Wherein one of the metals of the metal ring is copper or aluminum.
23. The method of claim 22,
Wherein the top surface of the substrate is silicon oxynitride.
23. The method of claim 22,
Wherein the substrate comprises silicon.
24. The method of claim 23,
Wherein the top surface of the substrate is silicon oxynitride.
24. The method of claim 23,
Wherein the substrate comprises silicon.
The method according to claim 1,
Wherein the first layer of the metal ring is titanium having a thickness greater than 500 ANGSTROM.

Images