JP6487032B2 - Sealed package with stress reduction layer - Google Patents

Description

  The present disclosure relates generally to electronic packages. And more specifically, it relates to a microelectromechanical system (MEMS) package.

  As is known in the art, an electromechanical system (MEMS) is an integrated microdevice or system that combines electronic and mechanical components. MEMS devices can be fabricated using, for example, standard integrated circuit batch processing techniques. Typical applications for MEMS devices include detecting, controlling, and driving in a micro scale. Such MEMS devices may function individually or in an array to produce an effect on a macro scale.

  In the prior art and as is known, many MEMS devices require a hermetically sealed environment to achieve the best performance. This may be a vacuum environment, a controlled pressure environment, or a controlled gas environment. The package environment also provides protection and an optimal operating environment for the MEMS device. Specific examples of these MEMS include infrared MEMS such as bolometers, sometimes referred to as microbolometers, predetermined inertia MEMS such as gyros and accelerometers, and optomechanical devices such as moving mirror arrays. . Previously, MEMS devices have been individually packaged in vacuum compatible packages after manufacturing and dicing of the MEMS device wafer. Often, however, the cost of packaging a MEMS device in a conventional metal or ceramic package can be on the order of about 10 to 100 times the device manufacturing cost. This is especially true when a vacuum is required in the package.

  Over the years, various types of infrared detectors have been developed. Many include a substrate having a focal plane array thereon. The focal plane array includes a plurality of detector elements (detection devices) each corresponding to each pixel. The substrate includes an integrated circuit that is electrically connected to the detector element. Commonly known as a read-out integrated circuit (ROIC), the signals from each detector element are integrated and the signals from the chip are multiplexed using appropriate adjustments and processing. It is used for

  As with certain microelectromechanical (MEMS) devices, the bolometer may need to be sealed in a vacuum or other controlled environment for best performance. Typical requirements for packaging bolometer arrays are a reliable hermetic seal capable of maintaining a high vacuum for extended periods of time, integration of IR window material with good infrared transmission And high yield / low cost packaging. Both the reliability and cost of the MEMS device depend on the chosen encapsulation. For MEMS based bolometers, packaging may be done at the chip level or wafer level. The general method of packaging in this instance is to fabricate a protective, IR transmissive cap wafer, or window cap wafer (WCW), and to create an active IR detector bolometer area. Bond to exposed semiconductor substrate or exposed surface of device wafer prior to dicing. A cap wafer is sometimes referred to as a window or lid structure, but is formed therein with a cavity. It appears that when the cap wafer is flipped and bonded to the device wafer, the cavity provides sufficient clearance to accommodate and protect the MEMS device therein. U.S. Pat. No. 5,701,008, entitled “Integrated Infrared microlens and gas molecular gettering in a vacuum package”, inventor Ray et al., Issued December 23, 1997. As described therein and with reference to FIGS. 1 and 2, a package assembly is shown having a read-out integrated circuit (ROIC) substrate 2 of semiconductor material, preferably silicon. doing. An infrared (IR) detector array 14 is disposed on the substrate 2 and includes a plurality of individual detector elements 6, also referred to as pixels. Although FIG. 2 shows only detector pixels 6 in a 5 × 6 cuboid array in the detector region 10, typical IR integrated circuits generally have hundreds or thousands × several hundreds or thousands of pixels 6. It is understood that this includes a planar IR detector array. In most commercial applications, IR detectors are often uncooled, and by detecting the temperature increase resulting from the heat applied to the detector by IR radiation, the IR detector Detect the intensity of the radiation. A typical layer of an uncooled IR detector is a vanadium oxide (VOx) microbolometer (MB), where a plurality of individual detectors are often fabricated on a ROIC substrate by conventional semiconductor manufacturing processes. It is formed with an array. MB arrays detect IR radiation by sensing IR generated heat and are also referred to as focal plane arrays (FPAs) or sensor chip assemblies (SCAs). The substrate 2 is an integrated circuit used for processing the signal generated by the bolometer. In this case, the bolometer is a microbridge resistor whose resistance changes when the temperature changes. Incoming radiation causes a change in the temperature of the microbridge. Although other semiconductor materials such as silicon (Si) can be used, VOx is a commonly available and cost effective one used in most commercial IR detection applications. .

  As described in the above referenced US Pat. No. 5,701,008, the vacuum seal assembly includes a hermetic seal 8 surrounding the IR detector array to seal the detector array from the atmosphere. The seal 8 may be, for example, indium, gold-tin, or other solder, and the height of the seal is precisely controlled when the seal is placed over the substrate 2 or preferably the wafer 10. Is done. The seal 8 supports a second substrate, a cap wafer, here an IR transmission window, here for example silicon. With wafer level packaging, the window wafer 10 appears to have a coefficient of thermal expansion that is consistent with an FPA wafer, which is also silicon. Wafer 10 is a gettering material formed over a defined area of the surface of wafer 10 having a predetermined surface area, as described in US Pat. No. 5,701,008 referenced above. ), Not shown.

  As is also known in the prior art, wafer level packaging (WLP) was developed to handle the high cost of packaging MEMS by removing the conventional package. One such WLP package is described in US Pat. No. 6,521,477, entitled “Vacuum package fabricate of integrated circuit components”, inventor Gooch et al., Issued February 18, 2003. In one WLP process, two wafers can be bonded together using a bonding material to produce a bonded wafer. For example, one of the wafers is a semiconductor (eg, silicon) device having a detector device in the detector area of the wafer. The detector area is located in the central interior area of the device wafer along a readout integrated circuit (ROIC) that is bonded to other wafers. The lid wafer is placed with respect to the detector area of the device wafer using a sheet metal ring of solder. After molding the device in a semiconductor wafer, the wafer includes a thin overglass layer, such as silicon nitride or silicon oxynitride (SiON). To form a titanium bottom layer, a conventional photolithographic process is used to form a seal ring metal that serves as a substrate adhesion layer for the ROIC overglass. Next, a nickel (Nickel) intermediate layer, which acts as a diffusion barrier, is followed by a gold layer to suppress oxidation formation and strengthen the solder joint. It is subsequently referred to as “seal ring”. A similar set of layers is formed on the lid wafer to provide a mating surface for the solder seal between the device and the lid wafer. After formation of the seal ring, solder is applied to, for example, 80% gold and 20% tin, device and / or lid wafer.

  While the described WLP technology provides an effective package, the inventor has found that the edge of the seal ring may be a device or ROCI due to a difference in thermal expansion between the gold tin 7 solder and the semiconductor device wafer. It was confirmed that the stress was increased in the high stress region as shown in FIG. 3 where it was in contact with the wafer. These stresses can result in unwanted crack growth in the overglass and the underlying structure of the device or ROIC wafer, as shown in FIG. These cracks can break the interconnect traces in the dielectric layer (ILD) of the interlayer and the ILD of the ROIC, leading to failure.

  More specifically, the inventors have confirmed in the prior art that seal ring metal stacks (about 0.5 μm thick) and solder (up to 11 μm thick) have coincident edges. When the solder cools below its melting temperature of about 280 degrees Celsius, the solder shrinks faster than the bottom seal ring and ROIC (solder coefficient of thermal expansion (CTE) is about 16 ppm, silicon CTE is about 3 ppm) ). And the solder is very hard (gold tin solder has a large Young's modulus) and thus cannot be deformed to relieve stress. The shrinkage of the solder layer tends to pull the edge of the solder joint, which is responsible for the stress point r and results in a crack at the edge of the joint. Simply increasing the thickness of the lower titanium (Ti) portion of the seal ring has little effect on stress. This is because the stress still remains with the solder pull of the seal ring, resulting in a stress point. By terminating the solder shorts of the metal edges adhering to the ROIC surface and providing an intervening layer, for example, a stress relaxation buffer layer made of titanium, it is localized on the ROIC surface. The sharp edges that transmit stress to the finished area terminate on the ROIC surface and are covered with a more ductile material. The inventor further increases the thickness of the stress relaxation buffer layer in one embodiment or the thickness of the titanium bonding material adhesion layer in another embodiment when the matched edge is removed. It has been confirmed that increasing the thickness of the lower titanium layer by any of the methods further reduces the stress. However, only if the matching edge is removed first.

  In accordance with the present disclosure, a structure is provided. The structure is a substrate; a metal ring disposed on the surface portion of the substrate around the surface portion of the substrate; a bonding material disposed on the metal ring and having inner and outer edges A bonding material. Here, the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the first layer of metal ring includes a stress relaxation buffer layer disposed over the surface portion of the substrate, the first layer being higher than the ductility of the surface portion at a predetermined temperature. It has ductility and is wider than the width of the bonding material. The stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the stress relaxation buffer layer has a coefficient of thermal expansion that is greater than the coefficient of thermal expansion of the surface portion of the substrate and less than the coefficient of thermal expansion of the bonding material.

  In one embodiment, the outer region of the top surface of the metal ring includes a material that inhibits adhesion of the bonding material to the top surface. Here, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the structure includes a bonding material masking layer on the top surface of the metal ring. The bonding material passes through a window in the masking layer that exposes a portion of the top surface of the metal layer, and where the portion of bonding material is windowed over the exposed portion of the top surface of the metal layer. Is going through.

  In one embodiment, the metal ring portion extends laterally beyond at least one of the inner and outer edges of the bonding material.

  In one embodiment, the structure includes a lid. Here, the bonding material bonds the substrate to the lid.

  The stress relaxation buffer layer adheres effectively to the substrate and is not wetted by the bonding material. Furthermore, the stress relaxation buffer layer has a CTE desirably between the coefficient of thermal expansion (CTE) of the surface portion of the substrate bonded to the stress relaxation buffer layer and the CTE of the solder or bonding material, and Instead of cracking as in the case of brittle materials such as SiON and silicon, it has the properties of a ductile material that locally produces regions of high stress. A typical stress relaxation buffer layer material is titanium.

  With such a configuration, the stress generated between the substrate, eg, the semiconductor wafer, and the adhesive layer causes the bonding material edge to contact the stress relaxation buffer layer from the point where the bonding material edge contacts the semiconductor wafer. Shifted to a point, and therefore shifted away from the semiconductor wafer and any associated overglass or brittle material. Thus, the stress relaxation buffer layer serves as a stress reducing layer, shifting the high stress region from a brittle overglass to a more ductile lower layer.

  More specifically, when using a solder with a high thermal contraction rate to join and seal the two wafers to form a package, the solder cools from its melting temperature. As it shrinks, it causes a high level of stress in the lower semiconductor wafer at the edge of the solder joint. The use of the stress relaxation buffer layer 1 isolates the high stress area at the edge of the solder joint from the underlying brittle semiconductor wafer. This is due to the interposition of a stress relaxation buffer layer that has a higher level of ductility than that of the semiconductor wafer and a thermal shrinkage that is lower than the solder layer and still higher than the lower wafer. Thus, the present disclosure allows the integration of high CTE solder or other bonding material with a brittle overglass on the semiconductor structure. Further, the process can be used for device wafers, lids, or both.

  It should be understood that the term “ring-shaped” refers to and includes a shape surrounding a space. The shape may be circular, rectangular, square, oval, or may have an irregular shape, such as a serpentine or serpentine shape.

  The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

FIG. 1 is a simplified cross-sectional perspective view of a vacuum package for an IR detector array in accordance with the prior art. FIG. 2 is a simplified plan view of an IR detector array used in the assembly of FIG. 1 according to the prior art. FIG. 3 is a cross-sectional view of the IR detector array of FIG. 2, with the cross section taken along line 3-3 in FIG. 2 according to the prior art. FIG. 4 is a plan view of a cross-section of a hermetic package according to the present disclosure, the cross-section taken along line 4-4 in FIG. FIG. 5 is a side view of the cross section of the package of FIG. 4, the cross section taken along line 5-5 in FIG. FIG. 5A is an enlarged portion according to a side view of the cross section of FIG. 5, and the enlarged portion is surrounded by arrows 5A-5A in FIG. FIG. 6 is a cross-sectional side view of a hermetically sealed package according to another embodiment of the present disclosure. 6A is an enlarged portion according to a side view of the cross section of FIG. 6, and the enlarged portion is surrounded by arrows 6A-6A in FIG.

  Like reference symbols in the various drawings indicate like elements.

  Referring now to FIGS. 4 and 5, a hermetic sealed package 100 for the sealing device 102 is shown. The package 100 has, in its central region, a substrate 104 having a device 102; a device 102; a cap wafer 108 (FIG. 5); and a pair of metal rings, here for example a multilayer metal ring, a 107DW metal ring 107 CW; The metal ring 107DW is disposed on the surface of the substrate 104 around the surface area 106 of the substrate 104, and the other metal ring 107CW is above the surface of the cap wafer 108 around the central area 106. Is arranged. It should be understood that in some applications, the metal ring 107CW may not be required. As shown more clearly in FIG. 5A, the metal ring 107DW is a ring-shaped stress relief buffer layer 109DW (more specifically, disposed on and in direct contact with the surface of the substrate 104. On the over-glass layer 116 of the substrate 104 and in direct contact); and on the top surface of the ring-shaped stress relief buffer layer 109DW, a seal ring structure 110DW (FIG. 5); Including. The metal ring 107CW includes a ring-shaped stress relief buffer layer 109CW on the surface of the cap wafer 108 around the central region 106; and a seal ring structure 110CW on the top surface of the ring-shaped stress relief buffer layer 109CW). ;including. A bonding material 118 is placed between the two seal ring structures 110DW, 110CW, as shown in FIG. Thus, as will be described in more detail below, the ring-shaped stress relief buffer layer 109CW is the underlying material of the ring seal structure 110CW, and the ring-shaped stress relief buffer layer 109DW is a ring seal. It is a lower material of the structure 110DW. Each of the stress relaxation buffer layers 109CW and 109DW serves as a stress relaxation buffer layer of a ring-shaped bonding material for the cap wafer 108 and the device wafer (or substrate 104), respectively.

  More specifically, the substrate 104 is a semiconductor device wafer 112, here, for example, silicon, which provides a read-only integrated circuit ROIC; a device wafer 112 having metal interconnect electrical conductive traces for ROIC components. An interlayer dielectric layer (ILD) 114 on the top surface; and an overglass layer 116 placed on the layer 114 as shown. As shown, the device 102 is here, for example, an array of infrared (IR) detectors, where, for example, the bolometer is located in the central region 106 above the overglass 116. The cap wafer 108 is any infrared transparent material and has a cavity disposed over the device 102, as shown, and may include a getter material, not shown.

  Each of the ring-shaped stress relief buffer layers 109DW, CW is a highly ductile material, here titanium, for example, for reasons to be explained. The ring-shaped stress relaxation buffer layer 109DW is disposed on the overglass layer 116 as described above. Each one of the two seal ring structures 110DW and 110CW, respectively, is a lower, substrate adhesive layer 122, placed on the stress relief buffer layer 109 on the overglass 116 and cap wafer 108, here For example, titanium; as shown, a diffusion barrier layer 124, for example, nickel (Ni) or platinum (Pt), disposed over the substrate adhesion layer 122, and the bonding material 118 is substrate bonded. For preventing diffusion into (or interacting with) layer 122; and, as shown, an oxidation block / bonding material adhesion layer 126 disposed over diffusion barrier layer 124, here For example, gold (Au) prevents oxidation formation and promotes solder wetting Intended for; including.

  Note that each one of the ring-shaped stress relief buffer layers 109CW, 109DW pairs is wider than the seal ring structures 110CW, 110DW, respectively, and the bonding material 118. In this embodiment, the inner and outer edges 109a, 109b of the ring-shaped stress relief buffer layers 109CW, 109DW, respectively, extend beyond at least one of the inner and outer sides, here the seal ring structures 110CW, 110DW. Step 224 is formed on either side of the seal ring structure 110CW, 110DW, both exceeding the inner and outer edges 110b by a length L, respectively. The stress relaxation buffer layer 109DW and the seal ring structure 110DW are more clearly shown in FIG. 5A.

  More specifically, in this embodiment, the overglass 116 is, for example, 2000 Angstrom thick silicon oxynitride (SiON), one each of the ring-shaped stress relief buffer layers 109DW, CW. Is, for example, a layer of titanium having a thickness greater than 500 angstroms, for example 2500 angstroms. Here, for example, each one of the ring-shaped stress relaxation buffer layers 109DW and CW is formed using a photolithographic lift-off process. In consideration of the formation of the stress relaxation layer 109DW and recognizing that the stress relaxation layer 109CW is formed in a similar manner, the ring-shaped stress relaxation buffer layer 109DW is, for example, On top, a photoresist layer, not shown, is formed first. A ring-shaped stress relief buffer layer 109DW remains in the regions of the photoresist layer inside and outside the device region, thereby leaving a ring-shaped region on the wafer surface where there is a ring-shaped stress. A relaxation buffer layer 109DW is formed and exposed. Next, the entire surface of the wafer is coated with titanium using either an evaporation or physical vapor deposition (PVD) process. Note that a portion of the titanium will be deposited on the patterned photoresist and the other portion will be deposited on the exposed ring-shaped portion of the wafer. Thereafter, the photoresist is lifted off from the wafer, thereby removing the portion of titanium on the photoresist and leaving a ring-shaped stress relief buffer layer 109DW on the wafer. The material can also be manufactured using a mechanical mask without the need for a photolithography process. Next, another lift-off process is used to form the seal ring structure 110DW. Here, for example, titanium having a thickness of 2000 angstroms deposited using either a vapor deposition or physical vapor deposition (PVD) process. Nickel having a thickness of 2500 angstroms deposited using either vapor deposition or physical vapor deposition (PVD) process, and deposited using either vapor deposition or physical vapor deposition (PVD) process This is followed by gold having a thickness of 2500 angstroms. Here, the width of the ring-shaped stress relaxation buffer layer 109DW is in a range of 300 micrometers, and the width of the ring-shaped seal ring structure 110DW is, for example, larger than the width of the ring-shaped stress relaxation buffer layer 109DW here. Note the narrow (200 micrometer) and set back from the inner and outer edges 109a, 109b of the ring shaped stress relief buffer layer 109DW, respectively. Here, for example, the inner and outer edges 110a, 110b of the seal ring structure 110DW are each set back by a length L, for example, the inner and outer edges 110a of the ring-shaped stress relief buffer layer 109DW. , 110b, respectively, 50 micrometers. This is because the step 224 is formed as shown in FIG. 5A. Here, for example, a step 224 having a width of 50 micrometers is formed. As a result, a sharp edge of the bonding material 118, eg, solder (here, eg, gold / tin (eg, 80% gold, 20% tin)) is set back from the edge of the ring-shaped stress relief buffer layer 109DW. And then lifted onto the surface of the substrate 104 and the cap wafer 108, respectively. As a result, the high stress points described in FIG. 3 are shifted (lifted away from the overlayer 116). A stress relaxation buffer layer 109DW is then effectively inserted into the high stress point path, thereby reducing the stress in the brittle SiON overglass layer 116. The stress relaxation buffer layer 109DW is higher than the ductility of the SiON overglass layer 166 at a predetermined temperature, such as room temperature (20-23 degrees Celsius) or the temperature of the package 100 when the lid 108 is bonded to the substrate 118. The thermal expansion coefficient (Coefficient of Thermal Expansion, CTE) of the ductility and stress relaxation buffer layer 109DW, which is inserted between the solder 118 and the substrate 118, is determined by the CTE value of the solder and the over glass layer. Note that the value is between 116 CTE values. Since the stress relaxation buffer layer 109DW has higher ductility than the SiON overglass layer 116, the stress in the brittle SiON overglass layer 116 can be further reduced for a small level of local deformation. .

  As a result, the high stress point SP is shifted out of the brittle SiON layer 116 (where it was placed in FIG. 3) and into the more ductile stress relaxation buffer layer 109DW. The stress point associated with the sharp edge of the stress relaxation buffer layer 109DW is that of the stress relaxation buffer layer 109DW having increased ductility, thanks to the stress relaxation buffer layer 109DW having a CTE closer to the coefficient of thermal expansion of the lower substrate 104. Combined with the relative thinness (here, for example, 2500 angstroms), it is reduced to an insignificant point. In addition, the small step 224 (FIG. 5) dislikes some solder because the surface is finished with titanium oxide after exposure to air, and therefore solder to counter the spread of molten solder 118 from the joint. Works as a dam (solder dam). That is, the surfaces of 109CW and 109DW are titanium that is quickly oxidized to titanium oxide, and titanium oxide is a material that suppresses adhesion by the bonding material 118.

  Thermal expansion coefficient (CTE) of AuSn (gold tin) solder = 16 ppm / K, CTE of Ti (titanium) ≈8.5 ppm / degree Fahrenheit (degree Kelvin), CTE of silicon (silicon) ≈2.6 ppm / Fahrenheit Note that the CTE of SiON (silicon oxynitride) is approximately 2 ppm / Fahrenheit. The ring-shaped stress relaxation buffer layer 109DW includes the CTE of the surface portion of the substrate joined to the ring-shaped stress relaxation buffer layer 109DW (that is, the overglass layer 116 (2 ppm / degrees Fahrenheit)), and the seal ring structure. Note that it has a coefficient of thermal expansion (CTE) (≈8.5 ppm / Fahrenheit) between (approximately in between) the CTE (16 ppm / K) of the bonding material 118 above 110 DW.

  Therefore, note that the CTE difference between gold tin solder 118 and silicon is very large (6 times). These are the two main materials that are causing stress problems. When solder cools from the molten state of the solder, it wants to shrink more than 6 times that of the deposited silicon. The stress relaxation buffer layer 109DW preferably has an intermediate coefficient of thermal expansion (CTE) between the CTE of the overglass layer 116 and the CTE of the solder or bonding material 118, and for brittle materials such as silicon oxynitride and silicon Note that instead of cracking like this, the ductile stress relaxation buffer layer 109DW can locally generate high stress areas. The stress relaxation buffer layer 109CW has a ductility higher than that of the silicon cap wafer 108, and the coefficient of thermal expansion (CTE) of the stress relaxation buffer layer 109CW is inserted between the solder 118 and the silicon cap wafer 108. Also note that

  Referring now to FIG. 6, a sealed package 100 'is shown according to another embodiment of the present disclosure. Here, the seal ring structure 110DW ′ has a titanium substrate adhesion / diffusion barrier layer 122 ′ (FIG. 6A), and actually the layer 122 ′ is formed from the diffusion barrier layer 122 and the stress relaxation layer 109DW. It has become. Thus, the substrate adhesion / diffusion barrier layer 122 'is actually titanium thickened to a thickness of approximately 4000 Angstroms, and serves the dual purpose of the substrate adhesion layer 122 and the stress relief layer 109DW. Solder mark 150, here, for example, titanium or titanium nitride, has a window formed therein using a photolithographic etching process or lift-off lithography to expose the lower portion of bonding material adhesion layer 126. Yes. Note that when titanium is used for the solder mask 150, the titanium is rapidly oxidized to titanium oxide, and the titanium oxide suppresses adhesion of the bonding material 118. Similarly, titanium nitride suppresses adhesion of the bonding material 118.

  Bonding material 118, here, for example, solder, is deposited onto the exposed portion of bonding material adhesion layer 126 into the window. Note that the seal material 116 is narrower than the metal ring 107DW '. The metal ring here includes a seal ring structure 110DW 'and a solder mark 150 to set back the edge of the bonding material 118 from the edge of the metal ring 107DW' as shown. Note also that this setback forms a solder dam equivalent to step 224 described above in connection with FIGS. 5 and 5A. It should be understood that a similar structure is used for the metal ring on the cap wafer 108 in this example.

  A structure according to the present disclosure is disposed on a metal ring having a substrate; a metal ring disposed on the surface portion of the substrate around the surface portion of the substrate; and inner and outer edges. It should be understood from now that the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. One or more of the following features may include independent or combined with another feature. Here, the first layer of the metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate, and the first layer has a higher ductility than the surface portion at a predetermined temperature. And wider than the width of the bonding material, and the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a thermal expansion coefficient larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material. Here, the region of the top surface of the metal ring includes a material that inhibits the bonding material from adhering to the top surface, and the portion of the metal ring lies across at least one of the inner and outer edges of the bonding material. Spreading in the direction. The structure includes a bonding material masking layer on the top surface of the metal ring, the bonding material passing through a window in the masking layer exposing a portion of the top surface of the metal layer, and wherein The portion of bonding material passes through the window onto the exposed portion of the top surface of the metal layer. Here, the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The structure includes a lid and a device disposed on the substrate, and wherein the bonding material bonds the substrate to the lid. Here, the stress relaxation buffer layer has a thermal expansion coefficient larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material. The structure includes a bonding material masking layer on the top surface. A bonding material masking layer is included on the upper surface of the metal ring, the bonding material passing through a window in the masking layer exposing a portion of the upper surface of the metal layer, and wherein a portion of the bonding material Passes through the window over the exposed portion of the top surface of the metal layer. Here, the stress relaxation buffer layer is disposed on the surface portion of the substrate and is in direct contact therewith. Here, the first layer of the metal ring includes a stress relaxation buffer layer disposed on the surface portion of the substrate. Here, the first layer of the metal ring is titanium. Here, the first layer of the metal ring is copper or aluminum. Here, the upper surface of the substrate is silicon oxynitride. Here, the substrate includes silicon. Here, the first layer of the metal ring is titanium having a thickness greater than 500 angstroms.

  It should also be appreciated that a structure according to the present disclosure includes: The structure includes a substrate; a stress relief buffer layer; a seal ring disposed on the stress relief buffer layer and around a surface portion of the substrate. Here, the stress relaxation buffer layer has a ductility higher than the ductility of the surface portion of the substrate at a predetermined temperature. A bonding material is disposed on the seal ring, and the bonding material has inner and outer edges. Here, the stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material. Further, the ring-shaped stress relief layer may have a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

  It should also be appreciated that a structure according to the present disclosure includes: The structure includes a substrate; a device disposed on the substrate; a seal ring disposed on the substrate around the device; a bonding material disposed on the seal ring; a bonding material and the substrate A layer that extends laterally beyond at least one of the inner and outer edges of the bonding material; a lid; and the bonding material includes a substrate relative to the lid. It is to join. In addition, the layer has a CTE between the coefficient of thermal expansion (CTE) of the surface portion of the substrate and the CTE of the bonding material on the seal ring.

  It should also be appreciated that a package according to the present disclosure includes: The package includes a substrate; a device disposed on the surface of the package; a metal ring disposed on the surface portion of the substrate around the device; a lid; a bonding material disposed on opposite ends of the metal ring. Is included. Here, the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material, and the bonding material bonds the lid to the substrate. One or more of the following features may be included independently or in combination with another feature. The feature is that the first layer of the metal ring includes a stress relaxation buffer layer disposed over the surface portion of the substrate, the first layer having a ductility that is higher than the ductility of the surface portion at a predetermined temperature. And wider than the width of the bonding material, the stress relaxation buffer layer extending laterally beyond at least one of the inner and outer edges of the bonding material. Here, the stress relaxation buffer layer has a thermal expansion coefficient larger than that of the surface portion of the substrate and smaller than that of the bonding material. Here, the region of the upper surface of the metal ring includes a material that suppresses adhesion of the bonding material to the upper surface, and the portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. It is spreading. The package includes a bonding material masking layer on the top surface of the metal ring, the bonding material passing through a window in the masking layer exposing a portion of the top surface of the metal layer, and the portion of the bonding material is: Pass the window over the exposed portion of the top surface of the metal layer.

  A number of embodiments according to the present disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, sealed packages can be used for a wide variety of devices. Without limitation, infrared MEMS such as bolometers, what are sometimes referred to as microbolometers, and certain inertia MEMS such as gyros and accelerometers, devices dedicated to bonding to packages, non-evacuated applications ( Such as DLP) or wafer bonded MEMS in a vacuum package. In addition, other materials may be used for the stress relief buffer layer 109DW and / or 109CW. For example, copper or aluminum. In addition, other materials may be used for the substrate adhesive layer 122. For example, TiN. In this case, both Ti and Ni act as diffusion barriers for different stages of the manufacturing process. In addition, other materials may be used for the bonding material. For example, CuSn. Furthermore, still other overglass materials may be used. For example, SiN. Accordingly, other embodiments are within the scope of the following claims.

Claims (9)

A substrate,
A metal ring disposed on the surface portion of the substrate around the surface portion of the substrate;
A bonding material disposed on the metal ring, the bonding material having inner and outer edges, comprising:
The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material;
The structure further includes a bonding material masking layer on the top surface of the metal ring;
The bonding material passes through a window in the masking layer exposing a portion of the top surface of the metal layer; and
A portion of the bonding material passes through the window onto an exposed portion of the top surface of the metal layer ;
A first layer of the metal ring includes a stress relaxation buffer layer disposed on a surface portion of the substrate;
The first layer of the metal ring is copper or aluminum;
Structure. Before Symbol first layer is the default temperature has higher than ductility ductility of the surface portions, and wider than the width of the bonding material,
The stress relaxation buffer layer extends laterally beyond at least one of the inner and outer edges of the bonding material;
The structure according to claim 1. The stress relaxation buffer layer has a thermal expansion coefficient that is larger than the thermal expansion coefficient of the surface portion of the substrate and smaller than the thermal expansion coefficient of the bonding material.
The structure according to claim 2. A region of the upper surface of the metal ring includes a material that suppresses adhesion of the bonding material to the upper surface; and
A portion of the metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material;
The structure according to claim 1. The structure is
A lid and a device disposed on the substrate, and
The bonding material bonds the substrate to the lid.
The structure according to claim 1. The stress relaxation buffer layer is disposed on a surface portion of the substrate and is in direct contact;
The structure according to claim 2. A package,
The structure according to any one of claims 1 to 4,
A device disposed on a surface of the package;
Lid, and
The metal ring is disposed on the surface portion of the substrate around the device;
The bonding material is disposed at opposite ends of the metal ring;
The bonding material bonds the lid to the substrate;
package. The upper surface of the substrate is silicon oxynitride,
The structure according to claim 1 . The substrate comprises silicon;
The structure according to claim 1 .

Images