KR101852767B1 - Template epi substrates and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a template epitaxial substrate and a method of manufacturing the same, and more particularly, to a template epitaxial substrate exhibiting an effect of minimizing crystal defects and warping of a substrate by eliminating residual stress while preventing cracks, and a manufacturing method thereof .

Description

[0001] The present invention relates to a template epi substrate and a manufacturing method thereof,

The present invention relates to a template epitaxial substrate and a method of manufacturing the same, and more particularly, to a template epitaxial substrate exhibiting an effect of minimizing crystal defects and warping of a substrate by eliminating residual stress while preventing cracks, and a manufacturing method thereof .

Recently, the fabrication of power semiconductor optical devices, RF devices and sensors using III-nitride epitaxial layers has been expanded. However, attempts to improve performance and increase productivity are becoming a major concern. The reason for this is that when III-nitride is grown on a substrate such as sapphire, silicon, or silicon carbide (SiC), there is a problem of dependency on electric conductivity or a problem caused by a high density of crystal defects Or the diameter is so small that productivity is so low that it lacks economic value.

For example, applications for manufacturing Red-Green-Blue, UV, and White light emitting devices using GaN-based III nitride epitaxial layers have been greatly expanded. A GaN-based light emitting diode with a textured indium tin oxide transparent layer (hereinafter referred to as " GaN-based light emitting diode " (III-Nitride) is added to sapphire, as in the case of Al2O3-coated Al2O3 powder, "Appl. Phys. Lett.Vol. 94, No. 16, pp. 161107-1-3 ) Are mainly grown and used. Here, in order to increase the luminous efficiency, various techniques using a nanoparticle or a substrate to be patterned are used.

In recent years, devices such as Schottky barrier diodes, HEMTs and metal oxide semiconductor field effect transistors (MOSFETs) have been researched and developed as electronic devices, and some technologies have been commercialized . Recently, the current control slope of switching is rapidly controlled from dI / dt to 100 A / us as the operating speed of the power control becomes higher as well as the voltage and power of the power control. Thus, overvoltage and power loss And the problem of ensuring reliability at high voltage is serious. Particularly, the leakage current flowing at the interfaces or surfaces of the III-nitride layer (SKH, KH Shim, JW Yang, "Reduced gate leakage current in AlGaN / GaN HEMT by oxygen passivation of AlGaN surface, The leakage current flow or the change in the threshold voltage due to the serious surface and interface defects is a serious problem (see, for example, Wang et al., Vol.44, No. 18, Aug., 2008 , As well as ensuring the immunity and stability to EOS / ESD is a very important issue.

In modern times, there is a great need for countermeasures to simultaneously expand the limitations of high-speed operation and withstand voltage characteristics provided by silicon semiconductors in power semiconductor devices. In spite of the fact that product development for FET devices has become easier in recent years, device performance still needs to be improved in terms of operation speed, power consumption, over-voltage, reliability, and power driving.

Therefore, a technology for a high-power high-voltage device using a III-nitride semiconductor such as GaN having a high heat-resistant high withstand voltage characteristic is attracting attention. However, in terms of long-term reliability of devices, the role of power semiconductors mainly focusing on silicon is required. In other words, silicon-based advantages can be exploited to overcome static and thermal-electrical instabilities in GaN-based FETs with high-speed and high-voltage characteristics.

As described above, a GaN-based device is mounted on a silicon substrate and integrated with a silicon device, thereby achieving a great improvement in performance, productivity, and reliability. To do this, however, a good crystalline III-nitride epilayer must be formed on the silicon substrate.

However, existing techniques do not solve problems such as defects, cracks, and physical bending of the substrate caused by the lattice mismatch and the thermal expansion coefficient discrepancies in the III-nitride epitaxial layer.

Conventionally, a nitrided semiconductor epitaxial layer is formed by using a nitride film containing Al as a buffer layer to improve electrical characteristics and crystallinity. A metal oxide film is formed, a nitride buffer layer is formed thereon, and a nitride semiconductor epitaxial layer is grown thereon. Sapphire and GaInN are used for the substrate and buffer layer, respectively. Sapphire substrates or GaInN buffer layers have been used by other researchers in the past. However, most of the substrates used in the prior art are silicon (Si), sapphire, ZnO, and SiC, and the problems of the GaN-based III nitride semiconductor devices are inherent, The problem was, the thermal and electrical performance was not good. In addition, there is a problem that cracks do not occur and the effect of minimizing crystal defects and warping of the substrate can not be achieved through elimination of residual stress.

US 7,023,025 B2 (Registered on April 4, 2006)

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a template epitaxial substrate exhibiting an effect of minimizing crystal defects and warping of a substrate by eliminating residual stress while not generating cracks And a method for producing the same.

In order to solve the above-mentioned problems, the present invention includes a medium layer of a single layer structure or a multi-layer structure, and an intermixing layer formed on upper and lower parts of the intermediate layer of the single layer structure, , Wherein the intermediate layer comprises a compound satisfying the following molecular formula (1).

[Molecular formula 1]

Si _1-xy Ge _x Sn _y

X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y.

According to a preferred embodiment of the present invention, the lateral pattern of the intermediate layer is selected from a continuous pattern or an elliptical pattern, a circular pattern and a trapezoidal pattern including at least one selected from a linear pattern, a zigzag pattern, a wavy pattern and a rectangular pattern And may be a discontinuous pattern comprising at least one species.

According to another preferred embodiment of the present invention, when the intermediate layer is a continuous pattern, a base substrate, a medium layer, a cap layer, a buffer layer, and an epi layer And the intermediate layer, the buffer layer and the epi layer can satisfy the following relational expression (1).

[Relation 1]

Buffer layer melting point (占 폚)? Intermediate layer melting point (占 폚)? Epilayer melting point (占 폚)

According to another preferred embodiment of the present invention, the base substrate has a thickness of 100 μm to 950 μm, the intermediate layer has a thickness of 1 nm to 10 μm, the cap layer has a thickness of 1 nm to 10 μm, 1 to 10 [micro] m and the epilayer may have a thickness of 1 nm to 10 [micro] m.

According to another preferred embodiment of the present invention, when the intermediate layer is a discontinuous pattern, a base substrate, a cap layer, a buffer layer, and a main epi layer are sequentially stacked And the intermediate layer, the buffer layer and the epi layer may satisfy the following relational expression (1).

[Relation 1]

Buffer layer melting point (占 폚)? Intermediate layer melting point (占 폚)? Epilayer melting point (占 폚)

According to another preferred embodiment of the present invention, the base substrate has a lattice constant of 5.431 to 5.657 Å, a thermal expansion coefficient of (2.6 to 5.9) × 10 ^-6 K ^-1 , a lattice constant of 5.431 to 5.83 (2.6 to 13) x 10 ^-6 K ^-1 , the cap layer has a lattice constant of 5.431 to 5.83 Å, a thermal expansion coefficient of (2.6 to 13) × 10 ^-6 K ^-1 , the buffer layer has a lattice constant is 3.11 ~ 3.54 Å, a thermal expansion coefficient ^{(3.17 ~ 5.6) × 10 -6} K -1 , and the epitaxial layer has a lattice constant is 3.11 ~ 3.54 Å, a thermal expansion coefficient ^{(3.17 ~ 5.6) × 10 -6} K -1 day .

According to another preferred embodiment of the present invention, the base substrate includes at least one selected from silicon and germanium, and the intermediate layer includes at least one selected from the group consisting of silicon, germanium, tin and compounds thereof, The cap layer includes at least one selected from the group consisting of silicon, germanium, tin, and a compound thereof. The buffer layer includes a nitride based material including GaN and AlN. The epi layer includes nitride based materials including GaN and AlN can do.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming an intermediate layer on a base substrate; growing a cap layer and a buffer layer on the intermediate layer; and heat treating the intermediate layer to form an intermix layer And growing an epilayer on top of the buffer layer, wherein the intermediate layer comprises a compound that satisfies the following molecular formula 1: &lt; EMI ID = 1.0 &gt;

[Molecular formula 1]

Si _1-xy Ge _x Sn _y

X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y.

According to a preferred embodiment of the present invention, the step of growing the buffer layer may be performed at a temperature of 500 ° C to 800 ° C for 1 minute to 10 hours, and the step of forming the intermixing layer may be performed at a temperature of 800 ° C to 1500 ° C For 1 minute to 10 hours.

According to another preferred embodiment of the present invention, the intermix layer may be formed by modifying a part of at least one layer selected from a base substrate, an intermediate layer and a cap layer.

In order to solve the above-mentioned problems, the present invention provides a semiconductor device comprising the aforementioned template epitaxial substrate, wherein at least one intermixing layer formed on at least one side of the intermediate layer and the intermediate layer is side-etched .

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of: preparing a template epitaxial substrate by the above-described manufacturing method; and side-etching the intermediate layer of the template epitaxial substrate and one or more intermixing layers formed on at least one side of the intermediate layer A method of manufacturing a semiconductor device including the step of manufacturing a semiconductor device is provided.

INDUSTRIAL APPLICABILITY The template epitaxial substrate and the method of manufacturing the same according to the present invention have the effect of minimizing crystal defects and warpage of the substrate by eliminating residual stress while not causing cracks.

1 is a schematic diagram of a process for fabricating a template epi substrate structure, in accordance with a preferred embodiment of the present invention.
2 is a structural view of a template epi substrate having a multi-layered intermediate layer, according to a preferred embodiment of the present invention.
3 is a schematic diagram of a process for fabricating a semiconductor device with a template epi substrate, in accordance with a preferred embodiment of the present invention.
4 is a structural view of a template epi substrate including an intermediate layer of a discontinuous pattern, according to a preferred embodiment of the present invention.

Hereinafter, the present invention will be described in more detail.

As described above, conventionally, a nitrided semiconductor epitaxial layer is formed by using a nitride film containing Al as a buffer layer to improve electrical characteristics and crystallinity. A nitride epitaxial substrate was fabricated by forming a metal oxide film, forming a nitride buffer layer thereon, and then growing a nitride semiconductor epitaxial layer thereon. However, most of the substrates used in the prior art are silicon (Si), sapphire, ZnO, and SiC, and the problems of the GaN-based III nitride semiconductor devices are inherent, The problem was, the thermal and electrical performance was not good. In addition, there is a problem that cracks do not occur and the effect of minimizing crystal defects and warping of the substrate can not be achieved through elimination of residual stress.

Accordingly, the present invention relates to an intermediate layer of a single-layer structure or a multi-layer structure; And

An intermixing layer formed above and below the intermediate layer of the single layer structure and above and below each intermediate layer of the multi layer structure, wherein the intermediate layer provides a template epitaxial substrate comprising a compound satisfying a specific molecular formula And solved the above problem. As a result, unlike the prior art, cracks do not occur, and the crystal defects and the warping of the substrate can be minimized through elimination of the residual stress.

The template epi substrate of the present invention will be described according to the manufacturing method.

The template epi substrate of the present invention comprises a substrate, a substrate, an intermediate layer on the base substrate, a cap layer and a buffer layer on top of the intermediate layer, a heat treatment to form an intermixing layer above and below the intermediate layer, And growing an epitaxial layer on top of the epitaxial layer.

1 is a schematic diagram of a process for fabricating a template epi substrate structure, in accordance with a preferred embodiment of the present invention.

First, the step of forming an intermediate layer on the base substrate will be described.

1A, an intermediate layer 102 may be formed on the base substrate 101 as shown in FIG.

The base substrate 101 may be any material that exhibits a lattice constant and a thermal expansion coefficient similar to those of the epi layer 107, and may preferably include silicon.

The base substrate 101 may have a lattice constant ranging from 5.431 to 5.657 angstroms, preferably from 5.431 to 5.657 angstroms, and a thermal expansion coefficient of 2.6 to 5.9 × 10 ^-6 K ^-1, preferably from 2.6 to 5.8 ) × 10 ^-6 K ^{- 1} . If the lattice constant and the thermal expansion coefficient of the base substrate 101 are out of the above ranges, cracking and warping may occur.

The base substrate 101 may have a thickness of 100 mu m to 950 mu m, and preferably a thickness of 300 mu m to 750 mu m. If the thickness is out of the above range, the thin layer causes cracking or breakage during the device fabrication process. If the thickness is too thick, excessive back grinding may be required in the post fabrication process.

The intermediate layer 102 may be any material that can be used as an intermediate layer, and may include a compound that satisfies the following molecular formula 1.

[Molecular formula 1]

Si _1-xy Ge _x Sn _y

X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y, preferably 0 <x <0.8 and 0 <y <0.8.

The intermediate layer 102 may have a lattice constant of 5.431 to 5.83 A, preferably 5.431 to 5.83 A and a thermal expansion coefficient of 2.6 to 13 x 10 ^-6 K ^-1 , × 10 ^-6 K ^-1 . If the lattice constant and the thermal expansion coefficient of the intermediate layer 102 are out of the above ranges, cracking and warping may occur.

The intermediate layer 102 may have a thickness of 1 nm to 10 μm, and preferably a thickness of 50 nm to 300 nm. If the thickness is out of the above range, when an excessively thick intermediate layer having a thickness of 10 탆 or more is used, the reactivity in forming the intermixing layer is lowered, thereby reducing defects in the formation of the upper epilayer and lowering of the warping phenomenon Problems can arise.

On the other hand, the side surface pattern of the intermediate layer 102 is not limited as long as it is a side surface pattern of the conventional intermediate layer 102, and preferably, a continuous pattern including at least one selected from a linear pattern, a zigzag pattern, Or may be a discontinuous pattern comprising at least one selected from an elliptical pattern, a circular pattern, and a trapezoidal pattern.

FIG. 4 is a structural view of a template epi substrate including an intermediate layer of a discontinuous pattern according to a preferred embodiment of the present invention. When the intermediate layer includes an intermediate layer of a discontinuous pattern as shown in FIG. 4, May include an intermediate layer.

Next, a step of growing the cap layer 103 and the buffer layer 104 on the intermediate layer 102 will be described.

The cap layer 103 and the buffer layer 104 may be grown on the intermediate layer 102 as shown in FIG.

The cap layer 103 may be any material that can be used for the cap layer 103, and may include a silicon germanium compound. The buffer layer 104 may be any material that can be used for the buffer layer 104, and may include GaN and AlN.

The cap layer 103 may have a lattice constant of 5.431 to 5.83 Å, preferably 5.431 to 5.83 Å and a thermal expansion coefficient of 2.6 to 13 × 10 ^-6 K ^-1 , preferably of 2.6 to 12 × 10 ^-6 K ^{- 1} . If the lattice constant and the thermal expansion coefficient of the cap layer 103 are out of the above ranges, cracking and warping may occur.

The cap layer 103 may have a thickness of 1 nm to 10 탆, and preferably a thickness of 100 nm to 1 탆. If the thickness is out of the above range, when an excessively thick cap layer having a thickness of 10 탆 or more is used, the reactivity in forming the intermixing layer is lowered, thereby reducing defects in the formation of the upper epi layer, May occur.

The buffer layer 104 may have a lattice constant of 3.11 to 3.54 Å, preferably 3.11 to 3.54 Å, and a thermal expansion coefficient of 3.17 to 5.6 × 10 ^-6 K ^-1 , preferably 3.17 to 5.5 ) X 10 &lt; ^-6 &gt; K &lt; ^-1 &gt;. If the lattice constant and the thermal expansion coefficient of the buffer layer 104 are out of the above ranges, cracking and warping may occur.

The step of growing the buffer layer 104 may be performed at 500 ° C to 800 ° C, preferably 600 ° C to 800 ° C. If the temperature of the step of growing the buffer layer 104 is less than 500 ° C., crystallinity may be poor in the formation of the low-temperature buffer layer. If the temperature is more than 800 ° C., intermixing phenomenon There may be a problem that can proceed.

The buffer layer 104 may have a thickness of 1 nm to 10 탆, and preferably a thickness of 500 nm to 2 탆. If the thickness is out of the above range, a too thin buffer layer may be formed to form an epitaxial layer, which may result in a problem that sufficient crystallinity can not be transmitted to the epitaxial layer.

Next, the step of raising the temperature to form the intermixing layers 105, 106 above and below the medium layer 102 will be described.

1D, the intermixing layers 105 and 106 may be formed by modifying a part of a layer of at least one layer selected from the base substrate 101, the intermediate layer 102, and the cap layer 103, The step of forming the mixing layers 105 and 106 may be performed at 800 ° C to 1500 ° C for 1 minute to 10 hours, preferably 900 ° C to 1200 ° C for 30 minutes to 1 hour. If the temperature is less than 800 ° C., intermixing may not be smoothly performed. If the temperature is higher than 1500 ° C., the base substrate may be diffused upward, or the base substrate itself may be warped. If the time is less than 30 minutes, there may arise a problem that the epitaxial layer having crystallinity grows to a thickness insufficient for fabricating the device, and if it exceeds 10 hours, Problems can arise.

The intermixing layers 105 and 106 may have a thickness of 10 nm to 10 μm, preferably 100 nm to 1 μm. If the thickness is out of the above range, if the formed intermixing layer is too thin, there may be a problem that the lift-off does not proceed well due to insufficient space for the selective solution to penetrate during the lift-off process after the epi layer formation.

Next, the step of growing the epitaxial layer 107 on the buffer layer 104 will be described.

The epi layer 107 may be any material that can be used for the epitaxial layer 107, and may preferably include GaN InN.

1E, the epi layer 107 may be formed on the buffer layer 104, and the epi layer 107 may be formed at a temperature of 800 ° C to 1500 ° C, preferably 1000 ° C to 1300 ° C . If the temperature is less than 1000 ° C, the epitaxial layer may have crystallinity and may not be easily grown. If the temperature exceeds 1300 ° C, thermal loss and equipment overloading may occur in the device operation configuration.

The epitaxial layer 107 may have a lattice constant of 3.11 to 3.54 Å, preferably 3.11 to 3.54 Å, a thermal expansion coefficient of 3.17 to 5.6 × 10 ^-6 K ^-1 , preferably 3.17 to 5.5, × 10 ^-6 K ^-1 . If the lattice constant and the thermal expansion coefficient of the epi layer 107 are out of the above ranges, cracking and warping may occur.

The epitaxial layer 107 may have a thickness of 1 nm to 10 占 퐉, and preferably a thickness of 1 占 퐉 to 10 占 퐉. If the thickness is out of the above range, the thickness may be excessively thick. If the thickness is too large, the efficiency may deteriorate due to the thickness of the epi layer, which is unnecessary when fabricating the device. If the thickness is too small, .

On the other hand, the intermediate layer, the buffer layer and the epi layer can satisfy the following relational expression 1, preferably the following relational expression 1-1.

[Relation 1]

Buffer layer melting point (占 폚)? Intermediate layer melting point (占 폚)? Epilayer melting point (占 폚)

[Relational expression 1-1]

Buffer layer melting point (占 폚) <median plane melting point (占 폚) <epilayer melting point (占 폚)

If the above relational expression (1) is not satisfied, it is difficult to eliminate the residual stress and it may be difficult to prevent crystal defects and wafer whip phenomenon.

According to a preferred embodiment of the present invention, the intermediate layer may be a single layer structure or a multi-layer structure. FIG. 2 is a structural view of a template epi substrate having a multi-layered intermediate layer according to a preferred embodiment of the present invention. When a multi-layered intermediate layer is included, an intermixed layer is formed in a region between each intermediate layer. .

Meanwhile, the semiconductor device according to the present invention includes the steps of fabricating a template epi substrate by the above-described manufacturing method, and side-etching at least one intermixing layer formed on at least one side of the intermediate layer of the template epi substrate and the intermediate layer, &Lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt;

3 is a schematic diagram of a process for fabricating a semiconductor device with a template epi substrate, in accordance with a preferred embodiment of the present invention.

First, a template epi substrate is manufactured by the above-described manufacturing method, and a voltage control device (FET), a photodiode (PD), and a light emitting diode (LED) are formed on the epi layer of the template epi substrate as shown in FIG.

3B, one or more intermixing layers formed on at least one side of the intermediate layer and the intermediate layer are side-etched, and the upper side of the intermediate etched intermediate layer and the intermixing layer are lifted off to manufacture a semiconductor device as shown in FIG. 3C can do. The side etch and lift off methods are not limited as long as they are capable of side etching in general.

Hereinafter, the present invention will be described with reference to the following examples. The following examples are provided to illustrate the invention, but the scope of the present invention is not limited by the following examples.

[Example]

Example  One : Template Epi  Fabrication of Substrate

The lattice constant of 5.431Å comprises silicon, the thermal expansion coefficient is 2.6 × 10 ^-6 K ^{- 1} a lattice parameter comprising a compound represented by the following molecular formula 1 to the upper base substrate is 5.567 Å, the thermal expansion coefficient is 5.9 × 10 ^-6 K ^{- 1} linear pattern. A grid including a GaN at 560 ℃ on top of the cap to form a cap layer ^{1, -} then the lattice constant of germanium silicon compound on top of the media layer 5.458Å, the thermal expansion coefficient is 3.26 × 10 ^-6 K 3.189Å constant, thermal expansion coefficient of 3.17 × 10 ^-6 K ^{- 1} was grown in a buffer layer. Then, the temperature was raised to 1000 占 폚 over 5 minutes to form an intermixing layer on the upper and lower surfaces of the intermediate layer. Then, a lattice constant including GaN of 3.189 占 and a thermal expansion coefficient of 3.17 X 10 &lt; ^-6 &gt; K ^{& lt} ; &quot; ¹ &gt; The melting point of the buffer layer was 2500 ° C, the melting point of the intermediate layer was 938 ° C, and the melting point of the epi layer was 2500 ° C. The base substrate had a thickness of 250 μm, the intermediate layer had a thickness of 150 nm, the cap layer had a thickness of 20 nm, The intermixing layer had a thickness of 1.1 m, and the epi layer had a thickness of 1.3 m.

[Molecular formula 1]

Si _1-xy Ge _x Sn _y

X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y.

Example 2

A template epi substrate was prepared in the same manner as in Example 1, except that the side pattern of the intermediate layer was a zigzag pattern.

Example 3

A template epi substrate was prepared in the same manner as in Example 1, except that the side surface pattern of the intermediate layer was an elliptical pattern as shown in FIG. 4A.

Example 4

A template epi substrate was prepared in the same manner as in Example 1 except that the side surface pattern of the intermediate layer was a trapezoidal pattern as shown in FIG. 4D.

Example 5

The template epi substrate was prepared in the same manner as in Example 1, except that the intermediate layer was formed into a three-layer structure as shown in FIG.

101: base substrate 102, 102a to 102c: intermediate layer
103: cap layer 104: buffer layer
105, 106: Intermixing layer 107: Epi layer

Claims (12)

A base substrate having a thickness of 300 占 퐉 to 750 占 퐉;
And a side pattern provided on the base substrate and having a continuous pattern including at least one selected from a linear pattern, a zigzag pattern, a wavy pattern and a rectangular pattern, wherein a thickness of the single layer structure or the multilayer structure is 50 nm to 300 nm A medium layer;
An intermixing layer formed on the upper and lower surfaces of the intermediate layer or the upper and lower surfaces of the intermediate layer of the multi-layer structure of the single layer structure;
A cap layer provided on the intermediate layer and having a thickness of 100 nm to 1 占 퐉;
A buffer layer provided on the cap layer and having a thickness of 500 nm to 2 占 퐉; And
And an epi layer provided on the buffer layer and having a thickness in the range of 1 占 퐉 to 10 占 퐉,
Wherein the intermediate layer comprises a compound that meets the following molecular formula 1,
Wherein the intermediate layer, the buffer layer and the epi layer satisfy the following relational expression 1:
[Molecular formula 1]
Si _1-xy Ge _x Sn _y
X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y.
[Relation 1]
Buffer layer melting point (占 폚)? Intermediate layer melting point (占 폚)? Epilayer melting point (占 폚) delete delete delete delete According to claim 1, wherein the base substrate has a lattice constant of 5.431 ~ 5.657 Å, a thermal expansion coefficient ^{(2.6 ~ 5.9) × 10 -6} K -1,
The intermediate layer has a lattice constant of 5.431 ~ 5.83 Å, a thermal expansion coefficient ^{(2.6 ~ 13) × 10 -6} K -1,
Wherein the cap layer has a lattice constant of 5.431 to 5.83 Å, a thermal expansion coefficient of (2.6 to 13) × 10 ^-6 K ^-1 ,
The buffer layer has a lattice constant of 3.11 ~ 3.54 Å, a thermal expansion coefficient ^{(3.17 ~ 5.6) × 10 -6} K -1 and
Wherein the epitaxial layer has a lattice constant of 3.11 to 3.54 A and a thermal expansion coefficient of (3.17 to 5.6) x 10 &lt; ^-6 &gt; K &lt; ^-1 &gt;. The method of claim 1, wherein the base substrate comprises at least one selected from silicon and germanium, the intermediate layer comprises at least one selected from silicon, germanium, tin, and compounds thereof, , Tin, and a compound thereof, wherein the buffer layer includes a nitride based material including GaN and AlN, and the epi layer includes a nitride based material including GaN and AlN. Epi substrate. Forming a single layer or multilayered intermediate layer on the base substrate having a continuous pattern of side patterns comprising at least one selected from a linear pattern, a zigzag pattern, a wavy pattern and a rectangular pattern;
Growing a cap layer on top of the intermediate layer and growing a buffer layer on top of the cap layer;
Performing a heat treatment to form an intermixing layer on upper and lower surfaces of the intermediate layer; And
And growing an epi layer on top of the buffer layer,
Wherein the intermediate layer comprises a compound that meets the following molecular formula 1,
The base substrate provided on the manufactured template epitaxial substrate has a thickness of 300 탆 to 750 탆, the intermediate layer has a thickness of 50 nm to 300 nm, the cap layer has a thickness of 100 nm to 1 탆, 2 占 퐉 and the epilayer has a thickness of 1 占 퐉 to 10 占 퐉,
Wherein the intermediate layer, the buffer layer, and the epi layer satisfy the following relational expression 1:
[Molecular formula 1]
Si _1-xy Ge _x Sn _y
X and y are rational numbers satisfying 0 <x + y <1, 0 <x, 0 <y.
[Relation 1]
Buffer layer melting point (占 폚)? Intermediate layer melting point (占 폚)? Epilayer melting point (占 폚) 9. The method of claim 8, wherein growing the buffer layer is performed at 500 DEG C to 800 DEG C for 1 minute to 10 hours,
Wherein the step of forming the intermixing layer is performed at 800 ° C to 1500 ° C for 1 minute to 10 hours. 9. The method of claim 8, wherein the intermixing layer is formed by deforming at least a part of at least one layer selected from a base substrate, an intermediate layer and a cap layer. 8. A substrate comprising a template epitaxial substrate according to any one of claims 1, 6 and 7,
Wherein at least one intermixing layer formed on at least one side of the intermediate layer and the intermediate layer is side-etched. 10. A method for manufacturing a template epitaxial substrate, comprising: preparing a template epitaxial substrate by the manufacturing method according to any one of claims 8 to 10; And
And side-etching at least one intermixing layer formed on at least one side of the intermediate layer of the template epi substrate and the intermediate layer to manufacture a semiconductor device.

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