KR101842875B1 - Thin film deposition method and thin film deposition structure - Google Patents

Thin film deposition method and thin film deposition structure Download PDF

Info

Publication number
KR101842875B1
KR101842875B1 KR1020150087337A KR20150087337A KR101842875B1 KR 101842875 B1 KR101842875 B1 KR 101842875B1 KR 1020150087337 A KR1020150087337 A KR 1020150087337A KR 20150087337 A KR20150087337 A KR 20150087337A KR 101842875 B1 KR101842875 B1 KR 101842875B1
Authority
KR
South Korea
Prior art keywords
mixed gas
single crystal
silicon
time
layer
Prior art date
Application number
KR1020150087337A
Other languages
Korean (ko)
Other versions
KR20160149753A (en
Inventor
이현호
김경민
김지훈
노승완
안태산
이관우
Original Assignee
주성엔지니어링(주)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주성엔지니어링(주) filed Critical 주성엔지니어링(주)
Priority to KR1020150087337A priority Critical patent/KR101842875B1/en
Publication of KR20160149753A publication Critical patent/KR20160149753A/en
Application granted granted Critical
Publication of KR101842875B1 publication Critical patent/KR101842875B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/205—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/203—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy using physical deposition, e.g. vacuum deposition, sputtering
    • H01L21/2033—Epitaxial deposition of elements of Group IV of the Periodic System, e.g. Si, Ge

Abstract

One embodiment of the thin film deposition method is a method for depositing a thin film on an epi layer formed of a silicon single crystal (Si) and a silicon oxide (SiO) deposited on a substrate, wherein the epilayer includes silane, SiH 4 ) And a mixture of disilane (Si 2 H 6 ); A deposition step of depositing a silicon single crystal silicon layer on the upper surface of the silicon single crystal in the epi layer; And a mixed gas purge step of exhausting the mixed gas out of the process chamber.

Description

[0001] The present invention relates to a thin film deposition method and a thin film deposition structure,

Embodiments relate to a thin film deposition method and a thin film deposition structure capable of increasing the speed of the process while having a high step coverage and an excellent quality with a low surface roughness and a thin film deposited by a simple method.

The contents described in this section merely provide background information on the embodiment and do not constitute the prior art.

In general, a semiconductor memory device, a liquid crystal display device, an organic light emitting device, and the like are manufactured by stacking a structure having a desired shape by performing a plurality of semiconductor processes on a substrate. The semiconductor manufacturing process includes a process of depositing a predetermined thin film on a substrate, a photolithography process of exposing a selected region of the thin film, an etching process of removing a thin film of the selected region, and the like. A substrate processing process for manufacturing such a semiconductor is performed in a substrate processing apparatus including a process chamber having an optimal environment for the process.

In the thin film deposition process during the substrate processing process, the deposited thin film has a high step coverage and an excellent quality with low surface roughness, and at the same time, it is necessary to lower the production cost by increasing the process speed.

In general, to achieve the above-mentioned object, the process parameters during the process, that is, the temperature of the process chamber, the pressure, and the flow rate of the process gas flowing into the process chamber are adjusted.

However, there are limitations in controlling the temperature or the pressure of the process chamber and the flow rate of the process gas, so that complicated control of the entire substrate processing apparatus including the process chamber is required.

Therefore, the embodiment relates to a thin film deposition method and a thin film deposition structure which can increase the speed of the process while having a high step coverage and an excellent quality with a low surface roughness, and a thin film deposited by a simple method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

One embodiment of the thin film deposition method is a method for depositing a thin film on an epi layer formed of a silicon single crystal (Si) and a silicon oxide (SiO) deposited on a substrate, wherein the epilayer includes silane, SiH 4 ) And a mixture of disilane (Si 2 H 6 ); A deposition step of depositing a silicon single crystal silicon layer on the upper surface of the silicon single crystal in the epi layer; And a mixed gas purge step of exhausting the mixed gas out of the process chamber.

The mixed gas injection step, the deposition step, and the mixed gas purge step may be repeated a plurality of times.

The mixed gas may be such that an injection amount of each of the silane and the disilane is maintained at a ratio of disilane: silane = 1: 24 to 30, and is sprayed onto the substrate.

The silicon layer is formed of a plurality of layers, and the mixed gas injection step, the deposition step, and the mixed gas purge step may be repeated until the silicon layer forms a plurality of uniform layers and a thickness.

The mixed gas may be one that delays the incubation time for deposition of the silicon layer.

And the silicon single crystal may be deposited only on the upper surface of the silicon single crystal during the incubation time.

The mixed gas purge step may be performed at the incubation time.

The epi layer and the silicon layer may be stacked in a recessed gap of the substrate.

One embodiment of a thin film deposition structure includes a substrate on which a recessed gap is formed; An epi layer deposited on a lower portion of the gap; And a silicon layer stacked on the upper surface of the epi layer within the gap.

The epi layer may be made of silicon single crystal and silicon oxide.

In the embodiment, the use of the silane and the disilane in combination with the appropriate ratio of the silane to the thin film deposition makes it possible to produce a thin film deposited substrate having a high deposition rate, excellent step coverage and low surface roughness.

In the embodiment, since the mixed gas purge step can be completed at the incubation time, the thin film deposition time can be reduced.

In the embodiment, thin film deposition is performed using a mixed gas of silane and disilane, thereby improving the deposition rate of the thin film and reducing the deposition time of the thin film.

In addition, since the mixed gas does not contain the etching material, a part of the silicon single crystal is not etched during the deposition of the silicon single crystal, thereby reducing the deposition time of the thin film.

1 is a view illustrating a substrate processing apparatus and a process chamber in which a thin film deposition method according to an embodiment is performed.
2 is a flowchart illustrating a method of depositing a thin film according to an embodiment.
3 is a graph showing the injection amount of silane and disilane and the deposition rate according to one embodiment.
4 is a graph for explaining the relationship between the deposition time and the deposition thickness of the silicon layer according to one embodiment.
5 is a cross-sectional view illustrating a thin film deposition structure according to an embodiment.
6 is a cross-sectional view illustrating a thin film deposition structure according to another embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The embodiments are to be considered in all aspects as illustrative and not restrictive, and the invention is not limited thereto. It is to be understood, however, that the embodiments are not intended to be limited to the particular forms disclosed, but are to include all modifications, equivalents, and alternatives falling within the spirit and scope of the embodiments. The sizes and shapes of the components shown in the drawings may be exaggerated for clarity and convenience.

The terms "first "," second ", and the like can be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. In addition, terms specifically defined in consideration of the constitution and operation of the embodiment are only intended to illustrate the embodiments and do not limit the scope of the embodiments.

In the description of the embodiments, when it is described as being formed on the "upper" or "on or under" of each element, the upper or lower (on or under Quot; includes both that the two elements are in direct contact with each other or that one or more other elements are indirectly formed between the two elements. Also, when expressed as "on" or "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

It is also to be understood that the terms "top / top / top" and "bottom / bottom / bottom", as used below, do not necessarily imply nor imply any physical or logical relationship or order between such entities or elements, But may be used only to distinguish one entity or element from another entity or element.

1 is a view illustrating a substrate processing apparatus and a process chamber in which a thin film deposition method according to an embodiment is performed.

The substrate processing apparatus includes a processing chamber 100 having a reaction space, a substrate mounting part 200 provided in the processing chamber 100 to support at least one substrate 10, And a gas supply unit 400 provided outside the process chamber 100 and supplying a process gas to the gas distribution apparatus 300. The gas distribution unit 300 is provided at the other side of the process chamber 100, . ≪ / RTI > Further, it may further include an exhaust unit 500 for exhausting the inside of the process chamber 100.

The process chamber 100 may be provided in a cylindrical shape having a space for deposition of the substrate 10 therein. The process chamber 100 may be provided in various shapes according to the shape of the substrate 10.

 In the process chamber 100, the substrate seating part 200 and the gas distribution device 300 may be opposed to each other. For example, a substrate seating part 200 may be provided below the process chamber 100, and a gas distribution device 300 may be provided above the process chamber 100. In addition, the process chamber 100 may be provided with a substrate entry / exit port 110 through which the substrate 10 is drawn in and withdrawn. The process chamber 100 may be provided with a gas inlet 120 connected to a gas supply unit 400 for supplying a process gas into the process chamber 100.

The process chamber 100 is provided with an exhaust port 130 for regulating the internal pressure of the process chamber 100 and for exhausting process gas and other foreign substances in the process chamber 100, The base 500 may be connected.

For example, the substrate inlet 110 may be sized to allow the substrate 10 to enter and exit a side of the process chamber 100, and a gas inlet 120 may be provided to the top of the process chamber 100 And the exhaust port 130 may be provided through the side wall or the lower wall of the process chamber 100 at a position lower than the substrate seating portion 200. [

The substrate seating part 200 is installed inside the process chamber 100 and accommodates at least one substrate 10 to be introduced into the process chamber 100. The substrate seating part 200 may be provided at a position opposite to the gas distribution device 300. For example, the substrate mounting part 200 may be provided on the lower side of the process chamber 100, and the gas distribution device 300 may be provided on the upper side of the process chamber 100.

The elevation device 210 for moving the substrate seating part 200 up and down may be provided under the substrate seating part 200. The elevating device 210 is provided to support at least one area of the substrate seating part 200, for example, a central part thereof. When the substrate 10 is placed on the substrate seating part 200, To move closer to the dispensing device 300.

In addition, a heater (not shown) may be mounted inside the substrate seating part 200. The heater generates heat at a predetermined temperature and heats the substrate 10, so that the thin film deposition process, the etching process, and the like can be easily performed on the substrate 10.

The gas distribution apparatus 300 is disposed on the upper side of the process chamber 100 to inject the process gas toward the substrate 10 placed on the substrate seating unit 200. The gas distribution device 300 may be formed in a shape corresponding to the shape of the substrate 10, such as a substrate seating part 200, and may be formed in a substantially circular shape or a square shape.

Meanwhile, the gas distribution apparatus 300 may include a top plate 310, a shower head 320, and a side wall plate 330. The upper plate 310 may be connected to the gas supply unit 400 by forming a gas inlet 120 in the same manner as the upper wall of the process chamber 100.

The shower head 320 is spaced apart from the upper plate 310 by a predetermined distance, and a plurality of ejection holes (not shown) may be formed. The side wall plate 330 may be provided to seal the space between the top plate 310 and the shower head 320.

The gas supply unit 400 may include a gas supply source 410 that supplies each of the plurality of process gases and a gas supply pipe 420 that supplies the process gas from the gas supply source 410 into the process chamber 100. On the other hand, the process gas may include a source material for thin film deposition, an etchant material for etching, a purge gas for purge within the process chamber, and the like.

The exhaust unit 500 may include an exhaust unit 510 and an exhaust pipe 520 connected to the exhaust port 130 of the process chamber 100. The exhaust device 510 may be a vacuum pump or the like and may be configured to vacuum-suck the inside of the process chamber 100 to a pressure close to a vacuum, for example, a pressure of 0.1 mTorr or lower.

The substrate processing apparatus may further include an RF power supply unit 600 having an RF power supply 620 and an impedance matching box (IM.B) 610. The RF power supply unit 600 may generate a plasma in the process gas using the top plate 310 of the gas distribution apparatus 300 as a plasma electrode.

An RF power source 620 for supplying RF power is connected to the top plate 310 and an impedance matching box for matching the impedance so that maximum power can be applied between the top plate 310 and the RF power source 620. [ (610) may be located.

2 is a flowchart illustrating a method of depositing a thin film according to an embodiment. The thin film deposition method may include a mixed gas injection step (S110), a deposition step (S120), and a mixed gas purge step (S130).

In the mixed gas injection step (S110), the mixed gas may be injected into the epi layer (730) deposited on the substrate (10). At this time, the epi layer may be composed of, for example, silicon single crystal (Si) and silicon oxide (SiO). That is, the epitaxial layer may be formed in a state where the silicon single crystal and the silicon oxide are mixed.

In an embodiment, the mixed gas may be a mixture of precursors containing a plurality of silicones. At this time, the precursor may be, for example, silane (SiH 4 ) or disilane (Si 2 H 6 ).

Silane is a material with properties of uniform deposition, that is, excellent step coverage. Disilanes are materials with low surface roughness and high deposition rate due to their low thermal decomposition temperature and high surface mobility.

Therefore, in the embodiment, the use of the silane and the disilane in a suitable combination for the thin film deposition can produce a thin film deposition substrate having a high deposition rate, excellent step coverage, and low surface roughness.

Meanwhile, the mixed gas may be, for example, a mixture of silane and disilane at a certain ratio, and the injection rate of each of silane and disilane may be controlled to maintain a constant mixing ratio of silane and disilane.

At this time, the mixed gas may be sprayed on the substrate while keeping the ratio of disilane: silane = 1: 24 to 30, respectively. More preferably, the mixed gas can maintain the atomic amount of each of the silane and the disilane at a ratio of 1: 26 of the desilane: silane.

Therefore, the mixed gas is injected onto the substrate 10 while keeping the injection amount of the silane and the disilane at a predetermined ratio, and the silicon contained in the silane and the disilane is deposited on the substrate 10, A silicon layer 710 may be formed.

Meanwhile, the silicon layer 710 may be deposited on the upper surface of the epi layer 730 provided on the lower side. At this time, the epi layer 730 and the silicon layer 710 may be stacked in a recess 11 of the substrate 10, for example.

In addition, the silicon layer 710 may be stacked on the upper surface of the epi-layer 730 in the gap 11. The structure in which the silicon layer 710 and the epi layer 730 are stacked will be described in detail with reference to FIG.

In the deposition step S120, the silicon layer 710 made of silicon single crystal may be deposited on the epi layer 730 by silane and disilane contained in the gas mixture to be injected.

The silicon layer 710 may be formed by stacking a plurality of individual silicon layers formed through the repeated mixed gas injection step S110 and the deposition step S120.

Therefore, in the case of forming the silicon layer 710, after one unit of the mixed gas injection step S110 and the deposition step S120 are completed and a unit silicon layer is formed, the mixed gas injection step S110 and the deposition step (S120) may be repeated to form another unit silicon layer.

In the mixed gas purging step (S130), the mixed gas may be purged. That is, in the mixed gas purging step (S130), the purge gas may be used to discharge the mixed gas remaining in the process chamber and other foreign substances to the outside of the process chamber.

After the deposition step (S120) is completed, the purge gas is introduced into the process chamber and the mixed gas purging step (S130) may proceed. Therefore, in the mixed gas purging step (S130), unnecessary mixed gas and other foreign substances are discharged to the outside of the process chamber, and the quality of the thin film is prevented from being deteriorated due to foreign matter.

As described above, the silicon layer 710 may be formed by sequentially stacking a plurality of unit silicon layers. Accordingly, the mixed gas injection step S110, the deposition step S120 and the mixed gas purge step S130 can be repeated a plurality of times, and the silicon layer 710 can be formed as a plurality of uniform layers and a thickness It can be repeated until it is formed.

In the surface layer deposition step, the surface layer 720 may be deposited on the silicon layer 710. The surface layer 720 may be formed on the upper surface of the silicon layer 710 and the upper surface of the substrate 10.

Like the silicon layer 710, the surface layer 720 may be formed by sequentially stacking a plurality of unit silicon layers. Thus, the surface layer deposition step may be repeated until the surface layer 720 forms a plurality of uniform layers. The surface layer 720 will be described in detail with reference to FIG.

3 is a graph showing the injection amount of silane and disilane and the deposition rate according to one embodiment. 3, the x-axis represents the injection amount of silane (SiH 4 ), the y-axis represents the injection amount of the disilane (Si 2 H 6 ), and the z-axis represents the deposition rate of silicon relative to the substrate 10.

At this time, the injection amount of the silane and the disilane is expressed by the volumetric flow rate per minute (sccm, cm3 / min). In addition, the deposition rate is expressed as the thickness at which the thin film is deposited per minute.

As can be seen from FIG. 3, as the injection amount of silane and disilane increases, the deposition rate may also increase. Therefore, the injection amount of silane and disilane can be controlled at a constant ratio, and the ratio of silane to disilane in the injection amount of the mixed gas can be maintained constant.

At this time, the ratio of silane to disilane can be appropriately selected in consideration of the deposition rate of the thin film, the step coverage, the surface roughness, and the like.

4 is a graph for explaining the relationship between the deposition time and the deposition thickness of the silicon layer 710 according to one embodiment.

B graph shows a change in the deposition thickness with respect to the deposition time of the thin film of the silicon layer 710 when the epilayer 730 is a silicon single crystal and a mixed material of silane and disilane is used as a precursor .

C graph shows a change in the deposition thickness versus the deposition time of the thin film of silicon layer 710 when epilayer 730 is silicon oxide and a mixed material of silane and disilane is used as precursor .

At this time, the mixing ratios of silane and disilane in the B graph and the C graph are the same or extremely similar. Also, T2 and T3 represent the incubation time for each of the conditions of the B graph and the C graph. The incubation time means the time at which the first thin film deposition occurs from when the mixed gas is injected onto the substrate 10.

In the B and C graphs, there is a difference in incubation time between T2 and T3. This is because the crystal structures of silicon single crystals and silicon oxides are different.

That is, when the silicon single crystal is deposited on a homogeneous silicon single crystal having the same crystal structure, the incubation time is shorter than that when the silicon single crystal is deposited on a heterogeneous silicon oxide having a different crystal structure.

Therefore, as shown in the graph, the incubation time T2 when the silicon single crystal is deposited on the silicon single crystal is shorter than the incubation time T3 when the silicon single crystal is deposited on the silicon oxide.

The incubation time is suitably between 60 seconds and 120 seconds, and if it exceeds about 120 seconds, deposition also occurs on silicon oxide (SiO), so that it is difficult to form a silicon layer composed only of the desired silicon single crystal (Si).

The silicon single crystal is not deposited on the substrate 10 at the same time as the mixed gas is injected into the substrate 10, and the deposition is first generated after a predetermined time, and the time interval between the injection and deposition is referred to as the incubation time have. Such incubation time may vary depending on the kind of the mixed gas, the material of the part to be deposited, and the like.

As shown in Fig. 4, the incubation times (T2, T3) when a silane and a disilane mixture are used as a precursor, such as a B graph or a C graph, can be longer than when only silane is used as a precursor.

Therefore, the precursor in which the silane and the disilane are mixed in the embodiment can serve to delay the incubation time. The mixed gas purging step (S130) may proceed at the incubation time. That is, the inside of the process chamber 100 can be purged by injecting the purge gas at the incubation time.

That is, the deposition of the substrate 10 can proceed with the purging of the inside of the process chamber 100 during the incubation time by using the characteristic that the precursor contained in the mixed gas is sprayed and contacted with the thin film and then the incubation time passes .

In order to completely discharge unnecessary mixed gas or other foreign matter to the outside of the process chamber 100 in the mixed gas purge step S130, it is necessary to secure a sufficient time for the purge gas to be injected.

Thus, in an embodiment, the precursor mixture of silane and disilane can be used to sufficiently delay the incubation time to complete the mixed gas purge step (S130) at the incubation time.

The deposition step (S120) and the mixed gas purge step (S130) may be sequentially performed at the incubation time. In Fig. 4, a silicon single crystal is deposited on the silicon single crystal at a time between T1 and T2, but no silicon single crystal is deposited on the silicon oxide.

Accordingly, at the time between T1 and T2, the silicon single crystal is first deposited on the silicon single crystal (S120), and then the mixed gas purge step (S130) is performed.

In this case, since the silicon single crystal is not deposited on the silicon oxide, the silicon layer 710 in which the silicon single crystal is repeatedly deposited on the silicon single crystal can be formed.

Therefore, in the embodiment, the mixed gas purging step (S130) can be completed at the incubation time, and thus the thin film deposition time can be reduced.

At this time, in order to complete the mixed gas purging step (S130) within the incubation time, it is necessary to make the incubation time equal to or longer than the purge time. For this purpose, it is necessary to sufficiently delay the incubation time by controlling the mixing ratio of silane and disilane in the mixed gas and the material of the epi-layer 730.

Meanwhile, as shown in FIG. 4, it can be seen that the amount of change in the deposition thickness with respect to the deposition time of the B graph and the C graph, that is, the deposition rate is considerably large. Although not shown, the deposition rate is smaller than the B graph or the C graph when using a source material consisting only of silane. This means that the deposition rate of the source material in which the silane and the disilane are mixed is higher than that of the source material composed only of the silane.

Such a deposition rate can be further improved by controlling the ratio of silane to disilane in the mixed gas as described in FIG. Therefore, in the embodiment, thin film deposition is performed using a mixed gas of silane and disilane, thereby improving the deposition rate of the thin film, thereby reducing the deposition time of the thin film.

Meanwhile, in the embodiment, the mixed gas may not contain an etching material such as a chemical substance including chlorine (Cl 2 ) or chlorine, for example. The etchant is not a material for conducting the etching process but a material contained in a precursor used in the deposition process.

The precursor contained in the mixed gas for the thin film deposition may include the etching material. When such an etching material is included, the silicon single crystal to be deposited may be etched by the etching material during the deposition process. Therefore, when an etching material is contained in the mixed gas, the thin film deposition rate may be reduced and the thin film deposition time may be increased.

However, since the etching gas is not contained in the mixed gas in the embodiment, a part of the silicon single crystal is not etched during the deposition of the silicon single crystal, thereby reducing the deposition time of the thin film.

5 is a cross-sectional view illustrating a thin film deposition structure according to an embodiment. The thin film deposition structure may be formed by the thin film deposition method described above and may include a substrate 10, an epilayer 730, a silicon layer 710 and a surface layer 720.

The substrate 10 is formed with a recessed gap 11 and a thin film can be deposited on the gap 11 and the upper surface of the substrate 10. [ A portion of the epilayer 730, the silicon layer 710 and the surface layer 720 may be sequentially stacked in the gap 11 so that the gap 11 may be completely filled.

The epitaxial layer 730 may be stacked on the lower portion inside the gap 11, and may be made of, for example, silicon single crystal and silicon oxide. A mixed gas of silane and disilane is sprayed on the upper surface of the epi layer 730 to stack the silicon layer 710.

The silicon layer 710 may be stacked on the upper surface of the epi layer 730 within the gap 11, and a plurality of unit silicon layers may be sequentially stacked.

The silicon layer 710 may be formed by repeating the mixed gas injection step S110, the deposition step S120, and the mixed gas purge step S130, as described above. Meanwhile, the silicon layer 710 may be formed of a silicon single crystal as described above.

The surface layer 720 may be stacked on the upper surface of the silicon layer 710 and the upper surface of the substrate 10. [ 5, a part of the silicon can be stacked on the upper surface of the first silicon to fill the gap 11, and the remainder can be formed on the upper surface of the substrate 10 and the upper side of the portion filled with the gap 11 As shown in FIG.

The surface layer 720 may be made of, for example, silicon single crystal or silicon oxide. In addition, the surface layer 720 may be formed by sequentially stacking a plurality of unit silicon layers in the same manner as the silicon layer 710, for example.

6 is a cross-sectional view illustrating a thin film deposition structure according to another embodiment. In FIG. 6, the second epi-layer 730-1 is formed on the surface of the substrate 10, and the second epi-layer 730-1 is formed of silicon oxide (SiO). In this case, the silicon layer 710 formed of silicon single crystal (Si) may be stacked on the gap 11 by the following method.

4, the silicon single crystal is first deposited on the silicon single crystal at a time between T1 and T2, and then the mixed gas is purged (S130). Then, . That is, the silicon single crystal can be prevented from being deposited on the second epi-layer 730-1 by advancing the mixed gas purging step (S130) before the time T2 when the silicon single crystal is deposited on the silicon oxide.

In this case, a silicon single crystal is not deposited on the second epi layer 730-1 formed of silicon oxide, and a silicon layer 710 is formed in which a silicon single crystal is repeatedly deposited on the silicon single crystal in the gap 11 .

When the mixed gas injection step (S110), the deposition step (S120) and the mixed gas purge step (S130) are repeated in the above-described manner, no silicon single crystal is deposited on the second epi layer (730-1) A silicon layer 710 formed of silicon single crystal may be formed.

After the silicon layer 710 is formed to the designed height or volume in the gap 11, the thin film deposition process may be completed on the substrate 10 by proceeding to the surface layer deposition step as described above.

While only a few have been described above with respect to the embodiments, various other forms of implementation are possible. The technical contents of the embodiments described above may be combined in various forms other than the mutually incompatible technologies, and may be implemented in a new embodiment through the same.

S110: Mixed gas injection step
S120: deposition step
S130: Mixed gas purge step
10: substrate
11: Gap
710: Silicon layer
720: Surface layer
730: epi layer

Claims (10)

On an epi layer made of silicon single crystal (Si) and silicon oxide (SiO) deposited on a substrate,
A mixed gas injection step of injecting a mixed gas containing a silane (SiH 4 ) and a disilane (Si 2 H 6 ) mixture into the epi layer;
A deposition step of depositing a silicon single crystal silicon layer on the upper surface of the silicon single crystal in the epi layer; And
A mixed gas purge step of exhausting the mixed gas out of the process chamber
Lt; / RTI >
A thin film deposition method having an incubation time for depositing the silicon layer on the epi layer,
The incubation time may be,
A first time which is an incubation time when the silicon single crystal is deposited on the silicon single crystal and a second time which is an incubation time when the silicon single crystal is deposited on the silicon oxide longer than the first time,
The mixed gas includes,
Does not contain chemicals including chlorine (Cl 2 ) or chlorine, delays the incubation time,
Wherein the mixed gas purge step is performed at the incubation time. The method according to claim 1,
Wherein the deposition step and the mixed gas purge step are performed at a time between the first time end point and the second time end point. The method according to claim 1,
The mixed gas includes,
Wherein a spray amount of each of the silane and the disilane is maintained at a ratio of disilane: silane = 1: 24 to 30, and is sprayed onto the substrate. The method according to claim 1,
Wherein the silicon layer is formed of a plurality of layers and the mixed gas injection step, the deposition step and the mixed gas purge step are repeated until the silicon layer forms a plurality of uniform layers and a thickness. . delete The method according to claim 1,
Wherein the silicon single crystal is deposited only on the upper surface of the silicon single crystal during the incubation time. 3. The method of claim 2,
Wherein the mixed gas injection step, the deposition step, and the mixed gas purge step are sequentially and repeatedly performed. The method according to claim 1,
Wherein the epitaxial layer and the silicon layer are stacked within a recessed gap of the substrate. A substrate on which a recessed gap is formed;
An epitaxial layer stacked on the lower portion of the gap and made of silicon single crystal (Si) and silicon oxide (SiO); And
A silicon single crystal silicon layer is formed on the upper surface of the silicon single crystal in the epitaxial layer,
/ RTI >
A thin film deposition structure in which deposition is performed with an incubation time for depositing the silicon layer on the epi layer,
A mixed gas containing a mixture of silane (SiH 4 ) and disilane (Si 2 H 6 ) is sprayed on the epi layer to deposit the silicon layer on the upper surface of the epi layer,
The incubation time may be,
A first time which is an incubation time when the silicon single crystal is deposited on the silicon single crystal and a second time which is an incubation time when the silicon single crystal is deposited on the silicon oxide longer than the first time,
The mixed gas includes,
Does not contain chemicals including chlorine (Cl 2 ) or chlorine, delays the incubation time,
Wherein the purging of the mixed gas proceeds at the incubation time. 10. The method of claim 9,
The deposition of the silicon layer and the purging of the mixed gas proceed on the epi layer at a time between the first time end point and the second time end point,
Wherein the spraying of the mixed gas, the deposition of the silicon layer, and the spreading of the mixed gas proceed sequentially and repetitively.
KR1020150087337A 2015-06-19 2015-06-19 Thin film deposition method and thin film deposition structure KR101842875B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020150087337A KR101842875B1 (en) 2015-06-19 2015-06-19 Thin film deposition method and thin film deposition structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020150087337A KR101842875B1 (en) 2015-06-19 2015-06-19 Thin film deposition method and thin film deposition structure

Publications (2)

Publication Number Publication Date
KR20160149753A KR20160149753A (en) 2016-12-28
KR101842875B1 true KR101842875B1 (en) 2018-03-28

Family

ID=57724658

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020150087337A KR101842875B1 (en) 2015-06-19 2015-06-19 Thin film deposition method and thin film deposition structure

Country Status (1)

Country Link
KR (1) KR101842875B1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2667664B2 (en) * 1987-07-06 1997-10-27 三井東圧化学株式会社 Manufacturing method of silicon single crystal thin film
JP2011134971A (en) * 2009-12-25 2011-07-07 Denso Corp Semiconductor device and method of manufacturing the same
JP2012146741A (en) * 2011-01-07 2012-08-02 Hitachi Kokusai Electric Inc Manufacturing method of semiconductor device, and substrate processing apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2667664B2 (en) * 1987-07-06 1997-10-27 三井東圧化学株式会社 Manufacturing method of silicon single crystal thin film
JP2011134971A (en) * 2009-12-25 2011-07-07 Denso Corp Semiconductor device and method of manufacturing the same
JP2012146741A (en) * 2011-01-07 2012-08-02 Hitachi Kokusai Electric Inc Manufacturing method of semiconductor device, and substrate processing apparatus

Also Published As

Publication number Publication date
KR20160149753A (en) 2016-12-28

Similar Documents

Publication Publication Date Title
TWI736840B (en) Substrate processing method
CN109913852B (en) Method and device for suppressing parasitic plasma on back surface of spray head
TWI644359B (en) Chamber undercoat preparation method for low temperature ald films
US9005459B2 (en) Film deposition method and film deposition apparatus
TWI570890B (en) Method and apparatus for manufacturing memory device having 3-dimensional structure
US10224185B2 (en) Substrate processing apparatus
US20050145170A1 (en) Substrate processing apparatus and cleaning method therefor
KR20010081936A (en) Method for manufacturing a semiconductor device and apparatus for manufacturing a semiconductor
CN108220921A (en) Film formation device and film build method
US20200123656A1 (en) Systems and methods for a plasma enhanced deposition of material on a semiconductor substrate
KR100769522B1 (en) Shower head of chemical vapor deposition apparatus
KR20140000447A (en) Apparatus for gas dispenser and substrate treatment
KR101842875B1 (en) Thin film deposition method and thin film deposition structure
KR20080035735A (en) Equipment for plasma enhanced chemical vapor deposition
KR20060014495A (en) Shower head of chemical vapor deposition apparatus
KR101255763B1 (en) Substrate processing method
KR20220098816A (en) Station-to-station control of backside bow compensation deposition
KR20060100961A (en) Showerhead and atomic layer deposition equipment having the same
KR101807567B1 (en) Method and apparatus for forming ald oxide layer
KR102514043B1 (en) Method of manufacturing semiconductor device
KR102181120B1 (en) Apparatus of treating substrate
KR101980313B1 (en) Apparatus for processing substrate
KR100450173B1 (en) Methods and Apparatuses of Chemical Vapor Deposition using diffusion suppressing gasses and devices
KR100957456B1 (en) Thin film layer deposition apparatus using atomic layer deposition method
US20140038421A1 (en) Deposition Chamber and Injector

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
X701 Decision to grant (after re-examination)
GRNT Written decision to grant