KR101816970B1 - 비경쟁 메모리 장치 - Google Patents

비경쟁 메모리 장치 Download PDF

Info

Publication number
KR101816970B1
KR101816970B1 KR1020147017494A KR20147017494A KR101816970B1 KR 101816970 B1 KR101816970 B1 KR 101816970B1 KR 1020147017494 A KR1020147017494 A KR 1020147017494A KR 20147017494 A KR20147017494 A KR 20147017494A KR 101816970 B1 KR101816970 B1 KR 101816970B1
Authority
KR
South Korea
Prior art keywords
memory
access
memory blocks
group
access ports
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147017494A
Other languages
English (en)
Korean (ko)
Other versions
KR20140102718A (ko
Inventor
에프렘 씨 우
기아네쉬 사하리아
Original Assignee
자일링크스 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 자일링크스 인코포레이티드 filed Critical 자일링크스 인코포레이티드
Publication of KR20140102718A publication Critical patent/KR20140102718A/ko
Application granted granted Critical
Publication of KR101816970B1 publication Critical patent/KR101816970B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Dram (AREA)
KR1020147017494A 2011-12-07 2012-09-28 비경쟁 메모리 장치 Active KR101816970B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/314,079 US8611175B2 (en) 2011-12-07 2011-12-07 Contention-free memory arrangement
US13/314,079 2011-12-07
PCT/US2012/058039 WO2013085606A2 (en) 2011-12-07 2012-09-28 Contention-free memory arrangement

Publications (2)

Publication Number Publication Date
KR20140102718A KR20140102718A (ko) 2014-08-22
KR101816970B1 true KR101816970B1 (ko) 2018-01-09

Family

ID=47172872

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147017494A Active KR101816970B1 (ko) 2011-12-07 2012-09-28 비경쟁 메모리 장치

Country Status (7)

Country Link
US (1) US8611175B2 (enExample)
EP (1) EP2788983B1 (enExample)
JP (1) JP5947397B2 (enExample)
KR (1) KR101816970B1 (enExample)
CN (1) CN104106115B (enExample)
IN (1) IN2014CN04171A (enExample)
WO (1) WO2013085606A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8947931B1 (en) * 2014-06-13 2015-02-03 Sandisk Technologies Inc. Memory module
US9864710B2 (en) * 2015-03-30 2018-01-09 EMC IP Holding Company LLC Writing data to storage via a PCI express fabric having a fully-connected mesh topology
JP2018032141A (ja) * 2016-08-23 2018-03-01 東芝メモリ株式会社 半導体装置
US10141938B2 (en) * 2016-09-21 2018-11-27 Xilinx, Inc. Stacked columnar integrated circuits
US10635331B2 (en) * 2017-07-05 2020-04-28 Western Digital Technologies, Inc. Distribution of logical-to-physical address entries across bank groups
US10346093B1 (en) * 2018-03-16 2019-07-09 Xilinx, Inc. Memory arrangement for tensor data
US20200125506A1 (en) * 2018-10-23 2020-04-23 Etron Technology, Inc. Superscalar Memory IC, Bus And System For Use Therein
JP7563082B2 (ja) * 2020-09-29 2024-10-08 富士フイルムビジネスイノベーション株式会社 プログラマブル論理回路、情報処理装置、情報処理システム、及びプログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100655081B1 (ko) 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
US20100329066A1 (en) 2009-06-30 2010-12-30 Infinera Corporation Non-blocking multi-port memory formed from smaller multi-port memories

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145172A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd 試験回路付入出力パツフア
JP2546901B2 (ja) * 1989-12-05 1996-10-23 株式会社日立製作所 通信制御装置
JPH0668022A (ja) * 1992-08-18 1994-03-11 Oki Electric Ind Co Ltd ダイレクトメモリアクセス装置
GB9618137D0 (en) * 1996-08-30 1996-10-09 Sgs Thomson Microelectronics Improvements in or relating to an ATM switch
JP2000209172A (ja) * 1999-01-14 2000-07-28 Matsushita Electric Ind Co Ltd 多重化装置及び多重化システム
KR100546331B1 (ko) * 2003-06-03 2006-01-26 삼성전자주식회사 스택 뱅크들 마다 독립적으로 동작하는 멀티 포트 메모리장치
DE102004038211A1 (de) * 2004-08-05 2006-03-16 Robert Bosch Gmbh Botschaftsverwalter und Verfahren zur Steuerung des Zugriffs auf Daten eines Botschaftsspeichers eines Kommunikationsbausteins
US8547774B2 (en) * 2010-01-29 2013-10-01 Mosys, Inc. Hierarchical multi-bank multi-port memory organization

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100655081B1 (ko) 2005-12-22 2006-12-08 삼성전자주식회사 가변적 액세스 경로를 가지는 멀티 포트 반도체 메모리장치 및 그에 따른 방법
US20100329066A1 (en) 2009-06-30 2010-12-30 Infinera Corporation Non-blocking multi-port memory formed from smaller multi-port memories

Also Published As

Publication number Publication date
IN2014CN04171A (enExample) 2015-07-17
EP2788983B1 (en) 2016-04-06
KR20140102718A (ko) 2014-08-22
US8611175B2 (en) 2013-12-17
WO2013085606A2 (en) 2013-06-13
CN104106115B (zh) 2017-03-22
EP2788983A2 (en) 2014-10-15
JP5947397B2 (ja) 2016-07-06
JP2015506025A (ja) 2015-02-26
CN104106115A (zh) 2014-10-15
US20130148450A1 (en) 2013-06-13
WO2013085606A3 (en) 2014-08-14

Similar Documents

Publication Publication Date Title
KR101816970B1 (ko) 비경쟁 메모리 장치
EP3824392B1 (en) Configurable network-on-chip for a programmable device
KR102381158B1 (ko) 적층형 실리콘 상호 연결(ssi) 기술 통합을 위한 독립형 인터페이스
US10916516B2 (en) High bandwidth memory (HBM) bandwidth aggregation switch
CN113704137B (zh) 存内计算模块和方法、存内计算网络及构建方法
Weldezion et al. Scalability of network-on-chip communication architecture for 3-D meshes
US6237130B1 (en) Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
CN113688065B (zh) 近存计算模块和方法、近存计算网络及构建方法
CN108400880A (zh) 片上网络、数据传输方法和第一交换节点
US9069912B2 (en) System and method of distributed initiator-local reorder buffers
US20210373811A1 (en) Stacked Memory Device with Paired Channels
Mora et al. Towards an efficient switch architecture for high-radix switches
KR20230169096A (ko) 고대역폭 인터페이스를 위한 로컬화된 noc 스위칭 인터커넥트
US7965705B2 (en) Fast and fair arbitration on a data link
CN118012794B (zh) 计算芯粒及电子设备
US9164914B1 (en) Multiple port routing circuitry for flash memory storage systems
CN110825689B (zh) 电子芯片的实现方法及电子芯片
US10763862B1 (en) Boundary logic interface
EP2854042A1 (en) Information processing apparatus, data transfer apparatus, and data transfer method
TWI802275B (zh) 晶片系統架構
US12353717B2 (en) Localized and relocatable software placement and NoC-based access to memory controllers
CN115687242B (zh) 一种利用内置本地串联模块实现模块信号共享的fpga
US20250226818A1 (en) Techniques For Routing Between A Network-On-Chip And Multiplexer Circuits In A Central Region Of An Integrated Circuit
CN103383671A (zh) 一种基于片上网络的dram通讯优化方法
Qi et al. A delay model of two-cycle noc router in 2d-mesh network

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 9