KR101808528B1 - Thin film transistor substrate and method for fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate having a top gate structure and forming a thin film transistor substrate using a total of six masks to improve productivity, yield and reliability, and a manufacturing method thereof The thin film transistor substrate of the present invention includes: a substrate; A first active layer formed on the substrate, the first active layer including a source region and a drain region; A gate insulating film formed on the entire surface of the substrate including the first active layer; A reflective layer formed on the gate insulating layer; A gate line and a gate electrode formed on the same layer as the reflective layer and having a double layer structure in which first and second gate materials are sequentially stacked; A pixel electrode formed to cover the entire surface of the reflective layer and formed of only the first gate material; A first connection electrode formed on a portion of the pixel electrode that does not correspond to the reflective layer; A planarization layer and a protection layer sequentially formed on the entire surface of the gate insulation layer including the first connection electrode; First, second and third contact holes formed by selectively removing the planarization layer and the protection layer and exposing a part of the source region, the drain region and the first connection electrode, respectively; A data line formed on the protective film, a source electrode connected to the source region through the first contact hole, and a drain electrode connected to the drain region through the second contact hole, A drain electrode connected to the drain electrode; And a bank formed on the passivation layer including the source electrode and the drain electrode and having an opening exposing a part of the pixel electrode.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor, and more particularly, to a thin film transistor substrate capable of improving productivity and yield by manufacturing a thin film transistor substrate using six masks, and a manufacturing method thereof.

The image display device that implements various information on the screen is a key technology in the era of information and communication, and it is progressing in the direction of being thinner, lighter, more portable, but higher performance. An organic light emitting display device which controls the amount of light emitted from the organic light emitting layer by using a flat panel display device has recently been attracting attention as a flexible display capable of bending due to space and convenience is required.

The organic light emitting display utilizes an electroluminescence phenomenon in which electrons and holes are injected into an organic light emitting layer by applying an electric field to a cathode and an anode formed at both ends of the organic light emitting layer, and light is emitted by binding energy when the holes are coupled to each other. Electrons and holes are paired in the organic light emitting layer and then emit while falling from the excited state to the ground state.

Such an organic light emitting display device can be formed into a thin film and can be formed on a transparent substrate that can be made of plastic. In addition, the organic light emitting display device can be manufactured at a lower voltage than a plasma display panel (Plasma Display Panel) or an inorganic EL (Electro Luminescence) About 10V or less), and power consumption is relatively low. In addition, it has excellent properties in terms of lightness and color, and has become a target of many people.

On the other hand, the organic light emitting display can be divided into a front emission type and a back emission type according to the direction in which light emitted from the organic emission layer is emitted. The top emission type emits light through a top substrate opposed to a thin film transistor substrate on which a thin film transistor is formed, and a back emission type silver light is emitted toward the thin film transistor substrate. The direction of light emitted from the organic emission layer is downward Lt; / RTI >

Hereinafter, a general top emission type OLED display will be described with reference to the accompanying drawings.

FIG. 1 is a flow chart illustrating a method of manufacturing a general top emission type organic light emitting display device, illustrating a method of manufacturing a thin film transistor substrate, and FIG. 2 is a sectional view of a thin film transistor substrate of a general top emission type organic light emitting display device.

As shown in FIGS. 1 and 2, a general top emission type OLED display device is manufactured in the following order.

First, a gate electrode 11 and a gate pad lower electrode (not shown) are formed on the substrate 10 using a first mask (S5), and then the gate electrode 11 and the gate pad lower electrode (not shown) The gate insulating film 12 is formed on the entire surface of the substrate 10. [ Then, the active layer 13 is formed using the second mask (S10), and the gate insulating film 12 is selectively removed using the third mask to expose a part of the gate pad lower electrode (not shown) A first contact hole (not shown) is formed (S15).

The source and drain electrodes 14a and 14b are formed on the active layer 13 using the fourth mask (S20) and at the same time, the gate pad lower electrode (not shown) is connected to the gate pad via the first contact hole A gate pad upper electrode (not shown) is formed. At this time, the gate electrode 11, the gate insulating film 12, the active layer 13, and the source and drain electrodes 14a and 14b form a thin film transistor.

A protective film 15 is formed on the entire surface of the gate insulating film 12 including the source and drain electrodes 14a and 14b and the gate pad upper electrode (not shown). Then, a protective film 15 is formed on the protective film 15 using a fifth mask The reflection plate 16 is formed (S25).

A second contact hole (not shown) for exposing a part of the drain electrode 14b is formed (S30) by selectively removing the protective film 15 using the sixth mask, A pixel electrode 17 connected to the drain electrode 14b is formed through a contact hole (not shown) (S35). Finally, a bank 18 having an opening for exposing a part of the pixel electrode 17 is formed (S40) by using the eighth mask.

However, in the bottom gate structure of the thin film transistor as described above, when light generated in the organic light emitting layer is incident on the active layer 13, the thin film transistor may deteriorate, resulting in a failure of the organic light emitting display device. In addition, since the general thin film transistor substrate is manufactured by a process using 8 to 9 masks, the manufacturing cost is increased and the productivity and the yield are lowered.

Furthermore, when the etch process is performed to form the source electrode 14a and the drain electrode 14b, it is possible to prevent the source electrode 14a and the drain electrode 14b from being etched to the active layer 13 under the source electrode 14a and the drain electrode 14b If an etch stopper (not shown) is formed on the active layer 13, misalignment may occur between the gate electrode and the source and drain electrodes and between the source and drain electrodes and the etch stopper. have. Therefore, since an overlap design of several um or more is required in terms of the process margin, parasitic capacitance between the electrodes increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a thin film transistor having a top gate structure and a thin film transistor substrate using six masks in total to improve productivity, yield and reliability And a method of manufacturing the same.

According to an aspect of the present invention, there is provided a thin film transistor substrate comprising: a substrate; A first active layer formed on the substrate, the first active layer including a source region and a drain region; A gate insulating film formed on the entire surface of the substrate including the first active layer; A reflective layer formed on the gate insulating layer; A gate line and a gate electrode formed on the same layer as the reflective layer and having a double layer structure in which first and second gate materials are sequentially stacked; A pixel electrode formed to cover the entire surface of the reflective layer and formed of only the first gate material; A first connection electrode formed on a portion of the pixel electrode that does not correspond to the reflective layer; A planarization layer and a protection layer sequentially formed on the entire surface of the gate insulation layer including the first connection electrode; First, second and third contact holes formed by selectively removing the planarization layer and the protection layer and exposing a part of the source region, the drain region and the first connection electrode, respectively; A data line formed on the protective film, a source electrode connected to the source region through the first contact hole, and a drain electrode connected to the drain region through the second contact hole, A drain electrode connected to the drain electrode; And a bank formed on the passivation layer including the source electrode and the drain electrode and having an opening exposing a part of the pixel electrode.

The first gate material is selected from among transparent conductive materials such as ITO, IZO and ITZO.

And a gate pad and a data pad formed on the same layer as the pixel electrode and formed of the first gate material.

A second connection electrode is further formed on a part of the data pad, and the data line and the data pad are connected through the second connection electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, including: forming a first active layer on a substrate using a first mask; Forming a gate insulating film on the entire surface of the substrate including the first active layer; Forming a reflective layer on the gate insulating layer using a second mask; A gate electrode and a gate electrode of a double layer structure in which first and second gate materials are sequentially stacked on the same layer as the reflective layer by using a third mask and a gate electrode and a gate electrode which are formed only of the first gate material Forming a pixel electrode having a single layer structure and forming a first connecting electrode on a partial region of the pixel electrode not corresponding to the reflective layer; Doping the first active layer on both sides of the gate electrode to form a source region and a drain region; Forming a planarization layer and a passivation layer on the entire surface of the gate insulation layer including the first connection electrode; Forming a first, a second, and a third contact holes exposing a portion of the source region, the drain region, and the first connection electrode, respectively, by selectively removing the planarization layer and the protection layer using a fourth mask; A data line is formed on the protective film using a fifth mask, a source electrode connected to the source region through the first contact hole, and a drain electrode connected to the drain region through the second contact hole, Forming a drain electrode connected to the first connection electrode through the third contact hole; And forming a bank which is formed on the passivation layer including the source electrode and the drain electrode using a sixth mask and has an opening exposing a part of the pixel electrode.

The third mask is a halftone mask.

The step of forming the first active layer further forms a second active layer in the same layer as the first active layer.

Forming a storage upper electrode on the same layer as the pixel electrode and doping the second active layer using the storage upper electrode to form a storage lower electrode.

Forming a gate pad and a data pad with the first gate material in the same layer as the pixel electrode.

And forming a second connection electrode on a portion of the data pad to connect the data pad and the data line.

The step of forming the source region and the drain region uses a plasma doping method.

The thin film transistor substrate of the present invention and its manufacturing method as described above have the following effects.

First, since a thin film transistor substrate is formed using six masks, the manufacturing cost can be reduced, and the yield and productivity can be improved.

Second, a thin film transistor having a top gate structure is formed to prevent light generated in the organic light emitting layer from being incident on the active layer, thereby improving the reliability and stability of the thin film transistor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing a method of manufacturing a general top emission type organic light emitting display device. FIG.
2 is a cross-sectional view of a thin film transistor substrate of a general top emission organic light emitting display.
3 is an equivalent circuit diagram of a basic pixel of an organic light emitting diode display.
4 is a sectional view of a thin film transistor substrate of the present invention.
5A to 5G are process sectional views showing a method of manufacturing the thin film transistor substrate of the present invention.

First, an equivalent circuit diagram of a basic structure of an organic light emitting display will be described.

3 is an equivalent circuit diagram of a basic pixel of an organic light emitting diode display.

3, the basic pixel of the organic light emitting diode display includes a switching thin film transistor T1 connected to a data line DL, a gate line GL and a data line DL that are perpendicular to the gate line GL, A storage capacitor connected between the gate electrode of the driving thin film transistor T2 and the power supply line PL connected to the organic light emitting diode E between the thin film transistor T1 and the power supply line PL, (C).

The switching thin film transistor T1 supplies the data signal of the data line DL to the gate electrode of the driving thin film transistor T2 and the storage capacitor C in response to the scan signal of the gate line GL. The driving thin film transistor T2 controls the brightness of the organic light emitting element E by controlling the current supplied from the power supply line PL to the organic light emitting element E in response to the data signal from the switching thin film transistor T1. do.

The storage capacitor C charges the data signal from the switching thin film transistor T1 and supplies the charged voltage to the driving thin film transistor T2 so that even if the switching thin film transistor T1 is turned off, A constant current can be supplied to the transistor T2.

The organic light emitting display device is developed based on an active matrix type suitable for displaying moving images by independently driving each of three color (R, G, B) sub-pixels constituting one pixel. Each sub-pixel of the active matrix organic light emitting display includes an organic light emitting display element composed of an organic light emitting layer between an anode and a cathode, and a sub pixel driving part independently driving the organic light emitting display element.

The sub-pixel driver includes at least two thin film transistors and a storage capacitor (C), and controls the amount of current supplied to the organic light emitting display device according to the data signal to control the brightness of the organic light emitting display device. The organic light emitting display includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer stacked with an organic material between an anode and a cathode.

When a forward voltage is applied between the anode and the cathode, electrons from the cathode move to the light emitting layer through the electron injection layer and the electron transport layer, and holes from the anode move to the light emitting layer through the hole injection layer and the hole transport layer. The light emitting layer emits light by recombination of electrons from the electron transporting layer and holes from the hole transporting layer, and brightness is proportional to the amount of current flowing between the anode and the cathode.

Hereinafter, the thin film transistor substrate of the present invention will be described in detail.

FIG. 4 is a cross-sectional view of a thin film transistor substrate of the present invention, showing a driving thin film transistor.

4, the thin film transistor substrate of the present invention includes a substrate 200, a buffer layer 205 formed on the substrate 200, a buffer layer 205, and a source region 210c and a drain region 210d. A gate insulating layer 220 formed on the entire surface of the buffer layer 205 including the first active layer, a reflective layer 230 formed on the gate insulating layer 220, and a reflective layer 230 formed on the same layer as the first active layer, , A gate electrode (GL), a gate electrode (230a), and a reflective layer (230) in which first and second gate materials are sequentially stacked. The pixel electrode A first connection electrode 240a formed on a partial area of the pixel electrode 230c which does not correspond to the reflective layer 230 and a second connection electrode 240b formed on the entire surface of the gate insulation layer 220 including the first connection electrode 240a, The film 250 and the protective film 260, the planarization film 250 and the protective film 260 are selectively removed Second and third contact holes (not shown) for exposing a part of the source region 210c, the drain region 210d and the first connection electrode 240a, and a second contact hole A source electrode 270a connected to the source region 210c through a first contact hole (not shown), and a source electrode 270b connected to the drain region 210d through a second contact hole (not shown) And is formed on a protective film 260 including a drain electrode 270b and source and drain electrodes 270a and 270b connected to the first connection electrode 240a through a third contact hole And a bank 280 having an opening exposing a portion of the electrode 230c.

Here, the substrate 200 may be an insulating glass, a plastic, a conductive substrate, or a flexible substrate, and the buffer layer 210 formed on the entire surface of the substrate 200 may be omitted if necessary.

The first active layer 210a is an oxide layer such as IZO (Indium Zinc Oxide), GZO (Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or the like, and a storage lower electrode 210e is formed on the same layer as the first active layer Lt; / RTI > The reflective layer 230 is made of a metal having a high reflectance such as aluminum (Al) and silver (Ag) to improve light efficiency.

The thin film transistor including the first active layer, the gate electrode 230a and the source and drain electrodes 270a and 270b formed on the substrate 200 may be formed of indium gallium zinc oxide (IGZO), zinc oxide (ZnO) , An oxide thin film transistor (oxide TFT) which is a thin film transistor using an oxide such as TiO 2 (TiO 2), an organic thin film transistor (organic TFT) using an organic material in the active layer channel, and a thin film transistor substrate using amorphous silicon (Amorphous Silicon TFT) and a polysilicon TFT (Thin Film Transistor) for fabricating a thin film transistor substrate using polycrystalline silicon in the active layer channel.

The gate line GL, the gate electrode 230a, the pixel electrode 230c and the first connection electrode 240a are formed on the gate insulating layer 220 using a halftone mask, An electrode 230b, a gate pad 230d, and a data pad 230e are formed.

The gate line GL and the gate electrode 230a have a double layer structure in which first and second gate materials are sequentially stacked and the pixel electrode 230c has a single layer structure composed of only the first gate material, Respectively. In addition, the gate pad 230d and the data pad 230e are also of a single-layer structure composed of the first gate material such as the pixel electrode 230c.

A second connection electrode 240b connecting the data line and the data pad 230d is further formed on a part of the data pad 230e and the first and second connection electrodes 240a and 240b are formed on the second gate Lt; / RTI >

The first gate material may be a conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The second gate material may include neodymium (Nd), copper (Cu) ), Tungsten (W), and molybdenum (Mo), or an alloy thereof.

The planarization layer 250 and the passivation layer 260 may be formed of a material such as SiO ₂ or SiNx. The source, drain and data lines may be formed of a material such as neodymium (Nd), copper (Cu), aluminum (Al) , Tungsten (W), and molybdenum (Mo), or an alloy material thereof.

The first and second contact holes (not shown) expose the source and drain regions 210c and 210d, respectively, and the third contact hole (not shown) exposes the first connection electrode 240a. The fourth and sixth contact holes (not shown) expose the gate pad 230d and the data pad 230e, respectively, and the fifth contact hole (not shown) exposes the second connection electrode 240b.

The source electrode 270a is connected to the source region 210c through a first contact hole (not shown), the drain electrode 270b is connected to the drain region 210d through a second contact hole , And contacts the first connection electrode 240a through a third contact hole (not shown). The data line DL is connected to the second connection electrode 240b formed on the data pad 230e through a fifth contact hole (not shown).

The bank 280 is formed of a material selected from a polymer material such as polyimide, polyacrylic, and polystyrene, and divides a plurality of pixel regions for displaying an image. And, although not shown, the bank 280 can be formed simultaneously with the spacers, and the spacers prevent physical damage due to external pressure.

The thin film transistor substrate of the present invention as described above forms a top gate structure to prevent light generated in the organic light emitting layer from being incident on the active layer, thereby improving the reliability and stability of the thin film transistor. In particular, the reflection layer formed under the pixel electrode can minimize the incidence of light generated in the organic light emitting layer into the thin film transistor, thereby improving the overall light emitting efficiency.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

5A to 5G are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the present invention.

First, as shown in FIG. 5A, a buffer layer 205 is formed on a substrate 200 by a plasma enhanced chemical vapor deposition (PECVD) method. An oxide layer such as IZO (Indium Zinc Oxide), GZO (Gallium Zinc Oxide), IGZO (Indium Gallium Zinc Oxide) or the like is deposited on the buffer layer 205 and patterned using the first mask to form a buffer layer 205. The first active layer 210a and the second active layer 210b are formed in the switching region on the substrate.

5B, the gate insulating layer 220 is formed on the buffer layer 205 including the first active layer 210a and the second active layer 210b. A metal such as aluminum (Al) or silver (Ag) having a high reflectivity is deposited on the entire surface of the gate insulating layer 220 and then patterned using a second mask to form a reflective layer 230.

5C, the first and second gate materials are sequentially stacked on the entire surface of the gate insulating layer 220 including the reflective layer 230, and then a mask process using a half mask (Half Tone Mask) The gate line GL, the gate electrode 230a, the storage upper electrode 230b, the pixel electrode 230c, the gate pad 230d and the data pad 230e are formed by patterning.

The storage upper electrode 230b, the pixel electrode 230c, the gate pad 230d and the data pad 230e are a single layer structure composed only of the first gate material and the gate line GL and the gate electrode 230a are formed of a first layer, , And a second gate material are stacked in this order.

The first gate material may be a conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), and the second gate material may include neodymium (Nd), copper (Cu) Aluminum (Al), tungsten (W), and molybdenum (Mo), or an alloy thereof.

The pixel electrode 230c is formed to cover the entire surface of the reflective layer 230 and further includes a first connection electrode 240a on a portion of the pixel electrode 230c which does not correspond to the reflective layer 230. [ The first connection electrode 240a is for improving contact characteristics between the drain electrode and the pixel electrode 230c, which will be described later.

A second connection electrode 240b for improving contact characteristics between the data pad 230e and the data line DL is formed on a part of the data pad 230e. In this case, the first and second connection electrodes 240a and 240b may be formed of a second gate material.

5D, the source and drain regions 210c and 210d are formed by doping both sides of the first active layer 210a not corresponding to the gate electrode 230a by using a plasma such as H ₂ , He, or N ₂ O . At the same time, the storage upper electrode 230b is used to form the storage lower electrode 210e by doping the second active layer 210b. Thus, a storage capacitor C including a storage lower electrode 210e, a gate insulating film 220, and a storage upper electrode 230b is formed. At this time, the above-described H ₂ , He, and N ₂ O have a very small atomic size and can permeate through the storage upper electrode 230b and penetrate into the second active layer 210b.

5E, the gate line GL, the gate electrode 230a, the storage upper electrode 230b, the pixel electrode 230c, the gate pad 230d, the data pad 230e, and the first and second connection electrodes A planarization layer 250 and a protection layer 260 are sequentially formed on the entire surface of the gate insulation layer 220 including the gate electrodes 240a and 240b. Then, the planarization layer 250 and the protective layer 260 are selectively removed using a fourth mask to form the first to sixth contact holes 250a to 250f.

The first and second contact holes 250a and 250b expose the source and drain regions 210c and 210d respectively and the third contact hole 250c exposes the first connection electrode 240a. The fourth and sixth contact holes 250d and 250f expose the gate pad 230d and the data pad 230e respectively and the fifth contact hole 250e exposes the second connection electrode 240b.

5f, a data material is deposited on the entire surface of the passivation layer 260 including the first to sixth contact holes and patterned using a fifth mask to form source and drain electrodes 270a and 270b and a data line DL. The data material is preferably selected from the group consisting of neodymium (Nd), copper (Cu), aluminum (Al), tungsten (W), and molybdenum (Mo)

The source electrode 270a is connected to the source region 210c through the first contact hole 250a. The drain electrode 270b is connected to the drain region 210d via the second contact hole 250b and contacts the first connection electrode 240a through the third contact hole 250c. The data line DL is connected to the second connection electrode 240b formed on the data pad 230e through the fifth contact hole 250e.

5G, a polymer material is formed on the protective layer 260 including the source and drain electrodes 270a and 270b and the data line DL and selectively removed using a sixth mask to form a pixel electrode (Bank) 280 having openings for exposing a part of the banks 230c.

As described above, according to the present invention, since the thin film transistor substrate is formed using six masks, the manufacturing cost can be reduced, and the yield and productivity can be improved. Particularly, reduction in the number of masks makes it possible to omit the photolithography process, the etching process, and the cleaning process for the exposure and development required for each mask in the process, and the yield can be improved by reducing 10 steps.

Further, a thin film transistor of a top gate structure is formed to prevent light generated in the organic light emitting layer from being incident on the active layer, thereby improving the reliability and stability of the thin film transistor.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

200: substrate 205: buffer layer
210a: first active layer 210b: second active layer
210c: source region 210d: drain region
210e: storage lower electrode 220: gate insulating film
230: reflective layer 230a: gate electrode
230b: storage upper electrode 230c: pixel electrode
230d: gate pad 230e: data pad
240a: first connection electrode 240b: second connection electrode
250: planarization film 250a: first contact hole
250b: second contact hole 250c: third contact hole
250d: Fourth contact hole 250e: Fifth contact hole
250f: sixth contact hole 260: protective film
270a: source electrode 270b: drain electrode
280: Bank

Claims (11)

Board;
A first active layer formed on the substrate, the first active layer including a source region and a drain region;
A gate insulating film formed on the entire surface of the substrate including the first active layer;
A reflective layer formed on the gate insulating layer;
A gate line and a gate electrode formed on the same layer as the reflective layer and having a double layer structure in which first and second gate materials are sequentially stacked;
A pixel electrode formed to cover the entire surface of the reflective layer and formed of only the first gate material;
A first connection electrode formed on a portion of the pixel electrode that does not correspond to the reflective layer;
A planarization layer and a protection layer sequentially formed on the entire surface of the gate insulation layer including the first connection electrode;
First, second and third contact holes formed by selectively removing the planarization layer and the protection layer and exposing a part of the source region, the drain region and the first connection electrode, respectively;
A data line formed on the protective film, a source electrode connected to the source region through the first contact hole, and a drain electrode connected to the drain region through the second contact hole, A drain electrode connected to the drain electrode; And
And a bank formed on the protective film including the source electrode and the drain electrode and having an opening exposing a part of the pixel electrode. The method according to claim 1,
Wherein the first gate material is a selected one of transparent conductive materials such as ITO, IZO, and ITZO. The method according to claim 1,
And a gate pad and a data pad formed on the same layer as the pixel electrode and formed of the first gate material. The method of claim 3,
A second connection electrode is further formed on a part of the data pad and the data line and the data pad are connected through the second connection electrode. Forming a first active layer on the substrate using a first mask;
Forming a gate insulating film on the entire surface of the substrate including the first active layer;
Forming a reflective layer on the gate insulating layer using a second mask;
A gate electrode and a gate electrode of a double layer structure in which first and second gate materials are sequentially stacked on the same layer as the reflective layer by using a third mask and a gate electrode and a gate electrode which are formed only of the first gate material Forming a pixel electrode having a single layer structure and forming a first connecting electrode on a partial region of the pixel electrode not corresponding to the reflective layer;
Doping the first active layer on both sides of the gate electrode to form a source region and a drain region;
Forming a planarization layer and a passivation layer on the entire surface of the gate insulation layer including the first connection electrode;
Forming a first, a second, and a third contact holes exposing a portion of the source region, the drain region, and the first connection electrode, respectively, by selectively removing the planarization layer and the protection layer using a fourth mask;
A data line is formed on the protective film using a fifth mask, a source electrode connected to the source region through the first contact hole, and a drain electrode connected to the drain region through the second contact hole, Forming a drain electrode connected to the first connection electrode through the third contact hole; And
And forming a bank formed on the protective film including the source electrode and the drain electrode using a sixth mask and having an opening exposing a part of the pixel electrode. 6. The method of claim 5,
Wherein the third mask is a halftone mask. 6. The method of claim 5,
Wherein the forming of the first active layer further comprises forming a second active layer in the same layer as the first active layer. 8. The method of claim 7,
Forming a storage upper electrode on the same layer as the pixel electrode and doping the second active layer using the storage upper electrode to form a storage lower electrode; 6. The method of claim 5,
And forming a gate pad and a data pad with the first gate material in the same layer as the pixel electrode. 10. The method of claim 9,
Further comprising forming a second connection electrode on a portion of the data pad to connect the data pad and the data line. 6. The method of claim 5,
Wherein the forming of the source region and the drain region uses a plasma doping method.

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