KR101604255B1 - Component manufacturing method and component - Google Patents

Component manufacturing method and component Download PDF

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Publication number
KR101604255B1
KR101604255B1 KR1020137029433A KR20137029433A KR101604255B1 KR 101604255 B1 KR101604255 B1 KR 101604255B1 KR 1020137029433 A KR1020137029433 A KR 1020137029433A KR 20137029433 A KR20137029433 A KR 20137029433A KR 101604255 B1 KR101604255 B1 KR 101604255B1
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South Korea
Prior art keywords
alloy film
substrate
alloy
film
component
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KR1020137029433A
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Korean (ko)
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KR20130136582A (en
Inventor
유 나카무타
마사히로 마츠모토
다카유키 이나가키
다이스케 히라마츠
노리아키 다니
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가부시키가이샤 아루박
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Publication of KR20130136582A publication Critical patent/KR20130136582A/en
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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Abstract

이 부품의 제조 방법은, 한쪽 면이 니켈로 이루어지는 기판을 이용하고, 상기 한쪽 면 상에 주석을 주성분으로 하는 합금막을 스퍼터법에 의해 형성하는 공정 A1과, 상기 합금막 상에 적어도 상기 합금막과의 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는 공정 A3과, 상기 기판과 상기 합금막 사이 및 상기 합금막과 상기 부품 사이를 각각 접합하기 위해 열처리를 실시하는 공정 A4를 적어도 차례대로 구비하는 부품의 제조 방법으로서, 상기 공정 A1에서 감압 분위기로 한 공간 내에 주석을 주성분으로 하는 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치하고, 상기 기판의 상기 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가한다.The manufacturing method of this component includes a step A1 of using a substrate made of nickel on one side and an alloy film having tin as a main component on the one side by a sputtering method, A step A3 of placing a part composed of any one of copper and nickel-coated aluminum as a contact part of the alloy film and step A3 of performing a heat treatment to bond the substrate and the alloy film, Wherein a cathode electrode having an alloy target containing tin as a main component is disposed in a space defined by the reduced pressure atmosphere in the step A1 and an anode electrode provided with the substrate are arranged so as to face each other, A DC voltage is applied to the cathode electrode.

Description

부품의 제조 방법 및 부품{Component manufacturing method and component}[0001] Component manufacturing method and component [0002]

본 발명은 부품의 제조 방법 및 부품에 관한 것이다. 보다 상세하게는, 본 발명은 기계적 특성, 전기적 특성을 확보하면서 땜납층의 박막화에 의해 저비용화 및 박형화도 도모하는 것이 가능한 부품의 제조 방법 및 부품에 관한 것이다.The present invention relates to a method of manufacturing a component and parts thereof. More particularly, the present invention relates to a component manufacturing method and parts capable of achieving a reduction in cost and thickness by making the solder layer thinner while ensuring mechanical characteristics and electrical characteristics.

본 출원은 2011년 08월 16일에 일본 출원된 특허 출원 2011-177893호에 기초하여 우선권을 주장하고, 그 내용을 여기에 원용한다.This application claims priority based on Japanese Patent Application No. 2011-177893 filed on August 16, 2011, the contents of which are incorporated herein by reference.

반도체 디바이스 등의 실장에는 Sn-Pb(주석-납) 합금이나 Sn-Au(주석-금) 합금 등의 땜납 재료가 이용되고 있다. 특히, Sn계 땜납은 알루미늄 등의 전극층 중에 주석 성분의 확산이 현저하여 땜납 접합부의 신뢰성에 큰 영향을 준다. 이 때문에, Sn계 땜납을 이용할 때에는 하지의 전극층에 대해 땜납층을 직접 형성하지 않고, 주석 성분의 확산을 방지하기 위한 배리어층, 접합 강도를 높이기 위한 밀착층을 개재하여 땜납층을 형성하도록 하고 있다(예를 들면, 특허문헌 1 참조).Solder materials such as Sn-Pb (tin-lead) alloys and Sn-Au (tin-gold) alloys are used for mounting semiconductor devices and the like. Especially, the Sn-based solder has a significant influence on the reliability of the solder joint portion due to the remarkable diffusion of tin components in the electrode layer such as aluminum. For this reason, when a Sn-based solder is used, a solder layer is formed directly on the electrode layer of the base through a barrier layer for preventing the diffusion of the tin component and an adhesion layer for increasing the bonding strength (See, for example, Patent Document 1).

도 10a~도 10f는 종래 부품의 제조 방법을 모식적으로 도시한 공정 단면도이다. 종래 부품의 제조 방법은 하기의 순서 10a부터 순서 10f의 순으로 진행된다.10A to 10F are process sectional views schematically showing a conventional component manufacturing method. The conventional method of manufacturing the parts proceeds in the order of the following steps 10a to 10f.

(순서 10a)(Step 10a)

도 10a에 도시된 바와 같이, 기판(100) 상에 하지막(101)으로서 Au막(밀착층), Ni막(배리어층), Ti막, Al막을 차례대로 스퍼터법에 의해 적층 형성한다.An Au film (adhesion layer), an Ni film (barrier layer), a Ti film, and an Al film are sequentially formed as a base film 101 on the substrate 100 by sputtering, as shown in Fig. 10A.

(순서 10b)(Step 10b)

도 10b에 도시된 바와 같이, 후공정에서 부품을 마운트하는 영역에 해당하는 부분에 관통공(102a)을 구비한 테이프 형상의 레지스트(102)를 상기 하지막(101) 상에 마련한다.As shown in Fig. 10B, a tape-shaped resist 102 having a through hole 102a is provided on the base film 101 at a portion corresponding to a region for mounting a component in a later process.

(순서 10c)(Step 10c)

도 10c에 도시된 바와 같이, 상기 레지스트(102)의 관통공(102a)을 통과하여 보이는 상기 하지막(101) 상에 적어도 땜납 페이스트(103)를 도포한다.The solder paste 103 is coated on the underlying film 101 as seen through the through hole 102a of the resist 102 as shown in FIG. 10C.

(순서 10d)(Step 10d)

도 10d에 도시된 바와 같이, 상기 레지스트의 관통공(102a)을 통과하여 보이는 상기 하지막(101) 상에 땜납 페이스트(103)를 개재하여 부품(104)을 올려놓는다.The part 104 is placed on the base film 101 passing through the through hole 102a of the resist through the solder paste 103 as shown in FIG.

(순서 10e)(Step 10e)

도 10e에 도시된 바와 같이, 열처리를 실시하여 상기 기판(100)과 상기 하지막(101) 사이, 상기 하지막(101)과 땜납 페이스트(103) 사이 및 상기 땜납 페이스트(103)와 상기 부품(104) 사이를 각각 접합한다.The solder paste 103 and the parts (not shown) are subjected to a heat treatment as shown in FIG. 10E so as to heat the substrate 100 and the base film 101, between the base film 101 and the solder paste 103, 104, respectively.

(순서 10f)(Step 10f)

마지막으로, 도 10f에 도시된 바와 같이, 상기 레지스트(102)를 제거한다.Finally, as shown in Fig. 10F, the resist 102 is removed.

그러나, 하지막의 재료로서 이용되는 금(Au)은 고가로서 비용 증가로 이어진다.However, gold (Au) used as a material of the underlying film is expensive and leads to an increase in cost.

또, 부품이 기판 상에 실장되어 이루어지는 실장품을 이용한 패키지에서는, 패키지 전체의 소형화 요구도 강해지고 실장품 자체의 박형화 요구도 심해지고 있다.In addition, in a package using a package in which components are mounted on a substrate, a demand for miniaturization of the package as a whole also becomes strong, and a demand for thinning of the package itself also becomes severe.

종래와 같이 땜납 페이스트를 도포함으로써 땜납층을 형성하면, 예를 들면 50㎛로 땜납층의 두께가 두꺼워진다. 땜납층을 얇게 하면 기계적 특성, 전기적 특성이 저하되는 문제가 있고, 실장품 더욱이 패키지의 박형화의 방해가 되었다.When the solder layer is formed by applying the solder paste as in the conventional case, for example, the thickness of the solder layer becomes 50 占 퐉. If the solder layer is made thinner, there is a problem that the mechanical properties and the electrical characteristics are deteriorated, and the package is further prevented from being thinned.

특허문헌 1: 일본특허공개 2006-269458호 공보Patent Document 1: JP-A-2006-269458

본 발명은 이러한 종래의 실정을 감안하여 고안된 것으로, 종래와 동등한 기계적 특성, 전기적 특성을 확보하면서 땜납층을 박막화하는 것이 가능하고, 저비용화, 박형화를 실현 가능한 부품의 제조 방법 및 부품을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been devised in view of such conventional circumstances, and it is an object of the present invention to provide a method and a component for a component which can reduce the thickness of the solder layer while ensuring mechanical characteristics and electrical characteristics equivalent to those of the prior art, The purpose.

(1) 본 발명의 제1 태양에 관한 부품의 제조 방법은, 한쪽 면이 니켈로 이루어지는 기판을 이용하고, 상기 한쪽 면 상에 주석을 주성분으로 하는 합금막을 스퍼터법에 의해 형성하는 공정 A1과, 상기 합금막 상에 적어도 상기 합금막과의 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는 공정 A3와, 상기 기판과 상기 합금막 사이 및 상기 합금막과 상기 부품 사이를 각각 접합하기 위해 열처리를 실시하는 공정 A4를 적어도 차례대로 구비하는 부품의 제조 방법으로서, 상기 공정 A1에서 감압 분위기로 한 공간 내에 주석을 주성분으로 하는 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치하고, 상기 기판의 상기 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가한다.(1) A method of manufacturing a component according to a first aspect of the present invention includes the steps of: A1) forming a layer of an alloy film containing tin as a main component on one surface of a substrate made of nickel on one surface thereof by sputtering; A step A3 of placing a part made of copper or nickel-coated aluminum on the alloy film at least at a portion where the alloy film is in contact with the alloy film, a step A3 between the substrate and the alloy film, A step of performing a heat treatment to form a tin-based alloy target, wherein the step (A1) includes a step of forming a space between the cathode electrode and the anode electrode, And a DC voltage is applied to the cathode electrode when the alloy film is formed on the one surface of the substrate .

(2) 상기 (1)에 기재된 제조 방법은, 상기 공정 A1과 상기 공정 A3의 사이에, 후공정에서 상기 부품이 마운트되는 영역에 해당하는 부분에 관통공이 형성된 테이프 형상의 레지스트를 상기 합금막 상에 마련하는 공정 A2를 더 구비하고 있어도 된다.(2) In the manufacturing method described in (1), between the step A1 and the step A3, a tape-like resist having a through hole formed in a portion corresponding to a region where the component is mounted in a later step is formed on the alloy film May be further provided.

(3) 상기 (2)에 기재된 제조 방법은, 상기 공정 A2와 상기 공정 A3의 사이에, 상기 레지스트의 상기 관통공을 통과하여 보이는 상기 합금막 상에 플럭스를 도포하여 상기 합금막의 표층을 이루는 산화막을 제거하는 공정 A6을 더 구비하고 있어도 된다.(3) In the manufacturing method described in (2), between the step A2 and the step A3, a flux is applied on the alloy film which is seen through the through-hole of the resist to form an oxide film The step A6 may be further provided.

(4) 상기 (2) 또는 (3)에 기재된 제조 방법은, 상기 레지스트를 제거하는 공정 A5를 더 구비하고 있어도 된다.(4) The manufacturing method described in (2) or (3) above may further comprise a step A5 for removing the resist.

(5) 본 발명의 제2 태양에 관한 부품의 제조 방법은, 한쪽 면이 니켈로 이루어지는 기판을 이용하고, 상기 한쪽 면 상에 주석을 주성분으로 하는 합금막을 스퍼터법에 의해 형성하는 공정 B1과, 상기 합금막 상에 적어도 땜납 페이스트를 도포하는 공정 B3과, 상기 합금막 상에 상기 땜납 페이스트를 개재하여 적어도 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는 공정 B4와, 상기 기판과 상기 합금막 사이, 상기 땜납 페이스트와 상기 합금막 사이 및 상기 땜납 페이스트와 상기 부품 사이를 각각 접합하기 위해 열처리를 실시하는 공정 B5를 적어도 차례대로 구비하는 부품의 제조 방법으로서, 상기 공정 B1에서 감압 분위기로 한 공간 내에 주석을 주성분으로 하는 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치하고, 상기 기판의 상기 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가한다.(5) A method of manufacturing a component according to a second aspect of the present invention is a method of manufacturing a component, comprising: a step B1 in which a substrate made of nickel is used on one side and an alloy film having tin as a main component is formed on the one side by sputtering; A step B3 of applying at least solder paste on the alloy film, a step B4 of placing a component made of any one of copper and nickel-coated aluminum on the alloy film with the solder paste interposed therebetween, And a step B5 for performing a heat treatment to bond the solder paste and the alloy part to each other, and between the solder paste and the alloy film, and to bond the solder paste and the part to each other. In the step B1, A cathode electrode provided with an alloy target having tin as a main component in a space defined by an atmosphere, And a DC voltage is applied to the cathode electrode when the alloy film is formed on the one surface of the substrate.

(6) 상기 (5)에 기재된 제조 방법은, 상기 공정 B1과 상기 공정 B3의 사이에, 후공정에서 상기 부품이 마운트되는 영역에 해당하는 부분에 관통공이 형성된 테이프 형상의 레지스트를 상기 합금막 상에 마련하는 공정 B2를 더 구비하고 있어도 된다.(6) In the manufacturing method described in (5), between the step B1 and the step B3, a tape-shaped resist in which a through hole is formed in a portion corresponding to a region where the component is mounted in a later step is formed on the alloy film May be further provided.

(7) 상기 (5) 또는 (6)에 기재된 제조 방법은, 상기 공정 B3에서 상기 땜납 페이스트가 플럭스를 함유해도 되는 플럭스가 들어간 상기 땜납 페이스트를 이용해도 된다.(7) In the manufacturing method described in (5) or (6), the solder paste in which the flux, which may contain the flux in the solder paste in the step B3, may be used.

(8) 상기 (6) 또는 (7)에 기재된 제조 방법은, 상기 레지스트를 제거하는 공정 B6을 더 구비하고 있어도 된다.(8) The manufacturing method described in (6) or (7) above may further comprise a step B6 for removing the resist.

(9) 본 발명의 제3 태양에 관한 부품은, 한쪽 면이 니켈로 이루어지는 기판에 상기 한쪽 면 상에 주석을 주성분으로 하는 합금막을 스퍼터법에 의해 형성하고, 상기 합금막 상에 적어도 상기 합금막과의 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는다.(9) In the component according to the third aspect of the present invention, an alloy film having tin as a main component is formed on one surface of the substrate made of nickel on the one surface by sputtering, and at least the alloy film And a part made of copper and nickel-coated aluminum.

상기 (1)부터 (9)에 기재된 부품의 제조 방법 및 부품에 따르면, 주석을 주성분으로 하는 합금막을 스퍼터법에 의해 형성할 때에, 감압 분위기로 한 공간 내에 주석을 주성분으로 하는 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치한다. 그리고, 상기 기판의 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가함으로써, 박막화되어도 종래와 동등한 기계적 특성, 전기적 특성을 확보한 합금막을 성막하는 것이 가능하다. 이에 의해 상기 부품의 제조 방법 및 부품에 따르면, 종래와 동등한 기계적 특성, 전기적 특성을 확보하면서 땜납층을 박막화하는 것이 가능하고, 저비용화, 박형화를 실현할 수 있는 부품의 제조 방법 및 부품을 제공할 수 있다.According to the manufacturing method and parts of the parts described in (1) to (9) above, when an alloy film containing tin as a main component is formed by the sputtering method, a cathode having a tin- An electrode and an anode electrode provided with the substrate are disposed to face each other. By applying a DC voltage to the cathode electrode when forming the alloy film on one side of the substrate, it is possible to form an alloy film having mechanical characteristics and electrical characteristics equivalent to those of the conventional one even when the film thickness is reduced. Thus, according to the manufacturing method and parts of the above-described parts, it is possible to provide a manufacturing method and a part of a component capable of reducing the thickness of the solder layer while ensuring mechanical characteristics and electrical characteristics equivalent to those of the prior art, have.

도 1a는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1a를 설명하는 공정 단면도이다.
도 1b는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1b를 설명하는 공정 단면도이다.
도 1c는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1c를 설명하는 공정 단면도이다.
도 1d는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1d를 설명하는 공정 단면도이다.
도 1e는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1e를 설명하는 공정 단면도이다.
도 1f는 본 발명의 부품의 제조 방법(제1 실시형태)의 순서 1f를 설명하는 공정 단면도이다.
도 2는 본 발명에서 이용되는 스퍼터 장치의 구성을 도시한 모식 평면도이다.
도 3은 도 2에 도시된 스퍼터 장치에 있어서, 스퍼터실 내에 배치되어 있는 전극에 DC 펄스 전압을 인가하는 DC 펄스 전원 유닛의 구성을 도시한 모식 블록도이다.
도 4a는 도 3의 DC 펄스 전원 유닛의 출력 전압 파형을 설명하는 타임차트이다(DC 펄스 전압).
도 4b는 도 3의 DC 펄스 전원 유닛의 출력 전압 파형을 설명하는 타임차트이다(DC 전압).
도 5는 기판, 합금막 및 부품 부분을 확대하여 모식적으로 도시한 도면이다.
도 6a는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2a를 설명하는 공정 단면도이다.
도 6b는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2b를 설명하는 공정 단면도이다.
도 6c는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2c를 설명하는 공정 단면도이다.
도 6d는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2d를 설명하는 공정 단면도이다.
도 6e는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2e를 설명하는 공정 단면도이다.
도 6f는 본 발명의 부품의 제조 방법(제2 실시형태)의 순서 2f를 설명하는 공정 단면도이다.
도 7은 리플로우 프로파일을 도시한 도면이다.
도 8은 땜납 합금막과 Ni기판의 접합 계면에서의 SEM 사진을 도시한 도면이다.
도 9는 땜납 합금막과 Cu부품의 접합 계면에서의 SEM 사진을 도시한 도면이다.
도 10a는 종래 부품의 제조 방법의 순서 10a를 설명하는 공정 단면도이다.
도 10b는 종래 부품의 제조 방법의 순서 10b를 설명하는 공정 단면도이다.
도 10c는 종래 부품의 제조 방법의 순서 10c를 설명하는 공정 단면도이다.
도 10d는 종래 부품의 제조 방법의 순서 10d를 설명하는 공정 단면도이다.
도 10e는 종래 부품의 제조 방법의 순서 10e를 설명하는 공정 단면도이다.
도 10f는 종래 부품의 제조 방법의 순서 10f를 설명하는 공정 단면도이다.1A is a process sectional view for explaining a step 1a of a method of manufacturing a part (first embodiment) of the present invention.
1B is a process sectional view for explaining sequence 1b of a method of manufacturing a part (first embodiment) of the present invention.
1C is a process sectional view for explaining sequence 1c of the method for manufacturing a part (first embodiment) of the present invention.
Fig. 1D is a process sectional view for explaining step 1d of the method for manufacturing a part (first embodiment) of the present invention.
1E is a process sectional view for explaining sequence 1e of the method for manufacturing a part (first embodiment) of the present invention.
Fig. 1F is a process sectional view for explaining step 1f of the method for manufacturing a part (first embodiment) of the present invention.
2 is a schematic plan view showing a configuration of a sputtering apparatus used in the present invention.
3 is a schematic block diagram showing a configuration of a DC pulse power source unit for applying a DC pulse voltage to electrodes arranged in a sputter chamber in the sputtering apparatus shown in Fig.
4A is a time chart (DC pulse voltage) for explaining the output voltage waveform of the DC pulse power supply unit of FIG.
4B is a time chart illustrating the output voltage waveform of the DC pulse power supply unit of FIG. 3 (DC voltage).
5 is a diagram schematically showing an enlarged view of a substrate, an alloy film and a component part.
6A is a process sectional view for explaining step 2a of the method for manufacturing a part (second embodiment) of the present invention.
Fig. 6B is a process sectional view for explaining step 2b of the method for manufacturing a part (second embodiment) of the present invention.
6C is a process sectional view for explaining step 2c of the method for manufacturing a part (second embodiment) of the present invention.
FIG. 6D is a process sectional view for explaining the procedure 2d of the method for manufacturing a part (second embodiment) of the present invention. FIG.
6E is a process sectional view for explaining step 2e of the method for manufacturing a part (second embodiment) of the present invention.
Fig. 6F is a process sectional view for explaining step 2f of the method for manufacturing a part (second embodiment) of the present invention.
7 is a view showing a reflow profile.
8 is a SEM photograph showing a bonding interface between the solder alloy film and the Ni substrate.
9 is a SEM photograph showing a bonding interface between the solder alloy film and the Cu part.
10A is a process sectional view for explaining the procedure 10a of the conventional component manufacturing method.
10B is a process sectional view for explaining the procedure 10b of the conventional component manufacturing method.
10C is a process sectional view for explaining the procedure 10c of the conventional component manufacturing method.
10D is a process sectional view for explaining the procedure 10d of the conventional component manufacturing method.
10E is a process sectional view for explaining the procedure 10e of the conventional component manufacturing method.
10F is a process sectional view for explaining the procedure 10f of the conventional component manufacturing method.

이하, 본 발명에 관한 부품의 제조 방법의 일 실시형태를 도면에 기초하여 설명한다.DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, one embodiment of a method of manufacturing a component according to the present invention will be described with reference to the drawings.

후술하는 각 실시형태에서는, 주석(Sn)을 주성분으로 하는 합금 타겟으로서 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금 타겟을 이용하고, 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금막을 형성한 예에 대해 상술한다. 그러나, 본 발명은 반드시 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금 타겟에 한정되는 것은 아니다. 본 발명에 적합한 주석(Sn)을 주성분으로 하는 합금 타겟으로서는, 예를 들면 Sn을 주성분으로서 은(Ag), 구리(Cu), 아연(Zn), 비스무스(Bi), 인듐(In), 안티몬(Sb), 니켈(Ni) 등을 포함하는 것을 들 수 있다.In each embodiment described later, an alloy target containing silver (Ag), tin (Sn) and copper (Cu) is used as an alloy target whose main component is tin (Sn) And an alloy film containing copper (Cu) are formed. However, the present invention is not limited to an alloy target containing silver (Ag), tin (Sn) and copper (Cu). As an alloy target containing tin (Sn) as a main component suitable for the present invention, for example, silver (Ag), copper (Cu), zinc (Zn), bismuth (Bi), indium (In) Sb), nickel (Ni), and the like.

(제1 실시형태)(First Embodiment)

도 1a~도 1f는 본 발명에 의한 부품의 제조 방법을 설명하는 공정 단면도이다.1A to 1F are process sectional views illustrating a method of manufacturing a component according to the present invention.

(순서 1a)(Step 1a)

우선, 도 1a에 도시된 바와 같이, 한쪽 면(10a)이 니켈(Ni)로 이루어지는 기판(10)을 이용하고, 한쪽 면(10a) 상에 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금막(11)을 스퍼터법에 의해 형성한다(공정 A1).First, as shown in Fig. 1A, a substrate 10 made of nickel (Ni) is used as one surface 10a, silver (Ag), tin (Sn) and copper ) Is formed by a sputtering method (step A1).

기판(10)은 한쪽 면이 니켈로 이루어지면 좋고, 예를 들면 실리콘(Si) 기판(10)의 일면에 니켈(Ni) 막이 형성된 것이 적합하게 이용된다. 이하에서는 이 구성으로 한 것을 Ni막 부착 기판(10)이라고도 한다.The substrate 10 may be made of nickel on one side. For example, a nickel (Ni) film formed on one surface of a silicon (Si) substrate 10 is suitably used. Hereinafter, this structure is also referred to as a substrate 10 with an Ni film.

특히 본 실시형태는, 감압 분위기로 한 공간 내에 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금 타겟을 마련한 캐소드 전극(60)(도 3 참조)과 상기 기판(10)을 마련한 애노드 전극(70)(도 3 참조)을 대향하여 배치하고, 상기 기판(10)의 한쪽 면 상에 상기 합금막(11)을 형성할 때에 상기 캐소드 전극(60)에 DC 펄스 전압을 인가한다.Particularly, in this embodiment, a cathode electrode 60 (see FIG. 3) provided with an alloy target containing silver (Ag), tin (Sn) and copper (Cu) A DC pulse voltage is applied to the cathode electrode 60 when the alloy film 11 is formed on one side of the substrate 10 .

여기서, 도 2는 본 실시형태에서 이용되는 스퍼터 장치(110)의 구성을 도시한 모식 평면도이고, 기판(10) 상에 땜납 합금막(11)을 적층 형성하기 위한 것이다.2 is a schematic plan view showing a configuration of the sputtering apparatus 110 used in the present embodiment and is for forming a laminated layer of the solder alloy film 11 on the substrate 10. [

도 2에서, 스퍼터 장치(110)는 기판(웨이퍼)(10)의 반송실(T0)과, 스퍼터 처리를 하는 스퍼터실(S1, S2)과, 로드 로크실(L/UL)과, 기판(10)의 이동탑재기(T1)를 구비하고 있다.2, the sputtering apparatus 110 includes a transfer chamber T0 of a substrate (wafer) 10, sputtering chambers S1 and S2 for sputtering processing, a load lock chamber L / UL, 10 of a mobile unit T1.

스퍼터 장치(110)에 있어서, 스퍼터실(S1)은 Si기판(10)의 일면에 Ni막을 형성하는 성막실이고, 스퍼터실(S2)은 땜납 합금막(11)을 형성하는 성막실이다. 2개의 스퍼터실(S1, S2)은 후술하는 밸브 기구를 개재하여 반송실(T0)과 연통하도록 구성되어 있으므로, 스퍼터실(S1)에서 Ni막이 형성된 실리콘(Si) 기판(10)을 감압 분위기 중을 통과하여 땜납 합금막(11)을 형성하는 스퍼터실(S2)로 이동시키는 것이 가능하게 된다. 이에 의해, Ni막의 표면이 산화되는 일이 없으므로, Ni막 상에 땜납 합금막(11)을 형성하였을 때에 Ni막과 땜납 합금막(11)의 젖음성이 양호하게 유지된다. 즉, Ni막에 대한 땜납 합금막(11)의 젖음성을 양호하게 유지하기 위해서는 Ni막과 땜납막은 진공 중에서 일관적으로 성막하는 것이 바람직하다.In the sputtering apparatus 110, the sputtering chamber S1 is a deposition chamber for forming an Ni film on one surface of the Si substrate 10, and the sputtering chamber S2 is a deposition chamber for forming a solder alloy film 11. [ Since the two sputtering chambers S1 and S2 are configured to communicate with the transfer chamber T0 through a valve mechanism to be described later, the silicon (Si) substrate 10 in which the Ni film is formed in the sputtering chamber S1, To the sputtering chamber S2 in which the solder alloy film 11 is formed. Thus, since the surface of the Ni film is not oxidized, the wettability of the Ni film and the solder alloy film 11 is favorably maintained when the solder alloy film 11 is formed on the Ni film. That is, in order to maintain a good wettability of the solder alloy film 11 with respect to the Ni film, it is preferable to form the Ni film and the solder film consistently in vacuum.

또, 스퍼터 장치(110)로서는, 예를 들면 마그네트론 스퍼터 장치가 적합하게 이용된다.As the sputtering apparatus 110, for example, a magnetron sputtering apparatus is suitably used.

도 2의 스퍼터 장치(110)에 있어서, 반송실(T0)은 핸들러(H0)를 갖고 있다. 핸들러(H0)는 기판(10)을 보유지지한 채로 이동하여 스퍼터실 간 혹은 스퍼터실(S1, S2)과 로드 로크실(L/UL)의 사이에서 기판(10)을 반송한다. 또한, 이동탑재기(T1)는 핸들러(H1)와 기판(웨이퍼)(10)의 카세트(C1, C2)를 갖고 있다. 핸들러(H1)는 기판(10)을 보유지지한 채로 이동하여 카세트(C1)에 세트된 기판(10)을 로드 로크실(L/UL)로 반입하고, 스퍼터 처리된 기판(10)을 로드 로크실(L/UL)로부터 반출하여 카세트(C1)로 되돌린다.In the sputtering apparatus 110 of FIG. 2, the transport chamber T0 has a handler H0. The handler H0 moves while holding the substrate 10 and transports the substrate 10 between the sputter chambers or between the sputter chambers S1 and S2 and the load lock chambers L and UL. The mobile unit T1 has a handler H1 and cassettes C1 and C2 of a substrate (wafer) The handler H1 moves while holding the substrate 10 to carry the substrate 10 set in the cassette C1 to the load lock chamber L / UL, and the sputtered substrate 10 is loaded into the load lock chamber (L / UL) and returned to the cassette C1.

또, 스퍼터 장치(110)에서는, 반송실(T0)과 각 스퍼터실(S1, S2)의 사이, 반송실(T0)과 로드 로크실(L/UL)의 사이 및 로드 로크실(L/UL)과 이동탑재기(T1)의 사이에 각각 밸브 기구가 설치되어 있고, 실 간의 진공도·분위기를 차단할 수 있는 구성으로 되어 있다.In the sputtering apparatus 110, between the transfer chamber T0 and each of the sputter chambers S1 and S2, between the transfer chamber T0 and the load lock chamber L / UL, and between the load lock chamber L / UL ) And the mobile unit (T1), respectively, so that the degree of vacuum and atmosphere between the chambers can be cut off.

(스퍼터 장치(110)에서의 DC 펄스 스퍼터 및 정전 척에 의한 땜납 합금막(11)의 형성)(Formation of the solder alloy film 11 by the DC pulse sputtering and the electrostatic chuck in the sputtering apparatus 110)

이러한 스퍼터 장치(110)에 있어서, 스퍼터실(S2)에서는 전극에 DC전압(직류 전압)이 아니라 DC 펄스 전압을 인가하는 DC 펄스 스퍼터에 의해 합금막(11)을 미리 Ni막이 형성된 기판(10) 상에 형성한다. 또한, 스퍼터실(S2)에서는 기판(10)을 세트하는 정전 척에 온도 제어부가 설치되어 있고, 이 정전 척에 의해 기판(10)의 온도 상승을 억제하면서 합금막(11)을 형성한다. 정전 척에 설치된 온도 제어부는 기판(10)의 온도를 조정 제어 가능하고, 스퍼터 처리시에는 기판(10)을 냉각하여 소정의 온도로 유지한다.In this sputtering apparatus 110, in the sputtering chamber S2, the alloy film 11 is preliminarily deposited on the substrate 10 on which the Ni film is formed by means of DC pulse sputtering which applies a DC pulse voltage instead of a DC voltage (DC voltage) . In the sputtering chamber S2, a temperature control unit is provided on the electrostatic chuck for setting the substrate 10, and the alloy film 11 is formed by the electrostatic chuck while suppressing the temperature rise of the substrate 10. [ The temperature control unit provided on the electrostatic chuck can adjust and control the temperature of the substrate 10 and keeps the substrate 10 at a predetermined temperature during the sputtering process.

(DC 펄스 전원 유닛)(DC pulse power supply unit)

도 3은 스퍼터실(S3) 내에 배치되어 있는 전극에 DC 펄스 전압을 인가하는 DC 펄스 전원 유닛(50)의 구성을 도시한 모식 블록도이다. 도 3에서, DC 펄스 전원 유닛(50)은 DC전원(51), OFF 펄스 전원(52), 인가 전압 생성부(53), 제어부(54)를 구비하고 있다.3 is a schematic block diagram showing a configuration of a DC pulse power source unit 50 for applying a DC pulse voltage to electrodes disposed in the sputter chamber S3. 3, the DC pulse power source unit 50 includes a DC power source 51, an OFF pulse power source 52, an applied voltage generating unit 53, and a control unit 54. [

이 DC 펄스 전원 유닛(50)의 출력 전압은 스퍼터실(S3) 내의 캐소드 전극(60)에 인가된다. 또한, 스퍼터실(S3) 내의 애노드 전극(70)은 접지되어 있다. 따라서, 애노드 전극(70)의 전위(Ea)는 기준 전위(0전위)이고, 캐소드 전극(60)의 전위(Ek)는 DC 펄스 전원 유닛(50)의 출력 전위이다.The output voltage of the DC pulse power supply unit 50 is applied to the cathode electrode 60 in the sputter chamber S3. Further, the anode electrode 70 in the sputter chamber S3 is grounded. Therefore, the potential Ea of the anode electrode 70 is the reference potential (zero potential), and the potential Ek of the cathode electrode 60 is the output potential of the DC pulse power source unit 50. [

(DC 펄스)(DC pulse)

도 4a, 도 4b는 DC 펄스 전원 유닛(50)의 출력 전압 파형을 설명하는 타임차트이다. 도 4a는 DC 펄스 스퍼터 시에 전극에 인가하는 DC 펄스 전압이다. 도 4b는 DC 스퍼터 시에 전극에 인가하는 DC전압이다.4A and 4B are time charts illustrating the output voltage waveforms of the DC pulse power source unit 50. FIG. 4A is a DC pulse voltage to be applied to the electrode during the DC pulse sputtering. 4B is a DC voltage applied to the electrode during the DC sputtering.

도 4a에 도시된 바와 같이, DC 펄스 전원 유닛(50)에 의해 생성되는 DC 펄스의 주기는 t0이다. 이 주기(t0) 중에서 기간(t1)이 DC 펄스의 OFF 기간이고, 나머지 기간(t2)이 DC 펄스의 ON 기간이다. ON기간(t2)에서 캐소드 전위(Ek)는 음의 전위(Ek1)이다. 그러나, OFF 기간(t1)에서 캐소드 전위(Ek)는 양 또는 0의 OFF 펄스 전위(Ek0)(도 4a에서는 전위(Ek0)는 양전위)이다. 한편, 도 4b에 도시된 바와 같이, DC 펄스 전원 유닛(50)을 DC 전원(51)으로서 기능시킨 경우에는 캐소드 전위(Ek)는 음의 고정 전위(Ek2)가 된다.As shown in Fig. 4A, the period of the DC pulse generated by the DC pulse power source unit 50 is t0. In this period t0, the period t1 is the OFF period of the DC pulse and the remaining period t2 is the ON period of the DC pulse. In the ON period t2, the cathode potential Ek is a negative potential Ek1. However, in the OFF period t1, the cathode potential Ek is positive or zero OFF pulse potential Ek0 (potential Ek0 in Fig. 4A is positive potential). On the other hand, as shown in FIG. 4B, when the DC pulse power source unit 50 is made to function as the DC power source 51, the cathode potential Ek becomes the negative fixed potential Ek2.

도 3의 DC 펄스 전원 유닛(50)의 동작에 대해 설명한다. DC 전원(51)은 제어부(54)로부터 송신되는 파고치 제어 신호에 따라 음전위(Ek1)를 생성한다. OFF 펄스 전원(52)은, 제어부(54)로부터 송신되는 파고치 제어 신호에 따라 OFF 펄스 전위(양전위 또는 0(제로)전위)(Ek0)를 생성하고, 이들 전위(Ek1, Ek0)를 각각 인가 전압 생성부(53)에 출력한다. 또, 전위(Ek1, Ek0)의 값은 상기 파고치 제어 신호에 따라 가변 설정 가능하다.The operation of the DC pulse power source unit 50 of FIG. 3 will be described. The DC power supply 51 generates a negative potential Ek1 in accordance with the crest value control signal transmitted from the control unit 54. [ OFF pulse power supply 52 generates an OFF pulse electric potential (positive electric potential or zero electric potential) Ek0 in accordance with the crest value control signal transmitted from the control unit 54 and outputs these electric potential Ek1 Ek0 And outputs it to the applied voltage generating section 53. The values of the potentials Ek1 and Ek0 can be variably set according to the crest value control signal.

인가 전압 생성부(53)는, 제어부(54)로부터 송신되는 전환 제어 신호에 따라 ON기간(t2)에서 전위(Ek1)를, OFF 기간(t1)에서 전위(Ek0)를 전환하여 출력한다. 이에 의해, 캐소드 전극(60)에는 DC 펄스(Ek)(도 4a 참조)가 인가된다. 또, DC 펄스(Ek)의 OFF 듀티비(t1/t0)는 상기 전환 제어 신호에 따라 예를 들면 0%~50%의 사이에서 가변 설정 가능하다. 도 4a에서는 OFF 듀티비(t1/t0)를 20%로 설정하고 있다. 단, 이 OFF 듀티비(t1/t0)는 10%~30%의 범위 내로 설정하는 것이 바람직하다. 또한, DC 펄스(Ek)의 주파수(1/t0)도 상기 전환 제어 신호에 따라 예를 들면 50Hz~250Hz의 사이에서 가변 설정 가능하다.The applied voltage generating section 53 switches the potential Ek1 in the ON period t2 and the potential Ek0 in the OFF period t1 according to the switching control signal transmitted from the control section 54. [ As a result, a DC pulse Ek (see Fig. 4A) is applied to the cathode electrode 60. Fig. The OFF duty ratio t1 / t0 of the DC pulse Ek can be variably set between 0% and 50%, for example, in accordance with the switching control signal. In Fig. 4A, the OFF duty ratio t1 / t0 is set to 20%. However, it is preferable that the OFF duty ratio t1 / t0 is set within a range of 10% to 30%. Also, the frequency 1 / t0 of the DC pulse Ek can be variably set between, for example, 50 Hz to 250 Hz according to the switching control signal.

한편, DC 펄스 전원 유닛(50)을 DC 전원(51)으로서 사용할 때, 인가 전압 생성부(53)는 DC 전원(51)에서 생성된 전위(Ek2)(도 4b 참조)만을 계속하여 캐소드 인가 전위(Ek)로서 출력한다.On the other hand, when the DC pulse power supply unit 50 is used as the DC power supply 51, the applied voltage generating unit 53 continues to supply only the potential Ek2 (see FIG. 4B) generated by the DC power supply 51, (Ek).

(스퍼터 장치(110)에서의 Ni막 및 땜납 합금막(11)의 형성 순서)(The order of forming the Ni film and the solder alloy film 11 in the sputtering apparatus 110)

(기판(10)의 반입)(Bringing in the substrate 10)

우선, 실리콘(Si)으로 이루어지는 기판(웨이퍼)(10)을 이동탑재기(T1) 내의 카세트(C1)에 세트한다. 그리고, 로드 로크실(L/UL)을 벤트하여 이동탑재기(T1)와의 사이의 밸브 기구를 개방한 후, 상기 카세트(C1)에 세트한 기판(10)을 핸들러(H1)에 의해 카세트(C1)로부터 로드 로크실(L/UL) 내로 이송한다.First, a substrate (wafer) 10 made of silicon (Si) is set in the cassette C1 in the mobile unit T1. Subsequently, after the valve mechanism between the load lock chamber L / UL is opened to open the valve mechanism with the mobile unit T1, the substrate 10 set in the cassette C1 is moved by the handler H1 to the cassette C1 To the load lock chamber (L / UL).

다음에, 로드 로크실(L/UL)과 이동탑재기(T1) 사이의 밸브 기구를 닫고 로드 로크실(L/UL)을 10-3Pa대까지 진공 배기한다. 그리고, 로드 로크실(L/UL)과 반송실(T0) 사이의 밸브 기구를 열고 반송실(T0) 내의 핸들러(H0)에 의해 기판(10)을 반송실(T0) 내로 반입하고 로드 로크실(L/UL)과의 사이의 밸브 기구를 닫는다.Next, the valve mechanism between the load lock chamber (L / UL) and the mobile loader (T1) is closed and the load lock chamber (L / UL) is evacuated to 10 -3 Pa. Then the valve mechanism between the load lock chamber L / UL and the transfer chamber T0 is opened and the substrate 10 is carried into the transfer chamber T0 by the handler H0 in the transfer chamber T0, (L / UL) is closed.

(Ni막의 형성, 스퍼터실(S1))(Formation of Ni film, sputtering chamber S1)

다음에, 반송실(T0)과 스퍼터실(S1) 사이의 밸브 기구를 열고 핸들러(H0)에 의해 Ni기판(10)을 반송실(T0)로부터 스퍼터실(S1) 내로 반송한다. 그리고, 스퍼터실(S1)에서 Ni막을 형성한다. 스퍼터실(S1)의 성막 압력을 0.1Pa~1.0Pa로 하고 Ar 유량을 5sccm~50sccm으로 한 감압 분위기 중에서, Ni 타겟을 사용하여 DC 스퍼터법에 의해 예를 들면 막두께 0.2㎛~4.0㎛의 Ni막을 형성한다. 그리고, Ni막을 형성한 후, 반송실(T0)과의 사이의 밸브 기구를 열고 이면(피성막면)에 Ni가 형성된 Ni막 부착 기판(10)을 핸들러(H0)에 의해 스퍼터실(S1)로부터 반송실(T0)로 되돌리고 스퍼터실(S1)과의 사이의 밸브 기구를 닫는다.Next, the valve mechanism between the transport chamber T0 and the sputter chamber S1 is opened and the Ni substrate 10 is transported into the sputter chamber S1 from the transport chamber T0 by the handler H0. Then, a Ni film is formed in the sputter chamber S1. A Ni target having a film thickness of 0.2 탆 to 4.0 탆 is formed by a DC sputtering method using a Ni target in a reduced pressure atmosphere in which the film forming pressure of the sputter chamber S 1 is set to 0.1 Pa to 1.0 Pa and the Ar flow rate is set to 5 sccm to 50 sccm, Thereby forming a film. After the formation of the Ni film, the valve mechanism between the substrate and the transport chamber T0 is opened and the substrate 10 with the Ni film on which the Ni film is formed on the back surface (film formation surface) is transported to the sputter chamber S1 by the handler H0. Back to the transfer chamber T0 and closes the valve mechanism between the sputter chamber S1 and the sputter chamber S1.

(합금막(11)의 형성, 스퍼터실(S2))(Formation of the alloy film 11, sputtering chamber S2)

다음에, 반송실(T0)과 스퍼터실(S2) 사이의 밸브 기구를 열고 핸들러(H0)에 의해 Ni막 부착 기판(10)을 반송실(T0)로부터 스퍼터실(S2) 내로 반송한다. 그리고, 스퍼터실(S2)에서 Sn 및 Cu를 주성분으로서 Ag를 함유하는 합금막(11)을 성막한다. 스퍼터실(S2)의 성막 압력을 0.1Pa~1.0Pa로 하고 Ar 유량을 5sccm~50sccm으로 한 감압 분위기 중에서, Ag-Sn-Cu 합금의 땜납 타겟(Ag-Sn-Cu 합금 타겟)을 사용하여 DC 펄스 스퍼터(마그네트론 스퍼터)에 의해 예를 들면 막두께 2㎛~10㎛의 땜납 합금막(11)을 성막한다. 그리고, 성막 종료 후, 반송실(T0)과의 사이의 밸브 기구를 열고 이면(피성막면)에 합금막(11)이 형성된 Ni막 부착 기판(10)을 핸들러(H0)에 의해 스퍼터실(S2)로부터 반송실(T0)로 되돌리고 스퍼터실(S2)과의 사이의 밸브 기구를 닫는다.Next, the valve mechanism between the transport chamber T0 and the sputter chamber S2 is opened and the substrate 10 with the Ni film is transported into the sputter chamber S2 from the transport chamber T0 by the handler H0. Then, an alloy film 11 containing Ag and Sn as a main component is formed in the sputter chamber S2. (Ag-Sn-Cu alloy target) of Ag-Sn-Cu alloy in a reduced-pressure atmosphere in which the film forming pressure of the sputter chamber S2 is set to 0.1 Pa to 1.0 Pa and the Ar flow rate is set to 5 sccm to 50 sccm, A solder alloy film 11 having a thickness of, for example, 2 mu m to 10 mu m is formed by a pulse sputter (magnetron sputter). After the completion of the film formation, the valve mechanism between the transfer chamber T0 and the Ni film-deposited substrate 10 on which the alloy film 11 is formed is opened by the handler H0 to form the sputtering chamber S2 to the transport chamber T0 and closes the valve mechanism with respect to the sputter chamber S2.

상기 합금막(11)을 성막하는 DC 펄스 스퍼터에서는, 예를 들면 DC 펄스의 OFF 듀티(t1/t0)(도 4a 참조)를 20%로 설정하고, DC 펄스의 주파수(1/t0)를 250kHz로 설정한다. 또한, 정전 척의 온도 제어부에 의해 Ni기판(10)을 냉각함으로써, Ni기판(10)의 온도를 150℃ 이하로 유지하면서 땜납 합금막(11)을 성막한다. Ag-Sn-Cu 합금 타겟에는, 예를 들면 주성분이 되는 Sn와 Cu의 중량% 비율이 Sn:Cu=60:40이고, 이에 Ag가 3중량% 첨가된 합금 타겟(Sn-Cu(60:40)-Ag(97:3) 중량% 타겟)이 사용된다. Ag-Sn-Cu 합금 타겟은 스퍼터실(S3) 내의 캐소드 전극(60)(도 3 참조)의 애노드 전극(70) 측의 면 상에 설치된다. 또한, Ni막 부착 기판(10)은 애노드 전극(70)(도 3 참조)의 캐소드 전극(60) 측의 면 상에 피성막면인 이면(Ni막이 형성된 면)을 캐소드 전극(60) 측으로 향하여 설치된다.In the DC pulse sputter for forming the alloy film 11, for example, the OFF duty (t1 / t0) (see FIG. 4A) of the DC pulse is set to 20% and the frequency (1 / . The Ni substrate 10 is cooled by the temperature control unit of the electrostatic chuck to form the solder alloy film 11 while maintaining the temperature of the Ni substrate 10 at 150 캜 or lower. For example, an alloy target (Sn-Cu (60:40) having Sn: Cu = 60: 40 in which the weight percentage of Sn and Cu as main components is Sn: ) -Ag (97: 3) wt% target) is used. The Ag-Sn-Cu alloy target is provided on the side of the anode electrode 70 side of the cathode electrode 60 (see FIG. 3) in the sputter chamber S3. The Ni film-adhered substrate 10 has a structure in which the back surface (the surface on which the Ni film is formed) of the anode electrode 70 (see FIG. 3) on the cathode electrode 60 side is directed toward the cathode electrode 60 Respectively.

(성막된 기판(10)의 반출)(Removal of the deposited substrate 10)

그 후, 로드 로크실(L/UL)과의 사이의 밸브 기구를 열고 핸들러(H0)에 의해 합금막(11)을 형성한 Ni막 부착 기판(10)을 반송실(T0)로부터 반출하고 반송실(T0)과 로드 로크실(L/UL) 사이의 밸브 기구를 닫는다. 그리고, 로드 로크실(L/UL)을 벤트하여 이동탑재기(T1)와의 사이의 밸브 기구를 개방한 후, 이동탑재기(T1)의 핸들러(H1)에 의해 로드 로크실(L/UL) 내의 상기 Ni막 부착 기판(10)을 카세트(C2)로 되돌린다.Thereafter, the Ni film-adhered substrate 10 on which the alloy film 11 is formed by the handler H0 with the valve mechanism between the load lock chamber L / UL is removed from the transport chamber T0, The valve mechanism between the chamber T0 and the load lock chamber L / UL is closed. After the valve mechanism between the load lock chamber L / UL and the mobile unit T1 is opened by venting the load lock chamber L / UL, the handler H1 of the mobile unit T1 presses the above- The Ni film-adhered substrate 10 is returned to the cassette C2.

(기판(10)의 냉각)(Cooling of the substrate 10)

DC 스퍼터는 일반적으로 RF 스퍼터보다 스퍼터 레이트가 높지만, 기판(10)의 온도가 상승하면 기판(10)에 부착된 금속이 유리하기 쉬워지므로 스퍼터 레이트가 저하된다. 그래서, 기판(10)을 냉각하면 기판(10)에 부착된 금속이 유리하기 어려워지므로, 스퍼터 레이트의 저하를 억제할 수 있다. 본 실시형태의 땜납 합금막(11)의 DC 펄스 스퍼터에서는, DC 펄스의 OFF 기간(t1)(도 4a 참조)에서 기판(10)이 냉각되어 기판(10)의 온도 상승을 억제할 수 있으므로, 스퍼터 레이트의 저하를 억제할 수 있고, RF 스퍼터보다 높은 스퍼터 레이트를 확보할 수 있다.The sputter rate of the DC sputter is generally higher than that of the RF sputter. However, when the temperature of the substrate 10 rises, the metal attached to the substrate 10 tends to be favorable, so that the sputter rate is lowered. Therefore, since the metal attached to the substrate 10 is less likely to be liberated when the substrate 10 is cooled, a decrease in the sputter rate can be suppressed. The DC pulse sputtering of the solder alloy film 11 of the present embodiment can cool the substrate 10 in the OFF period t1 (see Fig. 4A) of the DC pulse to suppress the temperature rise of the substrate 10, Deterioration of the sputter rate can be suppressed and a sputter rate higher than that of the RF sputter can be ensured.

또, 본 실시형태의 땜납 합금막(11)의 DC 펄스 스퍼터에서는, 정전 척의 온도 제어부에 의해 기판(10)을 냉각하여 기판 온도를 150℃이하의 소정 온도로 유지하고 있으므로, 스퍼터 레이트의 저하를 효과적으로 억제할 수 있다. 여기서, 기판 온도를 150℃이하로 하는 것은, 일반적인 땜납의 융점이 150℃이고, 150℃이상의 온도가 되면 박막의 땜납이 증발하기 때문이다.In the DC pulse sputtering of the solder alloy film 11 of the present embodiment, since the substrate 10 is cooled by the temperature control unit of the electrostatic chuck and the substrate temperature is maintained at a predetermined temperature of 150 占 폚 or lower, It can be suppressed effectively. Here, the substrate temperature is set to 150 占 폚 or less because a melting point of a general solder is 150 占 폚, and when the temperature is 150 占 폚 or more, the solder of the thin film evaporates.

이상과 같이, 본 실시형태에 따르면, 캐소드 전극(60)에 DC 펄스 전압을 인가하는 DC 펄스 스퍼터에 의해 저융점 금속 Cu를 함유하는 합금막(11)을 성막함으로써, 합금막(11)의 함유 금속 조성의 어긋남을 발생시키지 않고, 또한 성막 레이트를 저하시키지 않고 성막할 수 있다. 따라서, 종래 기술에서 땜납층 성막을 위한 기판(10)의 대기 폭로시의 산화 방지막으로서 필요하였던 하지막을 마련할 필요가 없다. 이에 의해, 땜납 합금막(11)을 성막하기 위해 기판(10)을 스퍼터 장치(110)로부터 취출하여 진공 증착 장치에 설정할 때의 수고나 기판(10)의 파손 등을 저감할 수 있음과 동시에, 하지막의 금속 재료로서 사용하였던 귀금속(예를 들면 Au 등)의 비용을 저감할 수 있다.As described above, according to the present embodiment, the alloy film 11 containing the low-melting-point metal Cu is formed by the DC pulse sputtering which applies the DC pulse voltage to the cathode electrode 60, The film formation can be performed without causing a shift in the metal composition and without lowering the film formation rate. Therefore, it is not necessary to provide a base film which is required as an oxidation preventing film when the substrate 10 for the solder layer film formation is exposed in the prior art. This makes it possible to remove the substrate 10 from the sputtering apparatus 110 in order to form the solder alloy film 11 and to set the thickness of the substrate 10 in the vacuum evaporation apparatus and the breakage of the substrate 10, It is possible to reduce the cost of the noble metal (for example, Au or the like) used as the underlying metal material.

상술한 바와 같이 DC 펄스 스퍼터에는 뛰어난 점이 존재하지만, 본 발명은 DC 펄스 스퍼터에 한정되는 것은 아니다. 적절한 구성으로 한 성막 장치나 적절한 성막 조건 등을 설정함으로써, DC 펄스 스퍼터 대신에 DC 스퍼터를 이용해도 본 발명은 실현할 수 있다.As described above, there is an advantage in the DC pulse sputter, but the present invention is not limited to the DC pulse sputter. The present invention can be realized by using a DC sputtering instead of the DC pulse sputtering by setting a suitable film forming apparatus and an appropriate film forming condition.

또한, 후술하는 실시예에 나타나는 바와 같이, 땜납으로 이루어지는 합금막(11)을 형성할 때에 캐소드 전극(60)에 DC 펄스 전압을 인가함으로써, 박막화되어도 종래와 동등한 기계적 특성, 전기적 특성을 확보한 합금막을 성막하는 것이 가능하다. 특히, 종래 밀착층으로서 이용되었던 Au막을 형성하지 않아도 충분한 접합 강도를 확보할 수 있고 비용의 저하를 도모할 수 있다.In addition, as shown in the later-described embodiments, by applying a DC pulse voltage to the cathode electrode 60 when forming the alloy film 11 made of solder, the alloy having the same mechanical characteristics and electrical characteristics It is possible to form a film. Particularly, sufficient bonding strength can be ensured without forming an Au film, which has been used as a conventional adhesive layer, and cost reduction can be achieved.

이와 같이 하여 형성되는 합금막(11)의 두께로서는 특별히 한정되는 것은 아니지만, 예를 들면 2㎛이상 10㎛이하로 하는 것이 바람직하다.The thickness of the alloy film 11 thus formed is not particularly limited, but is preferably 2 m or more and 10 m or less, for example.

후술하는 바와 같이, Ni막 부착 기판(혹은 Ni기판(10))(10) 상에 형성된 합금막(11) 상에 부품(14)을 올려놓고 열처리(리플로우)하여 3자를 접합한다. 이 때, 합금막(11)에서 기판(10)과 접하는 측에는 기판(10)에 포함되는 Ni가 침입하여 이 Ni와 Sn의 합금 영역(α)이 형성된다. 또한, 합금막(11)에서 부품(14)과 접하는 측에는 부품(14)에 포함되는 Cu 또는 Ni가 침입하여 이 Cu 또는 Ni와 Sn의 합금 영역(β)이 형성된다. 이들 합금 영역(α), 합금 영역(β)은 모두 1㎛정도의 두께가 되는 것을 본 발명자들은 확인하였다. 그 때문에, 합금막(11)의 두께로서는 적어도 (1㎛+1㎛=)2㎛인 것이 바람직하다. 한편, 합금막(11)이 10㎛보다 두꺼우면 막에 크랙이 생길 우려가 있다.As described later, the component 14 is placed on the alloy film 11 formed on the Ni film-attached substrate (or the Ni substrate 10) 10 and heat-treated (reflowed) to join the three members. At this time, Ni contained in the substrate 10 enters the side of the alloy film 11 in contact with the substrate 10, and an alloy region? Of Ni and Sn is formed. Cu or Ni contained in the component 14 penetrates into the side of the alloy film 11 in contact with the component 14 to form an alloy region beta of Cu or Ni and Sn. The present inventors have confirmed that these alloying regions? And alloy regions? All have a thickness of about 1 占 퐉. Therefore, it is preferable that the thickness of the alloy film 11 is at least (1 mu m + 1 mu m =) 2 mu m. On the other hand, if the alloy film 11 is thicker than 10 mu m, cracks may occur in the film.

(순서 1b)(Step 1b)

다음에, 필요에 따라 도 1b에 도시된 바와 같이, 후공정에서 부품(14)을 마운트하는 영역에 해당하는 부분에 관통공(12a)을 구비한 테이프 형상의 레지스트(12)를 상기 합금막(11) 상에 마련한다(공정 A2). 후공정이란 조립, 검사를 행하는 공정이다.Next, as shown in FIG. 1B, a tape-shaped resist 12 having a through hole 12a at a portion corresponding to a region for mounting the component 14 in a later process is formed on the alloy film ( 11) (step A2). The post-process is a process for assembling and inspecting.

합금막(11) 상에 소정 두께의 테이프 형상의 레지스트(12)를 붙인다. 테이프 형상의 레지스트(12)에는, 후공정에서 부품(14)을 마운트하는 영역에 해당하는 부분에 관통공(12a)(개구부)이 설치되어 있다.A tape-shaped resist 12 having a predetermined thickness is adhered to the alloy film 11. The tape-shaped resist 12 is provided with a through hole 12a (opening portion) in a portion corresponding to a region for mounting the component 14 in a later process.

테이프 형상의 레지스트(12)로서는 특별히 한정되는 것은 아니지만, 예를 들면 폴리이미드 테이프가 이용된다.The tape-shaped resist 12 is not particularly limited, but polyimide tape is used, for example.

(순서 1c)(Step 1c)

다음에, 도 1c에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는, 레지스트(12)의 관통공(12a)을 통과하여 보임) 상기 합금막(11) 상에 플럭스(13)를 도포하여 상기 합금막(11)의 표층을 이루는 산화막을 제거한다(공정 A6).Next, as shown in Fig. 1C, the flux 13 is formed on the alloy film 11 (through the through hole 12a of the resist 12 when the resist 12 is formed) And the oxide film forming the surface layer of the alloy film 11 is removed (step A6).

합금막(11) 상에 부품(14)의 접합면과 접촉시킬 때, 합금막(11) 표면에 잔류되어 있는 산화막을 화학적으로 제거하기 위해 플럭스(13)를 도포한다. 이 플럭스(13)에는, 이 금속 산화물과 반응하여 이를 용해 제거하는 작용을 갖는 활성화학종이 함유되어 있다. 그 후, 세정 처리를 행함으로써 산화막이 제거된다.The flux 13 is applied to chemically remove the oxide film remaining on the surface of the alloy film 11 when the alloy film 11 is brought into contact with the bonding surface of the component 14. [ The flux 13 contains an active chemical species that reacts with the metal oxide to dissolve and remove the metal oxide. Thereafter, the oxide film is removed by performing a cleaning process.

(순서 1d)(Step 1d)

다음에, 도 1d에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는, 레지스트(12)의 관통공(12a)을 통과하여 보임) 상기 합금막(11) 상에 적어도 접촉 부위가 구리(Cu) 또는 니켈(Ni) 피복된 알루미늄(Al)으로 이루어지는 부품(14)을 올려놓는다(공정 A3).Then, as shown in Fig. 1D, at least the contact portion on the alloy film 11 (the resist 12 is seen to pass through the through hole 12a of the resist 12) (Cu) or nickel (Ni) -coated aluminum (Al) (step A3).

(순서 1e)(Step 1e)

다음에, 도 1e에 도시된 바와 같이, 상기 기판(10)과 상기 합금막(11) 및 상기 합금막(11)과 상기 부품(14)의 사이를 각각 접합하기 위해 열처리를 실시한다(공정 A4).Next, as shown in FIG. 1E, heat treatment is performed to bond the substrate 10, the alloy film 11, the alloy film 11, and the component 14, respectively (step A4 ).

원적외선 히터 및 열풍을 이용하여 열처리(리플로우)를 실시함으로써, 기판(10)과 합금막(11) 및 합금막(11)과 부품(14)의 사이가 각각 접합되고, 이에 의해 기판(10), 합금막(11) 및 부품(14)의 3자가 접합된다.The substrate 10 and the alloy film 11 and the alloy film 11 and the component 14 are bonded to each other by heat treatment (reflow) using a far-infrared heater and hot air, The alloy film 11 and the component 14 are bonded together.

이 때, 기판(10)과 합금막(11) 및 부품(14)을 올려놓는 것만으로는 어떤 변화도 생기지 않는데, 열처리함으로써 접합 계면에서 다음과 같은 변화가 생기는 것을 본 발명자들은 발견하였다.At this time, no change is caused simply by placing the substrate 10, the alloy film 11 and the component 14, and the present inventors have found that the following changes occur at the bonding interface by the heat treatment.

여기서, 도 5는 기판(10), 합금막(11) 및 부품(14)의 부분을 확대하여 모식적으로 도시한 도면이다.5 is an enlarged view schematically showing a portion of the substrate 10, the alloy film 11, and the component 14. As shown in Fig.

기판(10)에 해당하는 「부재 a」 상에 합금막(11)에 해당하는 「땜납(Sn계)」, 부품(14)에 해당하는 「부재 b」의 순으로 설치하여 리플로우(열처리)한 물품에서는, 「땜납(Sn계)」의 「부재 a」 측에 「부재 a에 포함되는 원소 X가 침입하여 이 원소 X와 Sn의 합금 영역(α)이 형성된다. 또한, 「땜납(Sn계)」의 「부재 b」 측에는 「부재 b에 포함되는 원소 Y가 침입하여 이 원소 Y와의 합금 영역(β)이 형성된다. 「땜납」은 2개의 합금 영역(α, β)에 끼워지는 영역에 타겟 조성과 같은 합금 영역(γ)(Sn-Ag-Cu)이 존재한다.The solder (Sn system) corresponding to the alloy film 11 and the " member b " corresponding to the component 14 are arranged in this order on the member a corresponding to the substrate 10 and reflowed (heat- In one article, the element X contained in the member a penetrates into the "member a" side of the "solder (Sn system)" to form an alloy region α between the element X and the Sn. On the "member b" side of the "solder (Sn system)", an element Y contained in the member b penetrates to form an alloy region β with the element Y. The "solder" has an alloy region γ (Sn-Ag-Cu) such as a target composition in a region sandwiched between two alloy regions (α, β).

즉, 본 실시형태에서는 도 5에 도시된 바와 같이, 우선, 하방의 기판(10)(Ni)과 합금막(11)(Sn-Ag-Cu)의 접합 계면에서는 Ni가 땜납 중에 침입하여 (Sn-Ni) 합금 영역(α)이 형성된다. 합금 영역(α)은 1㎛정도의 두께가 된다.That is, in this embodiment, as shown in Fig. 5, Ni enters the solder at the bonding interface between the lower substrate 10 (Ni) and the alloy film 11 (Sn-Ag-Cu) -Ni alloy region (?) Is formed. The alloy region? Has a thickness of about 1 占 퐉.

한편, 상방의 합금막(11)(Sn-Ag-Cu)과 부품(14)(Cu 또는 Ni 코트된 Ag)의 접합 계면에서는 Cu 또는 Ni가 땜납 중에 침입하여 (Sn-Cu) 혹은 (Sn-Ni) 합금 영역(β)이 형성된다. 합금 영역(β)은 1㎛정도의 두께가 된다.On the other hand, at the bonding interface between the upper alloy film 11 (Sn-Ag-Cu) and the component 14 (Cu or Ni coated Ag), Cu or Ni penetrates into the solder (Sn- Ni) alloy region (beta) is formed. The alloy region beta has a thickness of about 1 mu m.

그리고, 땜납 합금막(11)에서 2개의 합금 영역(α, β)에 끼워지는 영역에는 타겟 조성과 같은 합금 영역(γ)(Sn-Ag-Cu)이 존재한다.In the region of the solder alloy film 11 sandwiched between the two alloy regions? And?, An alloy region? (Sn-Ag-Cu) similar to the target composition exists.

이들 합금 영역(α)(Sn-Ni), 합금 영역(β)(Sn-Cu 혹은 Sn-Ni)은 합금 영역(γ)(Sn-Ag-Cu)에 비해 단단한 부분이 된다. 이에 의해, 땜납 합금막(11)을 얇게 해도 충분한 기계적 강도를 확보할 수 있다.The alloy region? (Sn-Ni) and the alloy region? (Sn-Cu or Sn-Ni) are harder than the alloy region? (Sn-Ag-Cu). Thus, even if the solder alloy film 11 is made thin, a sufficient mechanical strength can be secured.

열처리(리플로우)의 온도로서는 특별히 한정되는 것은 아니지만, 예를 들면 240~250℃로 하는 것이 바람직하다. 통상보다 높은 240~250℃에서 열처리함으로써 양호하게 접합할 수 있다.The temperature of the heat treatment (reflow) is not particularly limited, but is preferably 240 to 250 ° C, for example. It can be satisfactorily bonded by heat treatment at 240 to 250 DEG C, which is higher than usual.

(순서 1f)(Step 1f)

마지막으로, 도 1f에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는) 상기 레지스트(12)를 제거한다(공정 A5).Finally, as shown in Fig. 1F, the resist 12 is removed (in the case where the resist 12 is formed) (step A5).

마지막으로, 테이프 형상의 레지스트(12)를 제거(박리)함으로써, 기판(10) 상에 땜납으로 이루어지는 합금막(11)을 개재하여 부품(14)이 실장된 실장품을 얻을 수 있다.Finally, by removing (stripping) the tape-shaped resist 12, it is possible to obtain a package in which the component 14 is mounted via the alloy film 11 made of solder on the substrate 10.

또, 당연하지만 레지스트(12)를 형성할 필요가 없는 경우에는 상술한 「공정 A2」와 「공정 A5」는 필요 없다.Needless to say, when there is no need to form the resist 12, the above-mentioned "process A2" and "process A5" are not necessary.

이상 설명한 바와 같이, 본 발명에서는 땜납으로 이루어지는 합금막(11)을 형성할 때에 상기 캐소드 전극(60)에 DC 펄스 전압을 인가함으로써, 박막화되어도 종래와 동등한 기계적 특성, 전기적 특성을 확보한 합금막(11)을 성막하는 것이 가능하다. 이에 의해, 본 발명에서는 종래와 동등한 기계적 특성, 전기적 특성을 확보하면서 합금막(11)을 박막화하는 것이 가능하고 저비용화, 박형화를 실현할 수 있다.As described above, in the present invention, when a DC pulse voltage is applied to the cathode electrode 60 when forming the alloy film 11 made of solder, the alloy film 11 having the same mechanical characteristics and electrical characteristics 11 can be formed. Thus, in the present invention, it is possible to make the alloy film 11 thinner while ensuring mechanical properties and electrical characteristics equivalent to those of the prior art, thereby realizing reduction in cost and thickness.

이와 같이 하여 얻어진 실장품에 있어서, 땜납으로 이루어지는 합금막(11)(Sn-Ag-Cu)은 기판(10)(Ni층) 근방에 (Sn-Ni) 합금 영역(α)을, 부품(Cu 부품 혹은 Ni 코트 Al 부품)(14) 근방에 (Sn-Cu) 합금 혹은 (Sn-Ni) 합금 영역(β)을 각각 포함한다.In the thus obtained package, the alloy film 11 (Sn-Ag-Cu) made of solder has a (Sn-Ni) alloy region? In the vicinity of the substrate 10 (Sn-Cu) alloy or (Sn-Ni) alloy region (β) in the vicinity of the Ni-coated Al component (14).

<제2 실시형태>&Lt; Second Embodiment >

다음에, 본 발명의 제2 실시형태에 대해 설명한다.Next, a second embodiment of the present invention will be described.

또, 이하의 설명에 있어서 상술한 제1 실시형태와 다른 부분에 대해 주로 설명하고, 제1 실시형태와 동일한 부분에 대해서는 그 설명을 생략하는 경우가 있다.In the following description, a description will be mainly given of a part different from the first embodiment described above, and a description of the same parts as those in the first embodiment may be omitted.

도 6a~도 6f는 본 실시형태에 의한 부품의 제조 방법을 설명하는 공정 단면도이다.6A to 6F are process cross-sectional views illustrating a method of manufacturing a component according to the present embodiment.

(순서 2a)(Step 2a)

우선, 도 6a에 도시된 바와 같이, 한쪽 면이 니켈(Ni)로 이루어지는 기판(10)을 이용하고, 상기 한쪽 면 상에 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금막(11)을 스퍼터법에 의해 형성한다(공정 B1).First, as shown in FIG. 6A, a substrate 10 made of nickel (Ni) on one side is used and an alloy (Ag) containing tin (Sn) and copper The film 11 is formed by a sputtering method (step B1).

도 2에 도시된 바와 같은 장치를 이용하여 감압 분위기로 한 공간 내에 은(Ag), 주석(Sn) 및 구리(Cu)를 함유하는 합금 타겟을 마련한 캐소드 전극(60)과 상기 기판(10)을 마련한 애노드 전극(70)을 대향하여 배치하고, 상기 기판(10)의 한쪽 면 상에 상기 합금막(11)을 형성할 때에 상기 캐소드 전극(60)에 DC 펄스 전압을 인가한다.A cathode electrode 60 provided with an alloy target containing silver (Ag), tin (Sn), and copper (Cu) in a space in a reduced pressure atmosphere using an apparatus as shown in Fig. 2, And a DC pulse voltage is applied to the cathode electrode 60 when the alloy film 11 is formed on one side of the substrate 10. [

(순서 2b)(Step 2b)

다음에, 도 6b에 도시된 바와 같이, 필요에 따라 후공정에서 부품(14)을 마운트하는 영역에 해당하는 부분에 관통공(12a)을 구비한 테이프 형상의 레지스트(12)를 상기 합금막(11) 상에 마련한다(공정 B2).Next, as shown in FIG. 6B, a tape-shaped resist 12 having a through hole 12a at a portion corresponding to a region where the component 14 is mounted in a post-process is disposed on the alloy film ( 11) (step B2).

(순서 2c)(Step 2c)

다음에, 도 6c에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는 레지스트(12)의 관통공(12a)을 통과하여 보임) 상기 합금막(11) 상에 적어도 땜납 페이스트(15)를 도포한다(공정 B3).6C, at least the solder paste 15 is formed on the alloy film 11 (through the through hole 12a of the resist 12 when the resist 12 is formed) (Step B3).

이 때, 땜납 페이스트(15)로서 플럭스(13)가 들어간 땜납 페이스트(15)를 이용하는 것이 바람직하다.At this time, it is preferable to use the solder paste 15 containing the flux 13 as the solder paste 15.

(순서 2d)(Step 2d)

다음에, 도 6d에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는 레지스트(12)의 관통공(12a)을 통과하여 보임) 상기 합금막(11) 상에 상기 땜납 페이스트(15)를 개재하여 적어도 접촉 부위가 구리(Cu) 또는 니켈(Ni) 피복된 알루미늄(Al)으로 이루어지는 부품(14)을 올려놓는다(공정 B4).Then, as shown in Fig. 6D, the solder paste 15 is formed on the alloy film 11 (through the through hole 12a of the resist 12 when the resist 12 is formed) A part 14 made of aluminum (Al) coated with copper (Cu) or nickel (Ni) at least at a contact portion is placed thereon (step B4).

(순서 2e)(Step 2e)

다음에, 도 6e에 도시된 바와 같이, 상기 기판(10)과 상기 합금막(11), 상기 합금막(11)과 상기 땜납 페이스트(15) 및 상기 땜납 페이스트(15)와 상기 부품(14)의 사이를 각각 접합하기 위해 열처리(리플로우)를 실시한다(공정 B5).6E, the substrate 10, the alloy film 11, the alloy film 11, the solder paste 15, the solder paste 15, and the component 14 are bonded to each other, Heat treatment (reflow) is carried out to bond the respective layers (step B5).

(순서 2f)(Step 2f)

마지막으로, 도 6f에 도시된 바와 같이, (레지스트(12)를 형성한 경우에는) 상기 레지스트(12)를 제거한다(공정 B6).Finally, as shown in Fig. 6F, the resist 12 is removed (in the case of forming the resist 12) (step B6).

또, 당연하지만 레지스트(12)를 형성할 필요가 없는 경우에는 상술한 「공정 B2」와 「공정 B6」은 필요 없다.Needless to say, in the case where there is no need to form the resist 12, the above-mentioned "step B2" and "step B6" are not necessary.

본 실시형태에서도 땜납으로 이루어지는 합금막(11)을 형성할 때에 상기 캐소드 전극(60)에 DC 펄스 전압을 인가함으로써, 박막화되어도 종래와 동등한 기계적 특성, 전기적 특성을 확보한 합금막(11)을 성막하는 것이 가능하다. 이에 의해, 본 발명에서는 종래와 동등한 기계적 특성, 전기적 특성을 확보하면서 합금막(11)을 박막화하는 것이 가능하고 저비용화, 박형화를 실현할 수 있다.The DC pulse voltage is applied to the cathode electrode 60 at the time of forming the alloy film 11 made of solder in the present embodiment to form the alloy film 11 having the same mechanical characteristics and electrical characteristics It is possible to do. Thus, in the present invention, it is possible to make the alloy film 11 thinner while ensuring mechanical properties and electrical characteristics equivalent to those of the prior art, thereby realizing reduction in cost and thickness.

이와 같이 하여 얻어진 실장품에 있어서, 합금막(11) 및 땜납 페이스트(15)(Sn-Ag-Cu)는 기판(Ni층)(10) 근방에 (Sn-Ni) 합금 영역(α)을, 부품(Cu 부품 혹은 Ni 코트 Al 부품)(14) 근방에 (Sn-Cu) 합금 혹은 (Sn-Ni) 합금 영역(β)을 각각 포함한다.In the thus obtained package, the alloy film 11 and the solder paste 15 (Sn-Ag-Cu) have a (Sn-Ni) alloy region? In the vicinity of the substrate (Ni layer) (Sn-Cu) alloy or (Sn-Ni) alloy region (β) in the vicinity of the component (Cu component or Ni coat Al component)

실시예Example

본 발명의 효과를 확인하기 위해 행한 실시예에 대해 설명한다.Examples for confirming the effects of the present invention will be described.

(실시예 1)(Example 1)

도 2에 도시된 바와 같은 장치를 이용하여 Ni막 부착 기판(10) 상에 땜납(Sn-Ag-Cu) 합금막을 형성하였다.A solder (Sn-Ag-Cu) alloy film was formed on the Ni film-adhered substrate 10 by using the apparatus as shown in Fig.

우선, 스퍼터실(S1)에서 실리콘(Si) 기판(10) 상에 Ni막을 형성하였다. 스퍼터실(S1)의 성막 압력을 0.1Pa~1.0Pa로 하고 Ar 유량을 5sccm~50sccm으로 한 감압 분위기 중에서, Ni 타겟을 사용하여 DC 스퍼터법에 의해 막두께 0.7㎛의 Ni막을 성막하였다.First, an Ni film was formed on the silicon (Si) substrate 10 in the sputter chamber S1. A Ni film having a film thickness of 0.7 mu m was formed by a DC sputtering method using a Ni target in a reduced pressure atmosphere in which the film forming pressure of the sputter chamber S1 was set to 0.1 Pa to 1.0 Pa and the Ar flow rate was set to 5 sccm to 50 sccm.

다음에, Ni막 부착 기판(10)을 스퍼터실(S1)로부터 스퍼터실(S2)로 이동한 후, 스퍼터실(S2)의 성막 압력을 0.1Pa~1.0Pa로 하고 Ar 유량을 5sccm~50sccm으로 한 감압 분위기 중에서, Ag-Sn-Cu 합금의 땜납 타겟(Ag-Sn-Cu 합금 타겟)을 사용하여 DC 펄스 스퍼터(마그네트론 스퍼터)에 의해 막두께 10㎛의 땜납 합금막(11)을 Ni막 부착 기판(10) 상에 형성하였다.Next, after the Ni film-adhered substrate 10 is moved from the sputter chamber S1 to the sputter chamber S2, the deposition pressure of the sputter chamber S2 is set to 0.1 Pa to 1.0 Pa and the Ar flow rate is set to 5 sccm to 50 sccm A solder alloy film 11 having a thickness of 10 占 퐉 was formed by a DC pulse sputter (magnetron sputtering) using a solder target of Ag-Sn-Cu alloy (Ag-Sn-Cu alloy target) Was formed on the substrate 10.

땜납 합금막(11) 상에 Cu 부품(14)을 올려놓고, 그 후 열처리(리플로우)함으로써 Ni막 부착 기판(10), 땜납 합금막(11) 및 부품(14)의 3자를 접합하였다.The Cu component 14 was placed on the solder alloy film 11 and then the heat treatment (reflow) was performed to join the three components of the substrate 10 with the Ni film, the solder alloy film 11 and the component 14.

(실시예 2)(Example 2)

실시예 1과 같이 하여 Ni막 부착 기판(10) 상에 막두께 5㎛의 땜납 합금막(11)을 성막하였다. 땜납 합금막(11) 상에 Cu 부품(14)을 올려놓고, 그 후 열처리(리플로우)함으로써 Ni막 부착 기판(10), 땜납 합금막(11) 및 부품(14)의 3자를 접합하였다.A solder alloy film 11 having a thickness of 5 탆 was formed on the Ni film-adhered substrate 10 in the same manner as in Example 1. The Cu component 14 was placed on the solder alloy film 11 and then the heat treatment (reflow) was performed to join the three components of the substrate 10 with the Ni film, the solder alloy film 11 and the component 14.

(비교예 1)(Comparative Example 1)

Ni막 부착 기판(10) 상에 스퍼터법에 의해 Au막을 성막하고, Au막 상에 땜납을 도포하여 땜납막을 형성하였다. 땜납막 상에 Cu 부품(14)을 올려놓고, 그 후 열처리(리플로우)함으로써 Ni막 부착 기판(10), 땜납막 및 부품(14)의 3자를 접합하였다.An Au film was formed on the Ni film-attached substrate 10 by the sputtering method, and solder was applied on the Au film to form a solder film. The Cu component 14 was placed on the solder film and then the Ni film deposited substrate 10, the solder film and the component 14 were joined by heat treatment (reflow).

실시예 1에 있어서, 이 때의 리플로우 프로파일을 도 7에 나타낸다.In Example 1, the reflow profile at this time is shown in Fig.

도 7로부터, 통상(표준)보다 고온 조건(200-220초의 영역=240~250℃)에서 리플로우하면 좋은 결과가 얻어지는 것을 알 수 있다.From FIG. 7, it can be seen that a good result is obtained when reflowing under a high-temperature condition (range of 200 to 220 seconds = 240 to 250 ° C) higher than normal (standard).

또한, 실시예 1에서 땜납 합금막(11)과 Ni기판(10)의 접합 계면에서의 SEM 사진을 도 8에, 땜납 합금막(11)과 Cu 부품(14)의 접합 계면에서의 SEM 사진을 도 9에 각각 나타낸다.8 shows an SEM photograph of the bonding interface between the solder alloy film 11 and the Ni substrate 10 in Example 1 and an SEM photograph of the bonding interface between the solder alloy film 11 and the Cu component 14 And Fig. 9, respectively.

도 8로부터, Si웨이퍼 상에 마련한 Ni층으로부터 땜납(Sn-Ag-Cu) 중에 Ni가 침입하여 (Sn-Ni) 합금의 영역이 국소적으로(균일하지 않게) 형성되어 있는 것을 알 수 있다. 또한, 도 9로부터, Cu 부품(14)으로부터 땜납 합금막(Sn-Ag-Cu)(11) 중에 Cu가 침입하여 (Sn-Cu) 합금의 영역이 국소적으로(거품형상으로) 형성되어 있는 것을 알 수 있다.From FIG. 8, it can be seen that Ni penetrates into the solder (Sn-Ag-Cu) from the Ni layer provided on the Si wafer, and the region of the (Sn-Ni) alloy is formed locally (not uniformly). 9, Cu is invaded from the Cu component 14 to the solder alloy film (Sn-Ag-Cu) 11 to form a region of the (Sn-Cu) alloy locally .

이들 결과로부터, 본 발명에 관한 땜납 합금막(Sn-Ag-Cu)(11)은 Ni막 부착 기판(Ni막)(10) 근방에 (Sn-Ni) 합금 영역을, Cu 부품(Ni 코트 Al 부품)(14) 근방에 (Sn-Cu) 합금(혹은 (Sn-Ni) 합금) 영역을 각각 포함하고 있는 것이 확인되었다.(Sn-Ag-Cu) 11 according to the present invention has a (Sn-Ni) alloy region in the vicinity of the Ni film- (Sn-Cu) alloy (or (Sn-Ni) alloy) region in the vicinity of the substrate 14

다음에, 실시예 1, 2 및 비교예 1에서 얻어진 실장품에 대해 접합 강도를 측정하였다. 그 결과를 표 1에 나타낸다. 또, 표 1에 나타내는 결과는 10 샘플에 대한 평균값이다.Next, bonding strengths were measured for the mounting products obtained in Examples 1 and 2 and Comparative Example 1. The results are shown in Table 1. The results shown in Table 1 are average values for 10 samples.

막의 구성원소Constituent element of the film 막두께(㎛)Film thickness (占 퐉) 접착강도(N)Adhesive strength (N) 실시예 1Example 1 Sn-Ag-CuSn-Ag-Cu 1010 134.4134.4 실시예 2Example 2 Sn-Ag-CuSn-Ag-Cu 55 96.296.2 비교예 1Comparative Example 1 AuAu -- 123.9123.9

표 1로부터, 본 발명의 Sn-Ag-Cu계 땜납은 종래 밀착층으로서 이용하였던 Au막과 같은 레벨의 접합 강도를 갖는 것을 알 수 있었다. Au막의 경우(비교예 1)에 비해 땜납 합금막(11)의 두께를 5㎛로 한 경우(실시예 2)의 접착 강도는 약간 낮지만, 땜납 합금막(11)의 두께를 10㎛로 한 경우(실시예 1)에는 Au막의 경우(비교예 1)를 웃도는 접합 강도가 얻어지는 것이 확인되었다. 이에 의해, 밀착층으로서 이용되었던 Au막을 형성하지 않아도 충분한 접합 강도를 확보할 수 있고 비용의 저하를 도모할 수 있다.It can be seen from Table 1 that the Sn-Ag-Cu solder of the present invention has the same bonding strength as that of the Au film used as the conventional adhesive layer. The bonding strength in the case of the Au film (Comparative Example 1) (Example 2) where the thickness of the solder alloy film 11 was 5 m was slightly lower, but the thickness of the solder alloy film 11 was 10 m (Example 1), it was confirmed that a bonding strength exceeding that of the Au film (Comparative Example 1) was obtained. Thereby, sufficient bonding strength can be secured without forming the Au film used as the adhesion layer, and the cost can be reduced.

이상, 본 발명의 부품의 제조 방법에 대해 설명하였지만, 본 발명은 상술한 예에 한정되는 것은 아니고, 발명의 취지를 벗어나지 않는 범위에서 적절히 변경 가능하다.Although the method of manufacturing the component of the present invention has been described above, the present invention is not limited to the above-described example, and can be appropriately changed without departing from the gist of the invention.

본 발명에 따르면, 종래와 동등한 기계적 특성, 전기적 특성을 확보하면서 땜납층을 박막화하는 것이 가능하고 저비용화, 박형화를 실현할 수 있는 부품의 제조 방법 및 부품을 제공할 수 있다.According to the present invention, it is possible to provide a method and a component for manufacturing a component that can reduce the thickness of the solder layer while ensuring mechanical characteristics and electrical characteristics equivalent to those of the prior art, and can achieve reduction in cost and thickness.

10 기판 11 땜납 합금막
12 레지스트 12a 관통공
13 플럭스 14 부품
15 땜납 페이스트 50 DC 펄스 전원 유닛
51 DC 전원 52 OFF 펄스 전원
53 인가 전압 생성부 54 제어부
60 캐소드 전극 70 애노드 전극
100 기판 101 하지막
102 레지스트 102a 관통공
103 땜납 페이스트 104 부품
110 스퍼터 장치 C1, C2 카세트
Ea, Ek, Ek1 전위 Ek0 OFF 펄스 전위
Ek2 음의 고정 전위 H0, H1 핸들러
L/UL 로드 로크실 S1, S2, S3 스퍼터실
t0 주기 t1, t2 기간
T0 반송실 T1 이동탑재기10 substrate 11 solder alloy film
12 resist 12a through hole
13 Flux 14 Parts
15 Solder paste 50 DC pulse power supply unit
51 DC Power 52 OFF Pulse Power
53 applied voltage generating unit 54 control unit
60 cathode electrode 70 anode electrode
100 substrate 101 bottom film
102 Resist 102a Through hole
103 solder paste 104 parts
110 Sputtering apparatus C1, C2 Cassette
Ea, Ek, Ek1 Potential Ek0 OFF Pulse potential
Ek2 Negative fixed potential H0, H1 handler
L / UL Load lock thread S1, S2, S3 Sputter thread
t0 period t1, t2 period
T0 Transporting chamber T1 Moving machine

Claims (10)

한쪽 면이 니켈로 이루어지는 기판을 이용하고, 상기 한쪽 면 상에 주석의 함량이 가장 큰 합금막을 스퍼터법에 의해 형성하는 공정 A1;
상기 합금막 상에 적어도 상기 합금막과의 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는 공정 A3;
상기 기판과 상기 합금막 사이 및 상기 합금막과 상기 부품 사이를 각각 접합하기 위해 열처리를 실시하는 공정 A4;를 적어도 차례대로 구비하는 부품의 제조 방법으로서,
상기 공정 A1에서 감압 분위기로 한 공간 내에 주석의 함량이 가장 큰 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치하고, 상기 기판의 상기 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가하며,
상기 공정 A4에서, 상기 기판과 상기 합금막이 접하는 부분에서 Sn-Ni 합금영역(α)이, 상기 합금막과 상기 부품이 접하는 부분에서 Sn-Cu 또는 Sn-Ni 합금영역(β)이 형성되는 것을 특징으로 하는 전자부품의 제조 방법.A step A1 of forming an alloy film having the largest tin content on the one surface by sputtering using a substrate made of nickel on one side;
A step A3 of placing on the alloy film at least a part made of at least one of copper and nickel-coated aluminum in contact with at least the alloy film;
And a step (A4) of performing heat treatment between the substrate and the alloy film and between the alloy film and the component, respectively, the method comprising:
A cathode electrode provided with an alloy target having the largest content of tin in a space defined by the reduced pressure atmosphere in the step A1 and an anode electrode provided with the substrate are arranged to face each other and the alloy film is formed on the one surface of the substrate A DC voltage is applied to the cathode electrode,
In the step A4, a Sn-Ni alloy region (?) Is formed at a portion where the substrate and the alloy film are in contact with each other, and a Sn-Cu or Sn-Ni alloy region Wherein the method comprises the steps of: 청구항 1에 있어서,
상기 공정 A1과 상기 공정 A3의 사이에, 후공정에서 상기 부품이 마운트되는 영역에 해당하는 부분에 관통공이 형성된 테이프 형상의 레지스트를 상기 합금막 상에 마련하는 공정 A2를 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method according to claim 1,
Further comprising a step A2 between the step A1 and the step A3 in which a tape-shaped resist having a through hole is formed in a portion corresponding to a region where the component is mounted in a later step, on the alloy film A method of manufacturing an electronic component. 청구항 2에 있어서,
상기 공정 A2와 상기 공정 A3의 사이에, 상기 레지스트의 상기 관통공을 통과하여 보이는 상기 합금막 상에 플럭스를 도포하여 상기 합금막의 표층을 이루는 산화막을 제거하는 공정 A6을 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method of claim 2,
Further comprising a step A6 between the step A2 and the step A3 to remove an oxide film forming a surface layer of the alloy film by applying a flux on the alloy film seen through the through hole of the resist A method of manufacturing an electronic component. 청구항 2 또는 3에 있어서,
상기 레지스트를 제거하는 공정 A5를 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method according to claim 2 or 3,
And a step A5 of removing the resist. 한쪽 면이 니켈로 이루어지는 기판을 이용하고, 상기 한쪽 면 상에 주석의 함량이 가장 큰 합금막을 스퍼터법에 의해 형성하는 공정 B1;
상기 합금막 상에 적어도 땜납 페이스트를 도포하는 공정 B3;
상기 합금막 상에 상기 땜납 페이스트를 개재하여 적어도 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓는 공정 B4;
상기 기판과 상기 합금막 사이, 상기 땜납 페이스트와 상기 합금막 사이 및 상기 땜납 페이스트와 상기 부품 사이를 각각 접합하기 위해 열처리를 실시하는 공정 B5;를 적어도 차례대로 구비하는 부품의 제조 방법으로서,
상기 공정 B1에서 감압 분위기로 한 공간 내에 주석의 함량이 가장 큰 합금 타겟을 마련한 캐소드 전극과 상기 기판을 마련한 애노드 전극을 대향하여 배치하고, 상기 기판의 상기 한쪽 면 상에 상기 합금막을 형성할 때에 상기 캐소드 전극에 DC전압을 인가하며,
상기 공정 B5에서, 상기 기판과 상기 합금막이 접하는 부분에서 Sn-Ni 합금영역(α)이, 상기 땜납 페이스트와 상기 부품이 접하는 부분에서 Sn-Cu 또는 Sn-Ni 합금영역(β)이 형성되는 것을 특징으로 하는 전자부품의 제조 방법.A step B1 in which a substrate made of nickel is used on one side and an alloy film having the largest tin content on the one side is formed by sputtering;
A step B3 of applying at least a solder paste on the alloy film;
A step B4 of placing a component made of any one of copper and nickel-coated aluminum on the alloy film with the solder paste interposed therebetween;
And a step B5 of performing heat treatment to bond the substrate and the alloy film, between the solder paste and the alloy film, and between the solder paste and the component, respectively,
Wherein a cathode electrode provided with an alloy target having the largest amount of tin in a space defined by the reduced pressure atmosphere in the step B1 and an anode electrode provided with the substrate are disposed to face each other and when the alloy film is formed on the one surface of the substrate A DC voltage is applied to the cathode electrode,
The Sn-Ni alloy region (?) Is formed at a portion where the substrate and the alloy film contact with each other in the step B5 so that the Sn-Cu or Sn-Ni alloy region (?) Is formed at a portion where the solder paste contacts the component Wherein the method comprises the steps of: 청구항 5에 있어서,
상기 공정 B1과 상기 공정 B3의 사이에, 후공정에서 상기 부품이 마운트되는 영역에 해당하는 부분에 관통공이 형성된 테이프 형상의 레지스트를 상기 합금막 상에 마련하는 공정 B2를 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method of claim 5,
Further comprising a step B2 of providing, on the alloy film, a tape-shaped resist having a through hole formed in a portion corresponding to a region where the component is mounted in a subsequent step between the step B1 and the step B3 A method of manufacturing an electronic component. 청구항 6에 있어서,
상기 공정 B3에서 상기 땜납 페이스트가 플럭스를 함유하고 있는 것을 특징으로 하는 전자부품의 제조 방법.The method of claim 6,
And the solder paste contains a flux in the step B3. 청구항 6에 있어서,
상기 레지스트를 제거하는 공정 B6을 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method of claim 6,
And a step B6 of removing the resist. 청구항 7에 있어서,
상기 레지스트를 제거하는 공정 B6을 더 구비하는 것을 특징으로 하는 전자부품의 제조 방법.The method of claim 7,
And a step B6 of removing the resist. 한쪽 면이 니켈로 이루어지는 기판에 상기 한쪽 면 상에 주석의 함량이 가장 큰 합금막을 스퍼터법에 의해 형성하고,
상기 합금막 상에 적어도 상기 합금막과의 접촉 부위가 구리 및 니켈 피복된 알루미늄 중 어느 하나로 이루어지는 부품을 올려놓으며,
상기 기판과 상기 합금막이 접하는 부분에서 Sn-Ni 합금영역(α)이, 상기 합금막과 상기 부품이 접하는 부분에서 Sn-Cu 또는 Sn-Ni 합금영역(β)이 형성되어 있는 것을 특징으로 하는 전자부품.An alloy film having the largest content of tin is formed on the one surface of the substrate made of nickel by the sputtering method,
A part on which at least the contact area with the alloy film is made of copper and nickel-coated aluminum is placed on the alloy film,
Wherein an Sn-Ni alloy region (?) Is formed at a portion where the substrate and the alloy film contact with each other, and an Sn-Cu or Sn-Ni alloy region (?) Is formed at a portion where the alloy film and the component are in contact with each other. part.
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