JP2010040691A - Lead-free bump forming method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability lead-free bump forming method for preventing breakage of Ni due to formation of an inter-metal compound due to contact between Ni as UBM of a bump and a bump material. <P>SOLUTION: Disclosed is the lead-free bump forming method of forming a lead-free bump 17 consisting principally of Sn at a terminal 6 of an integrated circuit, wherein an Ni layer 11 is formed on the terminal, a Cu layer 15 is formed on an Ni layer 11, a lead-free solder layer 16 consisting principally of Sn is formed on the Cu layer 15, and the Ni layer 11, Cu layer 15, and lead-free solder layer 16 are heated to form the spherical lead-free bump. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to a bump forming method in an integrated circuit package, and more particularly to a method for forming a reliable lead-free bump used in a flip chip or wafer level package.

  As the functions of consumer products increase, the size of devices has been further reduced. Minimizing the footprint area of an integrated circuit package (hereinafter simply referred to as “package”), that is, the area of the circuit board occupied by the package, and arranging the packages closely on each other realizes further miniaturization of the device. Needed above. In recent years, consumer products such as mobile phones and digital cameras dominate the market and drive innovation and integration.

  As demand for adding many functions increases, introduction of CSP (Chip Size Packaging) is progressing. This CSP has a chip-sized circuit board and is smaller than a conventional package. Therefore, the introduction of this CSP enables a high-density arrangement, a minimum footprint area, and a short electrical path, and greatly contributes to further miniaturization of electronic devices.

  However, downsizing of the package faces many difficulties. The ITRS (International Semiconductor Technology Roadmap) lists system level issues as one of the most difficult issues. While the development of SOC (System on a Chip) that accommodates multiple functions in one chip and SIP (System in Packaging) in which multiple chips are integrated in one package, these systems are small. As you become more and more, the challenges you face will increase. For example, the reliability problem of the entire system, the thermal problem of individual components, and the problem of how to test a package containing a plurality of components. Furthermore, quality problems due to difficulty in manufacturing due to miniaturization and mechanical reliability problems such as stress are also raised. In addition to this, in high-density mounting, the current that flows in the unit area becomes very high, so it is extremely demanded to improve electrical and thermal reliability.

  In a typical CSP, an integrated circuit is formed on the surface of a Si substrate, and metal pads (terminals of the integrated circuit) are formed at the ends of the integrated circuit. On the substrate having the integrated circuit, a series of steps such as UBM (Under Bump Metallurgy) formation, resist application, bump pattern formation, bump formation, resist removal, UBM etching, and reflow are performed. Solder bumps are manufactured as external joint points of the CSP. And this Si substrate is cut | disconnected for every integrated circuit area | region (Die), and becomes a semiconductor chip. This semiconductor chip is mechanically and electrically fixed on the wiring board of the final product through these solder bumps. More specifically, the integrated circuit of the semiconductor chip and the wiring substrate are electrically connected by heating the solder bump while pressing the solder bump, which is a conductive bonding material, against the wiring substrate.

  More recently, as environmental awareness has increased, it has become a worldwide trend to ban the use of lead-containing solder in electrical products. Currently, the most widely used lead-free solder includes Sn alloys obtained by adding a small amount of at least one of Ag (silver) and Cu (copper) to Sn (tin). Therefore, it can be said that the composition of the lead-free bump that directly replaces the lead-tin alloy used for the conventional application is almost similar to Sn.

  Here, a general formation process of the Sn-based lead-free bump will be described with reference to FIG. First, a substrate (semiconductor wafer) W having an integrated circuit formed on the surface is prepared (step 1). A pad 6 and a protective film 5 as terminals of an integrated circuit are formed on the surface of the substrate W, and the central portion of the pad 6 is exposed from the protective film 5. The substrate W having the integrated circuit is irradiated with ions by reverse sputtering to physically remove impurities on the surface of the substrate W (step 2). A Ti layer 7 as a barrier layer is formed on the surface of the substrate W cleaned by reverse sputtering (step 3). Subsequently, a Cu layer 8 as a conductive seed layer is formed on the Ti layer 7 (step 4). Further, a resist 9 is formed on the Cu layer 8 (step 5) and exposed (step 6). The resist 9 is developed to form a resist pattern (opening) 10 above the pad 6 (step 7). Resist residue (scum) remains on the Cu layer 8 in the resist pattern 10 and is removed (step 8).

  Next, the Ni layer 11 is formed in the resist pattern 10 by electroplating using the Cu layer 8 as a seed (step 9). Next, a lead-free solder layer 12 made of Sn or an Sn-based alloy is formed on the Ni layer 11 by electroplating (step 10). The resist 9 is peeled off (step 11), and the Cu layer 8 and the Ti layer 7 are etched until the protective film 5 is exposed in a region other than the bump forming portion (step 12). Then, the lead-free solder layer 12 is dissolved by a reflow (heating) process to form ball-shaped solder bumps 13 (step 13). In this way, spherical bumps having a diameter of 100 μm or less are formed.

  As described above, the reason for forming the Ni layer and forming the lead-free solder layer made of Sn or Sn-based alloy thereon is that the Ni layer functions as a barrier layer. That is, the Ni layer has a role of preventing the reliability of the integrated circuit from being impaired by a reaction between different kinds of conductive materials such as a diffusion reaction between the solder bump 13 and the integrated circuit, electromigration, and the like.

However, Ni is known as a metal that easily diffuses into Sn. Conventional bump materials are mainly lead-based solders, and the influence of Sn contained in the bump material on Ni is such that there is no problem in practical reliability. Along with this, since the ratio of Sn in the bump material has increased, the influence of Ni by Sn cannot be ignored. In particular, when a solder layer containing Sn as a main component is formed by electroplating and then melted by a reflow process, as shown in FIG. 2, an intermetallic compound (IMC: resulting from a contact reaction between Ni and Sn) is obtained. Intermetallic Compound) is formed. This IMC grows over time, and its thickness reaches 1 μm or more. The IMC of Ni and Sn is brittle, and there is a problem that the IMC breaks early and becomes defective in a reliability test such as a temperature cycle test. In addition, there is a concern that Ni is consumed by the formation of IMC, and the role of the barrier layer cannot be fulfilled, and the life of the semiconductor device is significantly shortened.
Also, in terms of size, the bumps are conventionally as large as several hundreds to 250 μm. However, with the recent high integration, the bump size is further miniaturized, but a reliable Ni barrier layer must be formed. .

International Publication No. 2004/059042 Pamphlet JP 2003-342784 A

  The present invention has been made in view of the above-described conventional problems, and can prevent destruction of Ni due to formation of an intermetallic compound caused by contact between Ni as a bump UBM and a bump material, and has high reliability. An object is to provide a lead-free bump forming method.

  In order to achieve the above-described object, one aspect of the present invention is a method of forming a lead-free bump containing Sn as a main component on a terminal of an integrated circuit, the Ni layer being formed on the terminal, A Cu layer is formed on the Ni layer, a lead-free solder layer mainly composed of Sn is formed on the Cu layer, and a lead-free bump composed of the Ni layer, the Cu layer, and the lead-free solder layer is heated. Thus, a spherical lead-free bump is formed.

In a preferred aspect of the present invention, the Cu layer has a thickness of 0.5 μm to 1 μm.
In a preferred aspect of the present invention, the lead-free solder layer is made of a Sn—Ag alloy.
In a preferred aspect of the present invention, the lead-free solder layer is made of Sn.
In a preferred aspect of the present invention, the terminal is a pad as a metal electrode of an integrated circuit formed on a substrate.

In a preferred embodiment of the present invention, the formation of the Ni layer, the Cu layer, and the lead-free solder layer is continuously formed in a pattern opened in a resist. Method.
In a preferred aspect of the present invention, the spherical lead-free bumps are substantially free of Sn—Ni intermetallic compound crystals.

  Another aspect of the present invention is a lead-free bump as an external junction point of an integrated circuit, a Ni layer as a barrier layer connected to a terminal of the integrated circuit, and a Cu formed on the Ni layer A Sn-Cu intermetallic compound is formed between the lead-free solder layer and the Ni layer. It is characterized by.

  According to the present invention, by forming a Cu layer between the solder bump and the Ni layer, the Ni layer can be prevented from collapsing and the reliability of the integrated circuit can be prevented from being impaired. Improve bump reliability by forming Sn-Cu IMC (intermetallic compound of Sn and Cu) instead of brittle Sn-Ni IMC between solder bump and Ni layer to increase mechanical strength Can do.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 3 is a flow diagram showing a bump forming method according to an embodiment of the present invention. As shown in FIG. 3, first, a substrate (semiconductor wafer) W on which an integrated circuit is formed is prepared (step 1). A pad 6 and a protective film 5 as terminals of the integrated circuit are formed on the surface of the substrate W, and the central portion of the pad 6 is exposed from the protective film 5. The pad 6 functions as a metal electrode of an integrated circuit formed on the substrate W. The substrate W having the integrated circuit is irradiated with ions by reverse sputtering to physically remove impurities on the surface of the substrate W (step 2). A Ti layer 7 as a barrier layer is formed on the surface of the substrate W cleaned by reverse sputtering (step 3). Subsequently, a Cu layer 8 as a conductive seed layer is formed on the Ti layer 7 (step 4). Note that a layer made of a Cu alloy may be formed as the seed layer instead of the Cu layer. Further, a resist 9 is formed on the Cu layer 8 (step 5) and exposed (step 6). The resist 9 is developed to form a resist pattern (opening) 10 above the pad 6 (step 7). Since the residue (scum) of the resist 9 remains on the Cu layer 8 of the resist pattern 10, it is removed (step 8).

  Next, a Ni layer (UBM) 11 is formed in the resist pattern 10 by electroplating using the Cu layer 8 as a seed (step 9). Next, a Cu layer 15 is formed on the Ni layer 11 by electroplating (step 10). Then, a lead-free solder layer 16 made of Sn or an Sn alloy (for example, Sn—Ag) is formed on the Cu layer 15 by electroplating (step 11). In this way, the Ni layer 11, the Cu layer 15, and the lead-free solder layer 16 are continuously formed on the resist pattern 10. The resist 9 is peeled off (step 12), and the Cu layer 8 and the Ti layer 7 are etched until the protective film 5 is exposed in a region other than the bump forming portion (step 13). Then, a lead-free bump composed of the Ni layer 11, the Cu layer 15, and the lead-free solder layer 16 is heated by a reflow (heating) process, and the lead-free solder layer 16 is melted to form ball-shaped solder bumps 17 ( Step 14). A spherical lead-free bump is thus formed.

  FIG. 4 is a cross-sectional view showing the structure of the lead-free bump formed as described above. As can be seen from FIG. 4, Sn—Cu IMC exists between the Ni layer and the solder bump, and almost no Sn—Ni IMC is formed. The thickness of the Cu layer affects whether or not Sn—Ni IMC is formed. That is, if the thickness of the Cu layer is not sufficient, Cu alloyed with Sn disappears, and Sn further alloys with Ni to form Sn—Ni IMC. The thickness of the Cu layer 15 (see FIG. 3) immediately after plating is 0.2 μm to 5 μm, preferably 0.5 μm to 1 μm. When the thickness of the Cu layer is 0.5 μm or more, Sn—Cu IMC is formed thick. However, if the amount of Cu is large, the melting point of the solder bump rises and a defective connection is generated. Therefore, the amount of Cu constituting the Cu layer is 1.0 at% to 20 at compared to the amount of the lead-free solder layer. % (At% is an atomic quantity ratio). The Cu layer is consumed by reaction with Sn, but if the thickness of the Cu layer is generally 1 μm or more, it will not disappear as a layer.

  When a Sn-Ag alloy is used as the material of the lead-free solder layer 16, the Ag concentration in the Sn-Ag alloy is 3.5% by mass or less, preferably 1.6 to 2.6% by mass. . This is to avoid the formation of voids in the solder bumps. The reflow temperature varies somewhat depending on the material of the lead-free solder layer 16, but is generally 250 to 270 ° C. The reflow processing time is 1 to 3 minutes.

  In general, the composition of precipitation components in alloy plating is determined by the concentration of each component in the plating solution and the electrodeposition conditions. Therefore, also in the alloy plating of the present embodiment, the Ag concentration in the alloy plating film is controlled by adjusting the concentration ratio of Ag ions and Sn ions in the alloy plating solution or controlling the electrodeposition conditions. It can be a range. Specifically, (a) a method in which the concentration ratio of Ag ions and Sn ions in the plating bath is kept constant, and the Ag concentration in the alloy plating film is controlled by changing the electrodeposition conditions, or (b) electrodeposition The Ag concentration in the alloy plating film can be controlled by making the conditions constant and changing the concentration ratio of Ag ions and Sn ions in the plating bath.

  In other words, the alloy plating solution contains metal ions that form the alloy, complexing agents that stabilize the metal ions, brighteners to cleanly form the plating film surface, and other additives. Has been. However, since it is the concentration ratio of Ag ions and Sn ions in the alloy plating bath that mainly determines the Ag concentration in the alloy plating film, an experimentally preferable range is found, and plating is performed while maintaining this concentration ratio. Thus, an alloy plating film in which the Ag concentration is controlled is obtained. In fact, when alloy plating is performed with the electrodeposition conditions fixed, the Ag concentration in the alloy plating film is proportional to the concentration ratio of Ag ions and Sn ions present in the plating solution.

  Therefore, if the object to be processed is immersed in an alloy plating solution having a predetermined concentration ratio of Ag ions and Sn ions and plated under a certain electrodeposition condition, an alloy plating film with a controlled Ag concentration is obtained. By reflowing, a bump free from voids can be obtained.

As an example of the alloy plating solution used in this embodiment, the following plating solution can be mentioned.
composition:
Sn ion (Sn ²⁺ ): 10 to 100 g / L (preferably 35 to 50 g / L)
Ag ion (Ag ⁺ ): 0.3 to 8 g / L (preferably 0.6 to 4 g / L)
Methanesulfonic acid: 100 g / L

  In addition, it is known that the composition of precipitation components varies depending on the electrodeposition conditions in alloy plating. Even in the alloy plating of this embodiment, the Ag concentration in the alloy plating film can be changed by changing the electrodeposition conditions. Can do.

  The alloy plating of this embodiment can be performed with various current patterns. Even in the case of DC plating in which a direct current is continuously applied, a direct current is intermittently applied to periodically have a rest period. Intermittent plating may be used.

In the case of DC plating in which plating is performed by continuously applying a direct current, since there is a relationship that the Ag content concentration in the alloy plating film decreases as the current density increases, preferable current conditions are experimentally determined. It is sufficient to perform plating while maintaining the above. Preferred current density in the case of this DC plating is about 10 to 100 / cm ^2.

In addition, in the case of intermittent plating in which a quiescent period periodically exists by performing plating by intermittently applying a direct current, Ag in the case of intermittently applying the same current as when direct current is continuously applied Since the contained concentrations are different, in this case as well, a preferable applied voltage, a ratio of the pause time, and the like are experimentally determined, and plating may be performed while maintaining these conditions. In the case of this intermittent plating, the preferable current density during application is about 10 to 200 mA / cm ² , and the rest time (zero current) is in the range of 1/10 to 1 times the application time.

  The applied voltage in the above two platings varies depending on conditions such as current intensity, base material, thickness, plating solution, and anode, but is preferably about 1 to 5V. There is no restriction | limiting in particular as an apparatus for implementing said alloy plating, A general dip type plating apparatus etc. can be used. However, in actual work, a jig structure that takes into account the mechanical conditions of the object to be processed, a stirring mechanism (paddle structure) for uniformly and quickly supplying metal ions to the entire surface of the object to be processed, such as a wafer, electric field distribution A device equipped with a plating solution circulation system to remove the foreign matter, remove the foreign matter, prevent the plating solution from changing, and provide metal ions uniformly and quickly over the entire surface of the workpiece. It is preferable to use it.

Further, as described above, since it is necessary to adjust the concentration of Ag ions and Sn ions in the plating solution and to perform alloy plating while controlling the electrodeposition conditions, a replenishment mechanism that replenishes Ag ions and Sn ions. , An analytical device for monitoring Ag ions and Sn ions, and a control mechanism for adjusting the concentration of Ag ions and Sn ions in the alloy plating solution and / or controlling the electrodeposition conditions based on analysis information from the analytical devices It is preferable to use a plating apparatus having
The formation of the pad, application of the resist, formation of the resist pattern, and removal of the resist shown in FIG. 3 can all be performed according to conventional methods in this technical field.

  Next, the bump formation method according to the present embodiment and the test results of bumps formed using the conventional method will be described. This test was conducted for the purpose of selecting a material having the smallest possible IMC and the highest shear strength.

Table 1 below shows the conditions of each sample used in the test.

  Each of the above samples was obtained by forming a Ni layer, a Cu layer, and a lead-free solder layer in this order by electrolytic plating. After plating and after reflow treatment, the shear strength and cross section of each sample were examined. Further, after the reflow treatment, each sample was subjected to an HTS (High Temperature Storage) test. In this HTS test, each sample was placed at a temperature of 125 ° C., and the shear strength and the cross section of each sample after 100 hours, 300 hours, and 500 hours were examined in that state. The cross section of the sample is polished, and the thickness and growth state of the IMC observed in the cross section are measured using a scanning electron microscope (SEM), an X-ray microanalyzer (EPMA), an energy dispersive X-ray fluorescence spectrometer (EDX), etc. And observed.

Table 2 below shows the measurement results of the shear strength of each sample shown in Table 1 above. In Table 2 below, the numerical value on the left side of the arrow indicates the strength of the lead-free solder layer immediately after plating, and the numerical value on the right side of the arrow indicates the strength of the solder bump (dissolved lead-free solder layer) after reflow. The unit of the numerical value is mN.

  From Table 2 above, it can be seen that the Sn-Ag bump has a slightly higher shear strength than the Sn bump. It can also be seen that the difference in strength between the Sn bump and the Sn-Ag bump tends to increase as the Cu thickness increases.

Hereinafter, an example of the plating conditions in the above-mentioned test is given.
(A) Cu plating Plating bath composition:
Cu ²⁺ 220 g / L
H ₂ SO ₄ 200 g / L
HCl 5mL / L
Additive 5mL / L
Plating temperature: 25 ° C
Stirring: Mechanical stirring (paddle stirring speed 10 m / min)
Plating solution circulation: Flow rate 2.5L / min
Electrode: Copper anode, distance between electrodes is about 7.5 mm, anode mask φ250 mm
Cathode current density (total ^{current): 5A / dm 2 (7.48A} )

(B) Ni plating Plating bath composition Ni (NH ₂ SO ₄ ) · 4H ₂ O 450 g / L
H ₃ BO ₃ 30g / L
NiCl ₂ · 6H ₂ O 10 g / L
Additive 2mL / L
Plating temperature: 50 ° C
Stirring: Mechanical stirring (paddle stirring speed 10 m / min)
Plating solution circulation: Flow rate 2.5L / min
Electrode: Nickel anode, distance between electrodes is about 75mm, anode mask φ250mm
Cathode current density (total current): 3 A / dm ² (4.49 A)
Plating thickness: 3μm

(C) Sn-Ag plating Plating bath composition Sn ²⁺ 40 g / L
Ag ⁺ 1.5g / L
Methanesulfonic acid 100g / L
Additive 10g / L
(Polyoxyethylene surfactant, thiourea, catechol by weight ratio
2: 2: 1)
Plating temperature: 25 ° C
Stirring: Mechanical stirring (paddle stirring speed 10 m / min)
Plating solution circulation: Flow rate 2.5L / min
Electrode: Titanium anode, distance between electrodes is about 7.5 mm, anode mask φ250 mm
Cathode current density (total ^{current): 10A / dm 2 (14.9A} ), DC plating plating thickness: 140 .mu.m

  5 to 7 show schematic views of bumps SEM images after the reflow of samples 1, 2 and 3 shown in Table 1, and bumps SEM images after 500 hours of HTS test, respectively, and the results of EPMA analysis. FIG. 5 shows the results when no Cu layer is formed between the Ni layer and the Sn layer. After reflow (left figure), a part of Sn and Ni is alloyed at the interface between the Sn layer and the Ni layer. After HTS (right figure), alloying of Sn and Ni proceeds, and Sn—Ni IMC is formed between the Sn layer and the Ni layer.

  FIG. 7 shows the result when a Cu layer of 0.5 μm is formed between the Ni layer and the Sn layer. After reflow (left figure), alloying of Sn and Cu has begun between the Sn layer and the Cu layer, but the Cu layer remains, and alloying of Sn and Ni has almost been performed. Absent. In addition, after HTS (right figure), Sn-Cu IMC is formed by the mutual diffusion of Sn and Cu. However, Sn—Ni IMC is hardly formed, and the erosion of the Ni layer has not progressed. Thus, the Ni layer can be prevented from being destroyed by forming the 0.5 μm Cu layer between the Sn layer and the Ni layer.

FIG. 6 shows the results when a 0.1 μm Cu layer is formed between the Ni layer and the Sn layer. After the reflow (left figure), the Cu layer has almost disappeared, and a part of Sn and Ni has started to be alloyed at the interface between the Sn layer and the Ni layer. After the HTS (right diagram), Ni diffuses into the Sn—Cu layer to form Sn—Cu (Ni) IMC. It is considered that the thickness of the Cu layer between the Sn layer and the Ni layer was not sufficient.
The Cu layer on the right side of each SEM image is a power supply seed layer for performing electroplating, and is not formed as a barrier between the Sn layer and the Ni layer.

It is a flow diagram which shows a general bump formation process. It is sectional drawing which shows the bump produced at the bump formation process shown in FIG. It is a flow diagram which shows the bump formation process which concerns on one Embodiment of this invention. It is sectional drawing which shows the lead free bump produced at the bump formation process which concerns on one Embodiment of this invention. It is a figure which shows the schematic diagram of the SEM image of a lead-free bump when a Cu layer is not formed, and the EPMA analysis result. It is a figure which shows the schematic diagram of the SEM image of a lead-free bump when a 0.1 micrometer Cu layer is formed, and an EPMA analysis result. It is a figure which shows the schematic diagram of the SEM image of a lead-free bump when a 0.5 micrometer Cu layer is formed, and an EPMA analysis result.

Explanation of symbols

5 Protective film 6 Pad (terminal)
7 Ti layer 8 Cu layer 9 Resist 10 Resist pattern 11 Ni layer 12, 16 Lead-free solder layer 13, 17 Solder bump 15 Cu layer

Claims (8)

A method of forming a lead-free bump mainly composed of Sn on a terminal of an integrated circuit,
Forming a Ni layer on the terminal;
Forming a Cu layer on the Ni layer;
Forming a lead-free solder layer mainly composed of Sn on the Cu layer;
A spherical lead-free bump is formed by heating a lead-free bump made of the Ni layer, the Cu layer, and the lead-free solder layer.   The method according to claim 1, wherein the Cu layer has a thickness of 0.5 μm to 1 μm.   The method according to claim 1, wherein the lead-free solder layer is made of a Sn—Ag alloy.   The method according to claim 1, wherein the lead-free solder layer is made of Sn.   2. The method according to claim 1, wherein the terminal is a pad as a metal electrode of an integrated circuit formed on a substrate.   The method according to claim 1, wherein the formation of the Ni layer, the Cu layer, and the lead-free solder layer is continuously formed in a pattern opened in a resist.   The method of claim 1, wherein the spherical lead-free bumps are substantially free of Sn-Ni intermetallic crystals. Lead-free bumps as external junctions of integrated circuits,
A Ni layer as a barrier layer connected to a terminal of the integrated circuit;
A Cu layer formed on the Ni layer;
A lead-free solder layer mainly composed of Sn formed on the Cu layer;
A lead-free bump, wherein a Sn-Cu intermetallic compound is formed between the lead-free solder layer and the Ni layer.

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