WO2001063668A2 - Method of forming lead-free solder alloys by electrochemical deposition process - Google Patents

Method of forming lead-free solder alloys by electrochemical deposition process Download PDF

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Publication number
WO2001063668A2
WO2001063668A2 PCT/US2001/004956 US0104956W WO0163668A2 WO 2001063668 A2 WO2001063668 A2 WO 2001063668A2 US 0104956 W US0104956 W US 0104956W WO 0163668 A2 WO0163668 A2 WO 0163668A2
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WO
WIPO (PCT)
Prior art keywords
layer
silver
tin
lead
free solder
Prior art date
Application number
PCT/US2001/004956
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French (fr)
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WO2001063668A3 (en
Inventor
Jaynal Abedin Molla
William Hines Lytle
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Motorola, Inc., A Corporation Of The State Of Delaware
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Application filed by Motorola, Inc., A Corporation Of The State Of Delaware filed Critical Motorola, Inc., A Corporation Of The State Of Delaware
Priority to AU2001241516A priority Critical patent/AU2001241516A1/en
Publication of WO2001063668A2 publication Critical patent/WO2001063668A2/en
Publication of WO2001063668A3 publication Critical patent/WO2001063668A3/en

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Definitions

  • This invention relates to a method of forming lead-free solder alloys and more particularly to a method of fo ⁇ riing solder alloys by electrochemical deposition for producing very small solder bumps in semiconductor applications.
  • solder alloys in present use throughout the world for electronic packaging are based on a tin-lead (Sn-Pb) alloy system
  • This system has been successfully used for decades primarily because this alloy has reasonable cost as well as acceptable metallurgical and mechanical properties.
  • lead is a heavy metal toxin and regulations have been proposed to eliminate the use of lead-based solders starting in 2002 and recently passed banning lead in 2004. Aside from governmental regulations, there is also a possible consumer-driven perception of having "environmentally friendly" products.
  • the best replacement alloys are Sn-3.5 (wt%)/Ag and Sn-3.7 (wt%)/Ag-0.7 (wt%)/Cu, based on reliability, wettability, cost, maturity, and availability.
  • these alloys have higher melting points (221°C and 217°C, respectively) as compared to eutectic tin- lead (180°C). Therefore, component reliability due to higher reflow temperatures may pose some concerns.
  • the two lead free solder alloys mentioned above are available in a solder paste formulation. As a result, the only way to apply these solder alloys on wafers for bumping is by stencil- printing (also known as screen-printing) teclmology.
  • FIGS. 1 through 6 are shnplified sectional views illustrating sequential steps in a method of forming lead-free solder bumps in accordance with the present invention.
  • a base is illustrated, which in this embodiment is a semiconductor wafer 10 with an electrical contact 11 formed thereon.
  • Contact 11 is surrounded by a dielectric layer 12 so that only a portion of the upper surface is accessible.
  • contact 11 is a 100 Dm diameter bond pad.
  • base 10 can be a semiconductor wafer, a printed circuit board, etc. and, while a semiconductor wafer is explained herein for convenience of understanding, the base can be any electronic apparatus in wliich lead-free solder can be conveniently electroplated.
  • contact 11 can be a bond pad, a simple electrical contact for an electrical circuit, a contact for bumping wafers or chips and printed circuit boards together, electrodes (e.g. a base, source, and/or drain of a transistor) or any other contacts.
  • a layer 15 of titanium- tungsten (TiW) is deposited on the entire surface of base 10, including dielectric layer 12 and contact 11, by some convenient process such as sputtering.
  • a layer 16 of copper is then deposited over the titanium-tungsten layer, again by some convenient process such as sputtering.
  • the titanium tungsten layer 15 serves as a "glue” layer so that copper layer 16 is firmly held in place.
  • Copper layer 16 creates a platform (one terminal of an electroplating cell) onto which electroplated deposition of metal layers can be built up.
  • the structure of FIG. 1 is then spin coated with a photoresist layer 20 having a thickness, of approximately 27 Dm to 30 Dm.
  • Photoresist layer 20 is exposed and developed in a well known process to open a contact area 21 on the surface of copper layer 16 overlying contact 11. As illustrated in FIG. 2, contact area 21 is generally larger than contact 1 1 to provide sufficient space for a solder bump.
  • photoresist layer 20 is generally made sufficiently thick to provide a desired height for the final solder bump, as will be understood presently.
  • a layer 25 of solderable, electrically conductive material for example, copper (Cu), nickel (Ni), or the like, is electrochemically plated, or electroplated from an appropriate bath, e.g., copper from an acid copper bath at a current density in a range of 25 to 40 amperes per square foot (asf).
  • Layer 25 of solderable conductive material is included in overlying relationship to copper layer 16 because tin forms an inte ⁇ netallic compound with copper or nickel and essentially dissolves the copper or nickel.
  • Layer 25 should be thick enough so that a layer of solderable conductive material remains to cover TiW layer 15 after tin is deposited.
  • layer 25 is copper and is deposited to a thickness of approximately 13 Dm to 15 Dm.
  • the entire structure is rinsed in DI water and transferred into a silver (Ag) bath.
  • a silver bath from Technic, Inc. is used, wliich is a cyanide-free silver bath.
  • a layer 26 of silver is electroplated onto layer 25 in a range of approximately 5 to 25 asf.
  • Silver layer 26 is plated to a thickness such that the silver content in the final alloy composition is in a range of approximately 1% to 5% and preferably 3.5%.
  • a layer 27 including tin is electroplated onto silver layer 26. While tin is described herein for convenience, it will be understood that tin alloys, such as Sn-Cu, Sn-Bi, or the like, can be used if desired. Further, when the term “tin” is used in this disclosure it is intended to encompass any such alloys.
  • the entire structure is rinsed again in DI water and transferred into a tin (Sn) bath.
  • a methane sulfonic acid based tin bath is used from Enthone-OMI with a tradename Microfab Sn-200.
  • Layer 27 of tin is deposited at 25 to 40 asf such that the tin content in the final alloy composition is in a range of approximately 95% to 99%. As can be seen in FIG. 3, tin layer 27 is grown above the upper surface of photoresist layer 20 sufficiently to begin to "mushroom” outwardly and form a composite mushroom 28.
  • layer 20 of photoresist is removed to expose the surface of layer 16 of sputtered copper.
  • Cu layer 16 and TiW layer 15 are then etched away surrounding contact area 21 using composite mushroom 28 as a mask.
  • Cu layer 16 and TiW layer 15 remain under composite mushroom 28 to increase the adherence and reduce the resistance of the connection, as illustrated in FIG. 5.
  • a standard wet etch procedure is used in the bimetal etchback process.
  • a commercial copper etch is used to etch back copper layer 16 and expose layer 15 of TiW.
  • TiW layer 15 is then etched back using H2O2.
  • etching TiW layer 15 with H2O2 is very simple because H2O2 does not attack tin but will attack silver if exposed. Since silver layer 26 is spaced from bimetal layers 15 and 16 by copper layer 25, silver layer 26 is basically not exposed.
  • a reflow procedure is performed on composite mushroom 28 to form a bump 30.
  • the plated wafer is soaked with a non-clean flux and is then placed in a furnace to a specific temperature profile which causes mushroom 28 to form a solder alloy and to ball into bump 30.
  • the reflow procedure includes heating the structure to 260°C for a very short time, preferably 60 seconds.
  • the reflow temperature profile in this preferred embodiment includes raising the temperature to a range of 245°C to 260°C with a temperature rising slope of 1.60 °C/second and lowering the temperature (once the desired temperature is achieved) with a falling slope of 2.30°C/second. Because of the very short high temperature, component reliability is not compromised.
  • the thicknesses of the various layers should be adjusted to just exceed the height of photoresist layer 20 to fo ⁇ ri musliroom shape 28.
  • a method of fo ⁇ riing lead-free, Sn/Ag alloy, solder bumps or Sn Ag/Cu alloy, solder bumps is disclosed which is simple and inexpensive to use and which will not damage semiconductor components on a soldered wafer.
  • the lead-free solder alloy is fo ⁇ ried without the need to develop a Sn/Ag alloy plating bath.
  • the lead-free solder alloy is free of alpha particle emission when used in active electronic circuits. Because the lead-free alloy is fo ⁇ ried by electroplating, fine pitch capability is achieved. Individual Sn and Ag baths are easy to control, making the entire process simple and applicable to achieve high yield bumping on wafers. Further, the etch back of the bimetal base is protected and simple to achieve with little or no damage to surrounding structures.

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Abstract

A method of forming lead-free solder bumps includes sputtering a titanium-tungsten (TiW) layer on the surface of a semiconductor wafer and a copper layer on the titanium-tungsten layer. Photoresist is used to define a contact area on the copper layer. A layer of solderable electrically conductive material is plated on the sputtered copper layer in the contact area, a layer of silver is plated on the solderable material, and a layer including tin is plated on the silver. The photoresist material is removed and, using the tin, silver, and solderable material layers as a mask, the sputtered copper and the titanium-tungsten are etched away from the surface of the wafer surrounding the contact area. The tin, silver, and solderable material layers are then reflowed to form a solder alloy bump.

Description

METHOD OF FORMING LEAD-FREE SOLDER ALLOYS BY ELECTROCHEMICAL DEPOSITION PROCESS
Field of the Invention
This invention relates to a method of forming lead-free solder alloys and more particularly to a method of foπriing solder alloys by electrochemical deposition for producing very small solder bumps in semiconductor applications.
Background of* the Invention
The solder alloys in present use throughout the world for electronic packaging (surface mount technology in printed circuit boards, flip chip in wafer level, etc.) are based on a tin-lead (Sn-Pb) alloy system This system has been successfully used for decades primarily because this alloy has reasonable cost as well as acceptable metallurgical and mechanical properties. However, lead is a heavy metal toxin and regulations have been proposed to eliminate the use of lead-based solders starting in 2002 and recently passed banning lead in 2004. Aside from governmental regulations, there is also a possible consumer-driven perception of having "environmentally friendly" products.
In addition to the environmental issue regarding the use of lead bearing alloys in microelectronics applications, there is another issue of using lead in solder in an advanced CMOS teclmology. When used near active circuits, alpha particle emission from lead can result in soft errors (SER).
At present, the best replacement alloys are Sn-3.5 (wt%)/Ag and Sn-3.7 (wt%)/Ag-0.7 (wt%)/Cu, based on reliability, wettability, cost, maturity, and availability. However, these alloys have higher melting points (221°C and 217°C, respectively) as compared to eutectic tin- lead (180°C). Therefore, component reliability due to higher reflow temperatures may pose some concerns. The two lead free solder alloys mentioned above are available in a solder paste formulation. As a result, the only way to apply these solder alloys on wafers for bumping is by stencil- printing (also known as screen-printing) teclmology.
However, for fine pitch applications, such as 150 Dm pitch or less, screen- printing is not a desirable process to achieve high yield bumping on wafers. In this respect, electrolytically deposited lead-free solder would be the most desirable process to satisfy the fine pitch requirements. While tin-lead solder alloys were successfully deposited by electroplating techniques, to date no plating bath chemistry is available for electroplating of Sn-Ag or Sn-Ag-Cu alloys. Plating baths that consist of tin and silver elements are not available because the standard potentials of tin and silver are widely separated (the standard electrode potentials at 25°C for Sn2+ + 2e is -0.136 and for Ag+ + e is +0.779). Therefore, alloy plating of tin and silver under such a situation is not feasible. Indeed, several companies, such as Lucent Technologies, Shipley- LeaRonal, Uyemura International Corp., etc. have been working on developing the bath chemistry intensively for a year, but without much success.
Accordingly it is highly desirable to provide a method of foπning lead- free solder bumps for semiconductor applications. Further, it is desirable to provide a method of tbιτning lead-free solder bumps for semiconductor applications wliich is inexpensive and easy to perform. Brief Description of the Drawings
Referring to the drawings:
FIGS. 1 through 6 are shnplified sectional views illustrating sequential steps in a method of forming lead-free solder bumps in accordance with the present invention.
Detailed Description of the Drawings
Tuπiing to the drawings and specifically to FIG. 1, a base is illustrated, which in this embodiment is a semiconductor wafer 10 with an electrical contact 11 formed thereon. Contact 11 is surrounded by a dielectric layer 12 so that only a portion of the upper surface is accessible. In this specific example, contact 11 is a 100 Dm diameter bond pad. Here it will be understood that base 10 can be a semiconductor wafer, a printed circuit board, etc. and, while a semiconductor wafer is explained herein for convenience of understanding, the base can be any electronic apparatus in wliich lead-free solder can be conveniently electroplated. Further, contact 11 can be a bond pad, a simple electrical contact for an electrical circuit, a contact for bumping wafers or chips and printed circuit boards together, electrodes (e.g. a base, source, and/or drain of a transistor) or any other contacts.
A layer 15 of titanium- tungsten (TiW) is deposited on the entire surface of base 10, including dielectric layer 12 and contact 11, by some convenient process such as sputtering. A layer 16 of copper is then deposited over the titanium-tungsten layer, again by some convenient process such as sputtering. In siixiplified teπns, the titanium tungsten layer 15 serves as a "glue" layer so that copper layer 16 is firmly held in place. Copper layer 16 creates a platform (one terminal of an electroplating cell) onto which electroplated deposition of metal layers can be built up. In this preferred embodiment, approximately 2000 A of TiW followed by a layer of Cu, with a thickness in a range of approximately 1000 A to 10,000 A, are sputtered across the entire surface of dielectric layer 12 and contact 11. Referring to FIG. 2, the structure of FIG. 1 is then spin coated with a photoresist layer 20 having a thickness, of approximately 27 Dm to 30 Dm. Photoresist layer 20 is exposed and developed in a well known process to open a contact area 21 on the surface of copper layer 16 overlying contact 11. As illustrated in FIG. 2, contact area 21 is generally larger than contact 1 1 to provide sufficient space for a solder bump. Also, photoresist layer 20 is generally made sufficiently thick to provide a desired height for the final solder bump, as will be understood presently.
Referring additionally to FIG. 3, a layer 25 of solderable, electrically conductive material, for example, copper (Cu), nickel (Ni), or the like, is electrochemically plated, or electroplated from an appropriate bath, e.g., copper from an acid copper bath at a current density in a range of 25 to 40 amperes per square foot (asf). Layer 25 of solderable conductive material is included in overlying relationship to copper layer 16 because tin forms an inteπnetallic compound with copper or nickel and essentially dissolves the copper or nickel. Layer 25 should be thick enough so that a layer of solderable conductive material remains to cover TiW layer 15 after tin is deposited. In this specific embodiment layer 25 is copper and is deposited to a thickness of approximately 13 Dm to 15 Dm.
The entire structure is rinsed in DI water and transferred into a silver (Ag) bath. In this preferred embodiment, a silver bath from Technic, Inc. is used, wliich is a cyanide-free silver bath. A layer 26 of silver is electroplated onto layer 25 in a range of approximately 5 to 25 asf. Silver layer 26 is plated to a thickness such that the silver content in the final alloy composition is in a range of approximately 1% to 5% and preferably 3.5%.
Next a layer 27 including tin is electroplated onto silver layer 26. While tin is described herein for convenience, it will be understood that tin alloys, such as Sn-Cu, Sn-Bi, or the like, can be used if desired. Further, when the term "tin" is used in this disclosure it is intended to encompass any such alloys. The entire structure is rinsed again in DI water and transferred into a tin (Sn) bath. In this preferred embodiment, a methane sulfonic acid based tin bath is used from Enthone-OMI with a tradename Microfab Sn-200. Layer 27 of tin is deposited at 25 to 40 asf such that the tin content in the final alloy composition is in a range of approximately 95% to 99%. As can be seen in FIG. 3, tin layer 27 is grown above the upper surface of photoresist layer 20 sufficiently to begin to "mushroom" outwardly and form a composite mushroom 28.
Tuπiing now to FIG. 4, layer 20 of photoresist is removed to expose the surface of layer 16 of sputtered copper. Cu layer 16 and TiW layer 15 are then etched away surrounding contact area 21 using composite mushroom 28 as a mask. Cu layer 16 and TiW layer 15 remain under composite mushroom 28 to increase the adherence and reduce the resistance of the connection, as illustrated in FIG. 5. A standard wet etch procedure is used in the bimetal etchback process. A commercial copper etch is used to etch back copper layer 16 and expose layer 15 of TiW. TiW layer 15 is then etched back using H2O2. Here it should be noted that etching TiW layer 15 with H2O2 is very simple because H2O2 does not attack tin but will attack silver if exposed. Since silver layer 26 is spaced from bimetal layers 15 and 16 by copper layer 25, silver layer 26 is basically not exposed.
Referring to FIG. 6, a reflow procedure is performed on composite mushroom 28 to form a bump 30. The plated wafer is soaked with a non-clean flux and is then placed in a furnace to a specific temperature profile which causes mushroom 28 to form a solder alloy and to ball into bump 30. Generally, the reflow procedure includes heating the structure to 260°C for a very short time, preferably 60 seconds. The reflow temperature profile in this preferred embodiment includes raising the temperature to a range of 245°C to 260°C with a temperature rising slope of 1.60 °C/second and lowering the temperature (once the desired temperature is achieved) with a falling slope of 2.30°C/second. Because of the very short high temperature, component reliability is not compromised.
To determine that silver and tin are inteπrixed uniformly in bump 30, an X- ray dot mapping procedure was performed for Sn and Ag. The analysis indicated that Ag is uniformly inteπriixed throughout the entire bump 30, which conclusively proves that Sn Ag alloy can be foπiied by electrochemically plating separate layers of Sn and Ag followed by a reflow. It has been found that a better result can be obtained by modifying the process to electrochemically plate a layer of Sn first on copper layer 25 followed by a layer of Ag and then another layer of Sn. The additional layer of Sn between layers 25 and 26 is electroplated in a process similar to that described above for layer 27. The thicknesses of the various layers should be adjusted to just exceed the height of photoresist layer 20 to foπri musliroom shape 28. Thus, a method of foπriing lead-free, Sn/Ag alloy, solder bumps or Sn Ag/Cu alloy, solder bumps is disclosed which is simple and inexpensive to use and which will not damage semiconductor components on a soldered wafer. The lead-free solder alloy is foπried without the need to develop a Sn/Ag alloy plating bath. Also, the lead-free solder alloy is free of alpha particle emission when used in active electronic circuits. Because the lead-free alloy is foπried by electroplating, fine pitch capability is achieved. Individual Sn and Ag baths are easy to control, making the entire process simple and applicable to achieve high yield bumping on wafers. Further, the etch back of the bimetal base is protected and simple to achieve with little or no damage to surrounding structures.
While we have shown and described specific embodiments of the present invention, further modifications and improvements will occur to those skilled in the art. We desire it to be understood, therefore, that this invention is not limited to the particular forms shown and we intend in the appended claims to cover all modifications that do not depart from the spirit and scope of this invention.

Claims

Claims
1. A method of formiiig lead-free solder bumps for semiconductor applications comprising electrochemically plating a layer of silver on a base, electrochemically plating a layer including tin on the layer of silver, and reflowrng the layer including tin and the layer of silver to foπri a solder bump.
2. A method of formiiig lead-free solder bumps for semiconductor applications as claimed in claim 1 wherein electrochemically plating the layer including tin includes electrochemically plating a tin alloy layer including one of copper and bismuth.
3. A method of forming lead-free solder bumps for semiconductor applications as claimed in claim 1 wherein electrochemically plating the layer of silver includes plating the layer of silver from a non-cyanide silver bath.
4. A method of formiiig lead-free solder bumps for semiconductor applications as claimed in claim 1 wherein electrochemically plating the layer of tin includes plating the layer of tin from a methane sulfonic acid based tin bath.
5. A method of forming lead-free solder bumps for semiconductor applications as claimed in claim 1 wherein reflowing the tin layer and silver layer to foπri the solder bump includes using a temperature profile of 245°C to 260°C for 60 seconds with a rising temperature slope of 1.60 °C/second and a falling temperature slope of 2.30°C/second.
6. A method of foπriing lead-free solder bumps for semiconductor applications as claimed in claim 1 including, in addition, providing a layer of solderable electrically conductive material and electrochemically plating the layer of silver on the layer of solderable electrically conductive material.
7. A method of foπriing lead-free solder bumps for semiconductor applications as claimed in claim 6 wherein providing the layer of solderable electrically conductive material includes sputtering a layer of titanium-tungsten (TiW) onto a surface of a semiconductor wafer and sputtering a layer of copper on the layer of titanium-tungsten (TiW).
8. A method of foπriing lead-free solder bumps for semiconductor applications as claimed in claim 7 wherein providing the layer of solderable electrically conductive material further includes electrochemically plating a layer of solderable electrically conductive material on the sputtered layer of copper.
9. A method of fomiing lead-free solder bumps for semiconductor applications as claimed in claim 8 wherein providing the layer of solderable electrically conductive material includes providing a layer including one of copper and nickel.
10. A method of forming lead-free solder bumps for semiconductor applications as claimed in claim 1 including, in additioii,electrocliemically plating a second layer of silver on the layer of tin prior to the reflowing.
PCT/US2001/004956 2000-02-23 2001-02-15 Method of forming lead-free solder alloys by electrochemical deposition process WO2001063668A2 (en)

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WO2004034460A2 (en) * 2002-10-09 2004-04-22 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder
DE102005053842A1 (en) * 2005-11-09 2007-06-14 Infineon Technologies Ag Chip components made from semiconductor wafer, include connection elements coplanar with plastic mass, for surface mounting on higher-order circuit board
WO2013032956A3 (en) * 2011-08-30 2013-09-12 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures by reflowing a first and a second metallic layer and corresponding device
US20150308007A1 (en) * 2014-04-28 2015-10-29 Samsung Electronics Co., Ltd. Tin plating solution, tin plating equipment, and method for fabricating semiconductor device using the tin plating solution

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US5316205A (en) * 1993-04-05 1994-05-31 Motorola, Inc. Method for forming gold bump connection using tin-bismuth solder
US6013572A (en) * 1997-05-27 2000-01-11 Samsung Electronics Co., Ltd. Methods of fabricating and testing silver-tin alloy solder bumps

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US4399006A (en) * 1978-08-29 1983-08-16 Learonal, Inc. Silver plating
US5316205A (en) * 1993-04-05 1994-05-31 Motorola, Inc. Method for forming gold bump connection using tin-bismuth solder
US6013572A (en) * 1997-05-27 2000-01-11 Samsung Electronics Co., Ltd. Methods of fabricating and testing silver-tin alloy solder bumps

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034460A2 (en) * 2002-10-09 2004-04-22 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder
WO2004034460A3 (en) * 2002-10-09 2004-06-03 Motorola Inc Method for eliminating voiding in plated solder
CN100342515C (en) * 2002-10-09 2007-10-10 飞思卡尔半导体公司 Method for eliminating voiding in plated solder
DE102005053842A1 (en) * 2005-11-09 2007-06-14 Infineon Technologies Ag Chip components made from semiconductor wafer, include connection elements coplanar with plastic mass, for surface mounting on higher-order circuit board
DE102005053842B4 (en) * 2005-11-09 2008-02-07 Infineon Technologies Ag Semiconductor device with connecting elements and method for producing the same
US7569427B2 (en) 2005-11-09 2009-08-04 Infineon Technologies Ag Semiconductor component with connecting elements and method for producing the same
WO2013032956A3 (en) * 2011-08-30 2013-09-12 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures by reflowing a first and a second metallic layer and corresponding device
US9142520B2 (en) 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
US9318457B2 (en) 2011-08-30 2016-04-19 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
US20150308007A1 (en) * 2014-04-28 2015-10-29 Samsung Electronics Co., Ltd. Tin plating solution, tin plating equipment, and method for fabricating semiconductor device using the tin plating solution
US9840785B2 (en) * 2014-04-28 2017-12-12 Samsung Electronics Co., Ltd. Tin plating solution, tin plating equipment, and method for fabricating semiconductor device using the tin plating solution

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