WO2001063668A3 - Method of forming lead-free solder alloys by electrochemical deposition process - Google Patents

Method of forming lead-free solder alloys by electrochemical deposition process Download PDF

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Publication number
WO2001063668A3
WO2001063668A3 PCT/US2001/004956 US0104956W WO0163668A3 WO 2001063668 A3 WO2001063668 A3 WO 2001063668A3 US 0104956 W US0104956 W US 0104956W WO 0163668 A3 WO0163668 A3 WO 0163668A3
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WO
WIPO (PCT)
Prior art keywords
layer
silver
free solder
plated
titanium
Prior art date
Application number
PCT/US2001/004956
Other languages
French (fr)
Other versions
WO2001063668A2 (en
Inventor
Jaynal Abedin Molla
William Hines Lytle
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Priority to AU2001241516A priority Critical patent/AU2001241516A1/en
Publication of WO2001063668A2 publication Critical patent/WO2001063668A2/en
Publication of WO2001063668A3 publication Critical patent/WO2001063668A3/en

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating Methods And Accessories (AREA)

Abstract

A method of forming lead-free solder bumps includes sputtering a titanium-tungsten (TiW) layer on the surface of a semiconductor wafer and a copper layer on the titanium-tungsten layer. Photoresist is used to define a contact area on the copper layer. A layer of solderable electrically conductive material is plated on the sputtered copper layer in the contact area, a layer of silver is plated on the solderable material, and a layer including tin is plated on the silver. The photoresist material is removed and, using the tin, silver, and solderable material layers as a mask, the sputtered copper and the titanium-tungsten are etched away from the surface of the wafer surrounding the contact area. The tin, silver, and solderable material layers are then reflowed to form a solder alloy bump.
PCT/US2001/004956 2000-02-23 2001-02-15 Method of forming lead-free solder alloys by electrochemical deposition process WO2001063668A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2001241516A AU2001241516A1 (en) 2000-02-23 2001-02-15 Method of forming lead-free solder alloys by electrochemical deposition process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51152500A 2000-02-23 2000-02-23
US09/511,525 2000-02-23

Publications (2)

Publication Number Publication Date
WO2001063668A2 WO2001063668A2 (en) 2001-08-30
WO2001063668A3 true WO2001063668A3 (en) 2002-02-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/004956 WO2001063668A2 (en) 2000-02-23 2001-02-15 Method of forming lead-free solder alloys by electrochemical deposition process

Country Status (2)

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AU (1) AU2001241516A1 (en)
WO (1) WO2001063668A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6780751B2 (en) * 2002-10-09 2004-08-24 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder
DE102005053842B4 (en) 2005-11-09 2008-02-07 Infineon Technologies Ag Semiconductor device with connecting elements and method for producing the same
US9142520B2 (en) * 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
KR102233334B1 (en) * 2014-04-28 2021-03-29 삼성전자주식회사 Tin plating solution, Tin plating equipment and method for fabricating semiconductor device using the tin plating solution

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4399006A (en) * 1978-08-29 1983-08-16 Learonal, Inc. Silver plating
US5316205A (en) * 1993-04-05 1994-05-31 Motorola, Inc. Method for forming gold bump connection using tin-bismuth solder
US6013572A (en) * 1997-05-27 2000-01-11 Samsung Electronics Co., Ltd. Methods of fabricating and testing silver-tin alloy solder bumps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4399006A (en) * 1978-08-29 1983-08-16 Learonal, Inc. Silver plating
US5316205A (en) * 1993-04-05 1994-05-31 Motorola, Inc. Method for forming gold bump connection using tin-bismuth solder
US6013572A (en) * 1997-05-27 2000-01-11 Samsung Electronics Co., Ltd. Methods of fabricating and testing silver-tin alloy solder bumps

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Publication number Publication date
AU2001241516A1 (en) 2001-09-03
WO2001063668A2 (en) 2001-08-30

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