KR101603859B1 - 프로세스 최적화를 위한 위상 조정 기법들 - Google Patents

프로세스 최적화를 위한 위상 조정 기법들 Download PDF

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Publication number
KR101603859B1
KR101603859B1 KR1020147016999A KR20147016999A KR101603859B1 KR 101603859 B1 KR101603859 B1 KR 101603859B1 KR 1020147016999 A KR1020147016999 A KR 1020147016999A KR 20147016999 A KR20147016999 A KR 20147016999A KR 101603859 B1 KR101603859 B1 KR 101603859B1
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KR
South Korea
Prior art keywords
layout design
test set
mask layout
mask
features
Prior art date
Application number
KR1020147016999A
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English (en)
Korean (ko)
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KR20140103977A (ko
Inventor
폴 에이. 니후스
셈 오. 오가드호
스와미나단 시바쿠마르
성태 정
Original Assignee
인텔 코포레이션
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Application filed by 인텔 코포레이션 filed Critical 인텔 코포레이션
Publication of KR20140103977A publication Critical patent/KR20140103977A/ko
Application granted granted Critical
Publication of KR101603859B1 publication Critical patent/KR101603859B1/ko

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Architecture (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
KR1020147016999A 2011-12-30 2011-12-30 프로세스 최적화를 위한 위상 조정 기법들 KR101603859B1 (ko)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/068157 WO2013101202A1 (fr) 2011-12-30 2011-12-30 Techniques d'accord de phase pour une optimisation de traitement

Publications (2)

Publication Number Publication Date
KR20140103977A KR20140103977A (ko) 2014-08-27
KR101603859B1 true KR101603859B1 (ko) 2016-03-16

Family

ID=48698434

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147016999A KR101603859B1 (ko) 2011-12-30 2011-12-30 프로세스 최적화를 위한 위상 조정 기법들

Country Status (5)

Country Link
US (1) US8959465B2 (fr)
KR (1) KR101603859B1 (fr)
CN (1) CN104025255B (fr)
TW (1) TWI615670B (fr)
WO (1) WO2013101202A1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101603859B1 (ko) 2011-12-30 2016-03-16 인텔 코포레이션 프로세스 최적화를 위한 위상 조정 기법들
US9965901B2 (en) * 2015-11-19 2018-05-08 KLA—Tencor Corp. Generating simulated images from design information
US10466586B2 (en) * 2016-11-29 2019-11-05 Taiwan Semiconductor Manufacturing Co., Ltd. Method of modeling a mask having patterns with arbitrary angles
CN108168464B (zh) * 2018-02-09 2019-12-13 东南大学 针对条纹投影三维测量系统离焦现象的相位误差校正方法
US11320742B2 (en) * 2018-10-31 2022-05-03 Taiwan Semiconductor Manufacturing Company Ltd. Method and system for generating photomask patterns
DE102019213904A1 (de) 2019-09-12 2021-03-18 Carl Zeiss Smt Gmbh Verfahren zur Erfassung einer Objektstruktur sowie Vorrichtung zur Durchführung des Verfahrens
CN110765724B (zh) * 2019-10-26 2023-04-18 东方晶源微电子科技（北京）有限公司 一种掩模优化方法及电子设备

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6902851B1 (en) 2001-03-14 2005-06-07 Advanced Micro Devices, Inc. Method for using phase-shifting mask

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3245882B2 (ja) * 1990-10-24 2002-01-15 株式会社日立製作所 パターン形成方法、および投影露光装置
JP3675421B2 (ja) 2002-03-28 2005-07-27 ソニー株式会社 マスクパターン補正方法、マスク製造方法、マスクおよび半導体装置の製造方法
US7312004B2 (en) * 2004-03-18 2007-12-25 Photronics, Inc. Embedded attenuated phase shift mask with tunable transmission
KR100594289B1 (ko) * 2004-07-23 2006-06-30 삼성전자주식회사 크롬리스 위상 반전 마스크 및 그 제조방법
US7642019B2 (en) * 2005-04-15 2010-01-05 Samsung Electronics Co., Ltd. Methods for monitoring and adjusting focus variation in a photolithographic process using test features printed from photomask test pattern images; and machine readable program storage device having instructions therefore
JP4922112B2 (ja) * 2006-09-13 2012-04-25 エーエスエムエル マスクツールズ ビー．ブイ． パターン分解フィーチャのためのモデルベースｏｐｃを行うための方法および装置
US7999920B2 (en) * 2007-08-22 2011-08-16 Asml Netherlands B.V. Method of performing model-based scanner tuning
KR101603859B1 (ko) 2011-12-30 2016-03-16 인텔 코포레이션 프로세스 최적화를 위한 위상 조정 기법들

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6902851B1 (en) 2001-03-14 2005-06-07 Advanced Micro Devices, Inc. Method for using phase-shifting mask

Also Published As

Publication number Publication date
US20140053117A1 (en) 2014-02-20
US8959465B2 (en) 2015-02-17
TWI615670B (zh) 2018-02-21
CN104025255A (zh) 2014-09-03
WO2013101202A1 (fr) 2013-07-04
CN104025255B (zh) 2016-09-07
KR20140103977A (ko) 2014-08-27
TW201348851A (zh) 2013-12-01

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