KR101525650B1 - Even- level inverter and driving method thereof - Google Patents

Abstract

The present invention relates to an even-level inverter in which switching loss of a transistor is reduced and a driving method thereof, and more particularly, to an even-number inverter and a driving method thereof. A switching unit having a plurality of switching elements for switching a voltage divided by the voltage dividing unit; A path providing unit having a bidirectional switching element for providing a path through which divided voltages are transferred between the plurality of switching elements; And a control unit for controlling the switching of the plurality of switching elements of the switching unit by modulating the input three-phase sine signal into a two-phase pulse width modulation (PWM) signal, and a driving method thereof do.

Description

EVEN-LEVEL INVERTER AND DRIVING METHOD THEREOF BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to an even-level inverter that divides an input DC power supply to an even number of voltage levels and generates an AC output signal having an even number of voltage levels by using a plurality of switching elements, and a driving method thereof.

An inverter is a circuit that receives a DC power and outputs an AC signal. It can control the size, frequency, and harmonic components of an AC signal to be output. Generally, the inverter can be divided into three levels, five levels, and the like, depending on the level (size) of the AC signal to be output, and includes a circuit for dividing the input DC power supply to a required number of levels, And a switching circuit for generating an AC output signal from the AC output signal.

In multi-level inverters such as three-level and five-level inverters, the number of transistors used in the inverter decreases as the number of levels of the inverters decreases. However, conventionally, odd-level inverters are mainly used, Even if the level is set to an even number, there is a problem that the size of the inverter is increased and the cost is increased because the level is forced to use one higher odd level.

In order to solve such a problem, an even-level inverter has been developed and used as in the prior art document. However, a conventional even-level inverter has a three-phase signal to generate an AC signal having a level such as a 2- (sine) signal to turn on / off the transistor. The transistors turn on and turn off repeatedly, resulting in a switching loss.

Korean Patent Laid-Open Publication No. 2002-0005883

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide an even-level inverter in which switching loss of a transistor is reduced and a driving method thereof.

In order to solve the above-described problems of the present invention, one technical aspect of the present invention is

A voltage divider for dividing the input DC power into an even number of voltages;

A switching unit having a plurality of switching elements for switching a voltage divided by the voltage dividing unit;

A path providing unit having a bidirectional switching element for providing a path through which divided voltages are transferred between the plurality of switching elements; And

A control unit for controlling the switching of the plurality of switching elements of the switching unit by modulating the inputted three-phase sine signal into a two-phase pulse width modulation (PWM) signal,

Level inverter including the inverter.

According to one technical aspect of the present invention,

A scale adjustment unit for adjusting a scale of the input signal with a predetermined modulation ratio;

A maximum / minimum detection unit for detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sinusoidal signal;

A calculating unit for calculating a maximum voltage value and a minimum voltage value, respectively;

A first comparison setting unit configured to compare a maximum voltage value calculated by the calculation unit with a minimum voltage value to set a reference voltage value and to calculate a set reference voltage value and a 3-phase sine signal to generate a 2-phase modulated signal;

A second comparison setting unit for comparing the level of the 2-phase modulation signal with the zero level or higher and setting the reference signal according to the comparison result; And

And a PWM signal generator for generating the two-phase PWM signal for controlling the switching of the plurality of switching elements according to the set reference signal.

According to one technical aspect of the present invention, the plurality of switching elements of the switching unit may be respectively connected to nodes outputting the divided power of the voltage dividing unit.

According to one technical aspect of the present invention, the bi-directional switch of the path providing unit may be connected to each node of the voltage dividing unit through at least one of the plurality of switching devices.

According to one technical aspect of the present invention, the voltage dividing unit may include a plurality of capacitors connected in series between input power terminals to which the input DC power is input.

According to one technical aspect of the present invention, the voltage division unit divides the input DC power supply into four voltage levels.

According to one technical aspect of the present invention, a plurality of the switching units may be provided, and the path providing unit may be provided corresponding to the plurality of switching units.

In order to solve the above-described problems of the present invention, another technical aspect of the present invention is

A scale adjusting step of adjusting a scale of a signal inputted with a modulation ratio set in advance;

A maximum / minimum detection step of detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sinusoidal signal;

An arithmetic step of calculating the detected maximum voltage value and the minimum voltage value, respectively;

A first comparison setting step of comparing a maximum voltage value calculated by the calculation unit with a minimum voltage value to set a reference voltage value, and calculating a set reference voltage value and a 3-phase sine signal to generate a 2-phase modulation signal;

A second comparison setting step of comparing the level of the two-phase modulated signal with the zero level or higher and setting the reference signal according to the comparison result; And

And a PWM signal generating step of generating the two-phase PWM signal for controlling the switching of the plurality of switching elements according to the set reference signal to drive an even-numbered inverter.

According to another technical aspect of the present invention, the scale adjustment step scales the input three-phase sinusoidal signal with a pre-set modulation ratio, scales the calculated maximum voltage value and the minimum voltage value with a different modulation ratio set in advance, Can be adjusted.

According to the present invention, the effect of reducing the switching loss of the transistors of the even-level inverters by driving the even-level inverters by performing two-phase modulation based on the sine signals of three phases when driving the transistors of the even- have.

1 is a schematic configuration diagram of an even-level inverter of the present invention;
2 is a detailed block diagram of a control unit employed in the even-level inverter of the present invention.
3 is a flow chart showing a driving method of an even-level inverter of the present invention.
4 is a waveform graph of a signal according to the flow chart of Fig.
5 to 7 are diagrams showing the detailed operation showing the inverting operation of the even-level inverter of the present invention;
8 is an even-level AC signal output from the even-level inverter of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order that those skilled in the art can easily carry out the present invention.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The same or similar reference numerals are used throughout the drawings for portions having similar functions and functions.

In addition, in the entire specification, when a part is referred to as being 'connected' with another part, it is not only a case where it is directly connected, but also a case where it is indirectly connected with another element in between do.

Also, to include an element means to include other elements, not to exclude other elements unless specifically stated otherwise.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a schematic configuration diagram of an even-level inverter of the present invention.

Referring to FIG. 1, the even-level inverter of the present invention may include a voltage divider 110, a switching unit 120, a path controller 130, and a controller 140.

The voltage divider 110 divides the input DC power supply Vdc into an even number of voltages. For this purpose, the voltage dividing unit 110 may include a plurality of capacitors connected in series between the input power source stages to which the input DC power source Vdc is input. For example, three capacitors may be serially connected between the input power terminals to divide the input DC power supply Vdc into four voltages ranging from a voltage level of '0' to a voltage level of 'Vdc' level.

The switching unit 120 may include first through fourth switching devices Q1 through Q4 and the first through fourth switching devices Q1 through Q4 may switch according to a control signal to output an AC power . The first through fourth switching devices Q1 through Q4 may be electrically connected to nodes of a plurality of capacitors of the voltage divider 110. [

In the case of a three-phase AC power source, three switching units 120 are provided so that three switching units 120 are connected to the AC power source I _A , I _B , and I _C , respectively.

Each of the switching elements Q1 to Q4 has a structure in which a transistor (N-MOS field effect transistor) and a diode are connected in parallel, and a current path through a diode or a transistor is formed according to a voltage to be transferred, The output AC signals I _A , I _B , and I _C are transferred to the output terminals through different current paths depending on the operation mode.

At this time, a current path by a DC voltage having the highest level is formed through the switching elements Q1 and Q4, and a current path by a DC voltage having an intermediate level is formed through the switching elements Q2 and Q3.

At least some of the plurality of current paths formed for voltages having four levels are formed in a path through the bi-directional switching element.

The bidirectional switching elements Qa and Qb may include at least a portion of a plurality of current paths formed for voltages having four levels Path can be formed.

In the present invention, the reversed parallel diodes are removed from the bi-directional switching device included in the path feeder 130 to form a current path, and only two transistors are connected in parallel to each other to reduce the conduction loss due to the conventional antiparallel diode .

Referring to FIG. 1, the input DC power supply Vdc is divided by Vdc / 3 into three capacitors and transmitted to the switching elements through the voltage output nodes DC LEV1 to DCV4. Here, the voltage divider 110 is shown as one input DC power supply Vdc and three capacitors C1 to C3, but is not limited thereto.

In the case of dividing the input DC power supply Vdc at an odd number of levels, an intermediate voltage output node (neutral point) which essentially outputs an intermediate level voltage is required. In a general inverter, a neutral point is connected to any one of the switching elements. However, in this embodiment, an intermediate voltage output node (neutral point) for dividing the input DC power supply Vdc at an even number of levels and outputting an intermediate level voltage may be omitted, thereby controlling the reactive power.

The control unit 140 receives PWM control signals S1 to S4 for PWM control of switching on / off of the first to fourth switching devices Q1 to Q4 by receiving a three-phase sine signal, Qa, and Qb of the current control signal Sa, Sb. The control unit 140 receives the three-phase sine signal and modulates the sine signal into a two-phase pulse width modulation (PWM) signal to switch the first to fourth switching devices Q1 to Q4 of the switching unit 120 Can be controlled.

2 is a detailed block diagram of a control unit employed in the even-level inverter of the present invention.

2, the control unit 140 includes a scale adjustment unit 141, a maximum / minimum detection unit 142, an operation unit 143, a first comparison setting unit 144, a second comparison setting unit 145, And a generating unit 146.

The scale adjustment unit 141 can adjust the signal level scale of the input signal. At this time, the scale adjusting unit 141 may adjust the signal level scale of the signal inputted with a predetermined modulation ratio, and the input signal may be a three-phase sine signal (Vabc_ref).

The maximum / minimum detection unit 142 can detect the maximum voltage value and the minimum voltage value of the scaled three-phase sine signal.

The operation unit 143 can calculate the detected maximum voltage value and the minimum voltage value, respectively, and the operation unit 143 subtracts the maximum voltage value detected at '1', adds the minimum voltage value, The minimum voltage value can be calculated, respectively. The calculated maximum voltage value and minimum voltage value can be scaled by the scale adjustment unit 141 to a previously set modulation ratio.

The first comparison setting unit 144 compares the maximum voltage value calculated by the calculation unit 143 with the minimum voltage value to set the reference voltage value and calculates the set reference voltage value and the three- Lt; / RTI >

The second comparison setting unit 145 can compare the level of the two-phase modulation signal from the first comparison setting unit 144 with the zero level or higher and set the reference signal according to the comparison result.

The PWM signal generating unit 146 generates two-phase PWM signals S1 to S4 for controlling the switching of the first to fourth switching devices Q1 to Q4 according to the reference signal set by the second comparison setting unit 145 Can be generated.

Accordingly, the control unit 140 can supply the switching unit 120 with the two-phase PWM signals S1 to S4 for controlling the switching of the first to fourth switching devices Q1 to Q4, It is possible to provide the control signals Sa and Sb capable of switching on / off the bidirectional switching elements Qa and Qb to form the current transfer path by the signals S1 to S4.

FIG. 3 is a flow chart showing a method of driving an even-numbered inverter of the present invention, and FIG. 4 is a waveform graph of a signal according to the flow chart of FIG.

Referring to FIG. 4 together with FIGS. 2 and 3, a 3-phase sine signal Vabc_ref can be input to the scale adjustment unit 141 of the even-level inverter of the present invention. Since the 3-phase sine signal Vabc_ref is 3-phase, (A) of FIG. 4, and may have a signal level of an AC power source of about 300 V or more (S1). Thus, the scale adjusting unit 141 can adjust the signal level scale of the three-phase sine signal (Vabc_ref [0,1,2]) as shown in FIG. 4B by setting the modulation ratio to 1 (Vabc_ref_m [ , 1,2]) (S2).

Then, the maximum / minimum detecting unit 142 can detect the maximum voltage value and the minimum voltage value of the scaled three-phase sine signal (S3 in FIG. 3, FIG. 4C).

Next, the operation unit 143 can calculate the detected maximum voltage value and the minimum voltage value, respectively, and the operation unit 143 subtracts the maximum voltage value detected at '1' or adds the minimum voltage value to the detected maximum value The voltage value and the minimum voltage value, respectively. The calculated maximum voltage value and the minimum voltage value can be scaled again by the scale adjustment unit 141 at a modulation ratio of 0.5 (S4 in FIG. 3 and FIG. 4 (d)).

Then, the first comparison setting unit 144 sets the reference voltage value by comparing the maximum voltage value calculated by the calculating unit 143 with the minimum voltage value (S5, S6, S7 in FIG. 3 and ), And a 2-phase modulated signal can be generated by calculating the set reference voltage value and the 3-phase sine signal (S8 in Fig. 3 and Fig. 4 (f)).

Next, the second comparison setting unit 145 compares the level of the two-phase modulated signal from the first comparison setting unit 144 with a level equal to or higher than the zero level (S9 in FIG. 3) (S10, S11 and Fig. 4 (g) in Fig. 3).

The PWM signal generator 146 generates PWM signals S 1 to S 4 for controlling the switching of the first to fourth switching elements Q 1 to Q 4 according to the reference signal set by the second comparison setting unit 145. S4) (S12, S13, S14 and Fig. 4 (h) in Fig. 3).

Figs. 5 to 7 are diagrams showing the detailed operation showing the inverting operation of the even-level inverter of the present invention.

5 to 7 are diagrams showing current paths of respective levels of the even-level inverter according to the embodiment of the present invention. 5 to 7, the path indicated by the solid line is a path through which the voltage output through the output terminal ARM _A is transmitted, and the path indicated by the broken line is the path through which the voltage output through the output terminal ARM _A Is a path of a current for generating a current. The level of the output voltage actually measured at the output terminal ARM _A can be determined depending on how many of the series connection capacitors C1 to C3 shown in the division part 110 pass the current path indicated by the broken line.

First, the operation of the inverter circuit according to the present embodiment will be described with reference to FIG. 5 for explaining the voltage level generated in the mode 1 section from the current path. When the switching element Q4 is turned on by the voltage -V _B / 2 output from the voltage divider 110 in the mode 1 section, a 0-level voltage is output as shown in FIG. 5, since the current I _A follows the path passing through only the switching element Q 4 without going through the bidirectional switching elements Qa and Qb, the current has a voltage of Vdc / 3 level, Since none of the three capacitors C1 to C3 connected in series can pass through, a 0-level voltage is output through the output terminal ARM _A.

On the other hand, when the switching element Q2 is turned on by the voltage output from the voltage divider 110 in the mode 1 section, a 1-level voltage is output as shown in FIG. That is, unlike the case where the 0-level voltage is outputted in the mode 1, a current path passing through the bidirectional switching elements Qa and Qb is formed, and the current I _A passes through the bidirectional switching elements Qa and Qb, The capacitor C3 between the DC LEV1 node and the DC LEV0 node of the transistor 110 is included in the path of the current I _A. Therefore, a voltage corresponding to the level of Vdc / 3 is outputted through the output terminal ARM _A.

6 is a diagram for explaining a current path generated in a mode 2 section and an output voltage according to the current path. 6, when the switching element Q2 is turned on by the voltage output from the voltage divider 110 in the mode 2 section, the same current as in the case of outputting the 1-level voltage shown in FIG. 5 A path is formed. 5, the current I _A passes through the current path passing through the capacitor C3 connected between the node of the DC LEV1 and the node of the DC LEV0, so that a voltage corresponding to the level of Vdc / 3 flows through the output terminal ARM _A , .

6, when the switching element Q1 is turned on by the voltage output from the voltage divider 110 in the mode 2 section, the bidirectional switching elements Qa and Qb and the turn- A current path through the element Q1 is generated. Referring to the current path shown in FIG. 6, after the current I _A input along the path shown by the dashed line reaches the voltage divider 110, the DC LEV 2 -> DC LEV 1 -> DC LEV 0 nodes are sequentially passed through the capacitor C 2 And C3. Therefore, in the case shown in Fig. 6, a voltage having a level of 2 Vdc / 3 is output to the output terminal ARM _A.

Referring to FIG. 7, the case where the switching element Q1 is turned on by the voltage output from the voltage divider 110 in the mode 3 section is similar to the case of FIG. That is, the current I _A reaching the divided portion 110 via the bidirectional switching elements Qa and Qb and the turned-on switching element Q1 is sequentially passed through the nodes of DC LEV2 -> DC LEV1 -> DC LEV0, C2 and C3. Thus, a voltage having a level of 2Vdc / 3 is transferred to the output terminal ARM _A.

7, when the switching element Q3 is turned on by the voltage V _B / 2 in the mode 3 section, the switching element Q3 is turned on without going through the bidirectional switching elements Qa and Qb The current I _A is directly transferred to the node DC LEV3 of the voltage divider 110 via only the transistor Q3. The current I _A delivered to the node DC LEV3 forms a current path passing through all of the capacitors C1 through C3 corresponding to the DC power source Vdc, so that a voltage having the level of Vdc is outputted through the output terminal ARM _A.

8 is an even-level AC signal output from the even-level inverter of the present invention.

Referring to FIG. 8, voltages having different levels are outputted in each of the modes 1 to 3, and a voltage having four different levels as a whole is output in the form of an AC waveform.

As described above, as the plurality of switching elements Q1 to Q4 and the bidirectional switching elements Qa and Qb are selectively turned on or off, the even-level inverters of Fig. 1 form different current paths do. An output voltage in the form of an AC signal having four levels (0 to 3 LEVEL in the case of FIGS. 5 to 7) is generated from the different current paths through the output terminal ARM _A. In the present invention, the bidirectional switching elements Qa and Qb are implemented without a diode, preferably with only a transistor, and the plurality of switching elements Q1 to Q4 having a neutral point outputting a mid- Of course, since it is not connected to the bidirectional switching elements Qa and Qb, the conduction loss can be reduced and the reactive power can be controlled.

As described above, according to the present invention, the effect of reducing the switching loss of the transistors of the even-level inverter by performing two-phase modulation based on the sine signal of three phases when driving the transistors of the even-level inverter have.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the particular forms disclosed. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

110 ... division unit
120 ... switching part
130 ... pathway supply
140 ... control unit
141 ... scale adjustment section
142 ... maximum / minimum detection unit
143 ... operation unit
144 ... first comparison setting section
145 ... second comparison setting section
146 ... PWM signal generating section

Claims (9)

A voltage divider for dividing the voltage level of the input DC power supply;
A switching unit having a plurality of switching elements each switching an even voltage including a divided voltage;
A path providing unit having a bidirectional switching element for providing a path through which divided voltages are transferred between the plurality of switching elements; And
Phase PWM signal according to a reference signal based on a maximum voltage value and a minimum voltage value of an input three-phase sine signal, and outputs the two-phase PWM signal to the plurality of switching units A control unit for controlling the switching of the device
Lt; th > inverter.
The apparatus of claim 1, wherein the control unit
A scale adjustment unit for adjusting a scale of the input signal with a predetermined modulation ratio;
A maximum / minimum detection unit for detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sinusoidal signal;
A calculating unit for calculating a maximum voltage value and a minimum voltage value, respectively;
A first comparison setting unit configured to compare a maximum voltage value calculated by the calculation unit with a minimum voltage value to set a reference voltage value and to calculate a set reference voltage value and a 3-phase sine signal to generate a 2-phase modulated signal;
A second comparison setting unit for comparing the level of the 2-phase modulation signal with the zero level or higher and setting the reference signal according to the comparison result; And
A PWM signal generating unit for generating the two-phase PWM signal for controlling switching of the plurality of switching elements according to the set reference signal,
Lt; th > inverter.
The method according to claim 1,
And the plurality of switching elements of the switching unit are respectively connected to nodes outputting the divided power of the voltage dividing unit.
The method of claim 3,
Wherein the bidirectional switching element of the path providing unit is connected to each node of the division unit through at least one of the plurality of switching elements.
The method according to claim 1,
Wherein the voltage division unit includes a plurality of capacitors connected in series between an input power supply terminal to which the input DC power is input.
6. The method of claim 5,
Wherein the voltage divider divides the input DC power supply into four voltage levels.
The method according to claim 1,
Wherein a plurality of the switching units are provided,
Wherein the path providing unit includes a plurality of paths corresponding to the plurality of switching units.
A scale adjusting step of adjusting a scale of a signal inputted with a modulation ratio set in advance;
A maximum / minimum detection step of detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sinusoidal signal;
An arithmetic step of calculating the detected maximum voltage value and the minimum voltage value, respectively;
A first comparison setting step of comparing a maximum voltage value calculated by the calculation unit with a minimum voltage value to set a reference voltage value, and calculating a set reference voltage value and a 3-phase sine signal to generate a 2-phase modulation signal;
A second comparison setting step of comparing the level of the two-phase modulated signal with the zero level or higher and setting the reference signal according to the comparison result; And
A PWM signal generation step of generating the 2-phase PWM signal for controlling switching of a plurality of switching elements according to the set reference signal to drive an even-
Level inverter.
9. The method of claim 8,
Wherein the scale adjustment step scales the input three-phase sinusoidal signal by a pre-set modulation ratio and scales the calculated maximum voltage value and minimum voltage value by a different modulation ratio set in advance.

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