KR20130094438A - Even- level inverter and driving method thereof - Google Patents

Abstract

PURPOSE: An even-level inverter and a driving method thereof are provided to reduce switching loss, by performing 2-phase modulation on the basis of a 3-phase sine signal. CONSTITUTION: A division part (110) divides an input direct current (DC) power into an even-number of voltages. A switching part (120) has a plurality of switching devices. The plurality of switching devices switches the divided voltage. A control part (140) modulates a 3-phase sine signal into a 2-phase pulse width modulation (PWM) signal. The control part controls switching of the switching device. [Reference numerals] (140) Control part; (AA) Three phase sine signal; (BB) PWM signal

Description

Even-Level Inverter and Its Driving Method {EVEN- LEVEL INVERTER AND DRIVING METHOD THEREOF}

The present invention relates to an even-level inverter and a driving method thereof for dividing an input DC power supply into an even voltage level and generating an AC output signal having an even voltage level using a plurality of switching elements.

The inverter is a circuit that receives a DC power and outputs an AC signal, and can control the magnitude, frequency, and harmonic components of the AC signal to be output. In general, the inverter can be classified into three-level, five-level, and the like according to the level (size) of the AC signal to be output, and a circuit for dividing the input DC power supply into the required number of levels and an input DC power supply divided into the required number of levels. And a switching circuit for generating an alternating current output signal.

In multi-level inverters such as three-level and five-level inverters, the smaller the number of inverters, the smaller the number of transistors used in the inverter, and thus the size of the inverter can be reduced. Even if the level is set to an even number, there is a problem in that the size of the inverter is increased and the cost is increased due to the use of an even higher level.

In order to solve this problem, even-level inverters have been developed and used as in the prior art literature, but conventional even-level inverters have three-phase sine to generate an AC signal having a level such as 2-level or 4-level. The transistor is turned on / off by receiving a sine signal, which causes a switching loss due to the transistor turning on and off repeatedly.

Korean Patent Publication No. 2002-0005883

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and the present invention proposes an even-level inverter and a driving method thereof in which the switching loss of the transistor is reduced.

In order to solve the above problems of the present invention, one technical aspect of the present invention

A voltage divider which divides the input DC power into an even voltage;

A switching unit having a plurality of switching elements for switching the voltage divided by the voltage dividing unit;

A path providing unit having a bidirectional switching element providing a path through which the divided voltage is transferred between the plurality of switching elements; And

Control unit for controlling the switching of the plurality of switching elements of the switching unit by modulating the input three-phase sine signal into a two-phase PWM (pulse width modulation) signal

It is to propose an even-level inverter comprising a.

According to one technical aspect of the invention, the control unit

A scale adjusting unit which adjusts a scale of an input signal at a preset modulation ratio;

A maximum / minimum detector for detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sine signal;

An operation unit for calculating the detected maximum voltage value and the minimum voltage value, respectively;

A first comparison setting unit configured to set a reference voltage value by comparing the maximum voltage value and the minimum voltage value calculated by the calculator, and generate a two-phase modulation signal by calculating a set reference voltage value and a three-phase sine signal;

A second comparison setting section for comparing whether the level of the two-phase modulation signal is equal to or greater than zero level and setting a reference signal according to the comparison result; And

It may include a PWM signal generator for generating the two-phase PWM signal for controlling the switching of the plurality of switching elements in accordance with the set reference signal.

According to one technical aspect of the present invention, the plurality of switching elements of the switching unit may be respectively connected to a node for outputting the divided power of the voltage divider.

According to one technical aspect of the present invention, the bidirectional switch of the path providing unit may be connected to each node of the voltage divider through at least one of the plurality of switching elements.

According to one technical aspect of the present invention, the voltage divider may include a plurality of capacitors connected in series between input power terminals to which the input DC power is input.

According to one technical aspect of the present invention, the voltage divider may divide the input DC power into four voltage levels.

According to one technical aspect of the present invention, the switching unit may be provided in plurality, the path providing unit corresponding to the plurality of switching unit may be provided in plurality.

In order to solve the above-described problems of the present invention, another technical aspect of the present invention is

A scale adjusting step of adjusting the scale of the input signal at a preset modulation ratio;

A maximum / minimum detection step of detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sine signal;

Calculating each of the detected maximum voltage value and minimum voltage value;

A first comparison setting step of comparing a maximum voltage value and a minimum voltage value calculated by the calculator to set a reference voltage value, and calculating a set reference voltage value and a three-phase sine signal to generate a two-phase modulation signal;

A second comparison setting step of comparing whether the level of the two-phase modulation signal is equal to or greater than zero level and setting a reference signal according to the comparison result; And

A method for driving an even level inverter including generating a PWM signal for driving an even level inverter by generating the two-phase PWM signal for controlling switching of the plurality of switching elements according to the set reference signal.

According to another technical aspect of the present invention, the scale adjustment step scales the input three-phase sine signal with a preset modulation ratio, and scales the calculated maximum voltage value and minimum voltage value with another preset modulation ratio. I can adjust it.

According to the present invention, the switching loss of the transistor of the even-level inverter is reduced by driving the even-level inverter by performing two-phase modulation based on the three-phase sine signal when driving the transistor of the even-level inverter. have.

1 is a schematic configuration diagram of an even-level inverter of the present invention.
2 is a detailed block diagram of a control unit employed in the even-level inverter of the present invention.
3 is a flow chart showing a method of driving an even-level inverter of the present invention.
4 is a waveform graph of a signal according to the flowchart of FIG. 3.
5 to 7 show detailed operations showing the inverting operation of the even-level inverter of the present invention.
8 is an even level AC signal output from an even level inverter of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The same or similar reference numerals are used throughout the drawings for portions having similar functions and functions.

In addition, in the entire specification, when a part is referred to as being 'connected' with another part, it is not only a case where it is directly connected, but also a case where it is indirectly connected with another element in between do.

Also, to include an element means to include other elements, not to exclude other elements unless specifically stated otherwise.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a schematic diagram of an even-level inverter of the present invention.

Referring to FIG. 1, the even-level inverter of the present invention may include a voltage divider 110, a switch 120, a path provider 130, and a controller 140.

The voltage dividing unit 110 may divide the input DC power supply Vdc into an even number of voltages. To this end, the voltage dividing unit 110 may include a plurality of capacitors connected in series between input power terminals to which an input DC power supply Vdc is input. For example, three capacitors may be connected in series between the input power terminals to divide the input DC power supply Vdc into four voltages from a voltage level of '0' to a voltage level of 'Vdc' level.

The switching unit 120 may include first to fourth switching elements Q1 to Q4, and the first to fourth switching elements Q1 to Q4 may switch and output AC power according to a control signal. . The first to fourth switching elements Q1 to Q4 may be electrically connected to nodes of the plurality of capacitors of the voltage divider 110.

In addition, the switching unit 120 may be provided in plural, and in the case of three-phase AC power, three switching units 120 are provided so that the three switching units 120 each have one phase AC power I _A ,. I _B , I _C ) can be output.

Each of the switching elements Q1 to Q4 has a structure in which a transistor (N-MOS field effect transistor) and a diode are connected in parallel, and a current path through the diode or the transistor is formed according to the transmitted voltage, so that each voltage having four levels and Depending on the mode of operation, the output AC signals I _A , I _B , and I _C are delivered to the output terminals through different current paths.

At this time, the current path by the DC voltage having the highest level is formed through the switching elements Q1 and Q4, and the current path by the DC voltage having the intermediate level is formed through the switching elements Q2 and Q3.

At least some of the plurality of current paths formed for voltages having four levels are formed as paths through bidirectional switching elements.

The path providing unit 130 may include bidirectional switching elements Qa and Qb, and the bidirectional switching elements Qa and Qb may communicate with at least some of the plurality of current paths formed for voltages having four levels. It can form a path.

In the present invention, by eliminating the anti-parallel diode in the bidirectional switching element included in the path providing unit 130 to form a current path, and by connecting only two transistors in parallel with each other to reduce the conduction loss due to the conventional anti-parallel diode. Can be.

Referring to FIG. 1, the input DC power supply Vdc is divided by Vdc / 3 by three capacitors, respectively, and transferred to the switching device through the voltage output nodes DC LEV1 to 4. Here, the voltage divider 110 is illustrated as one input DC power supply Vdc and three capacitors C1 to C3, but is not limited thereto.

When dividing the input DC power supply (Vdc) at odd levels, an intermediate voltage output node (neutral point) which essentially outputs a medium level voltage is required. In a typical inverter, the neutral point is connected to one of the switching elements. However, in the present application, an intermediate voltage output node (neutral point) for dividing the input DC power supply Vdc by an even number to output an intermediate level voltage may be omitted, thereby controlling reactive power.

The controller 140 receives a three-phase sine signal and PWM control signals S1 to S4 for PWM controlling switching on / off of the first to fourth switching elements Q1 to Q4, and a bidirectional switching element ( Control signals Sa and Sb for switching the current transfer paths of Qa and Qb may be provided. Herein, the control unit 140 receives a three-phase sine signal and modulates the signal into a two-phase PWM (pulse width modulation) signal to switch the first to fourth switching elements Q1 to Q4 of the switching unit 120. Can be controlled.

2 is a detailed block diagram of a control unit employed in the even-level inverter of the present invention.

Referring to FIG. 2, the controller 140 may include a scale adjusting unit 141, a maximum / minimum detection unit 142, an operation unit 143, a first comparison setting unit 144, a second comparison setting unit 145, and a PWM signal. It may include a generator 146.

The scale adjusting unit 141 may adjust the signal level scale of the input signal. In this case, the scale adjusting unit 141 may adjust the signal level scale of the input signal at a preset modulation ratio, and the input signal may be a three-phase sine signal Vabc_ref.

The maximum / minimum detector 142 may detect the maximum voltage value and the minimum voltage value of the scaled three-phase sine signal.

The operation unit 143 may calculate the detected maximum voltage value and the minimum voltage value, respectively, and the operation unit 143 may subtract the maximum voltage value detected at '1' or add the minimum voltage value to detect the maximum voltage value and the minimum voltage value. The minimum voltage value can be calculated separately. The calculated maximum voltage value and the minimum voltage value may be scaled again by the scale adjusting unit 141 at a modulation ratio preset.

The first comparison setting unit 144 compares the maximum voltage value and the minimum voltage value calculated by the operation unit 143 to set the reference voltage value, calculates the set reference voltage value and the three-phase sine signal, and performs a two-phase modulation signal. Can be generated.

The second comparison setting unit 145 may compare whether the level of the two-phase modulation signal from the first comparison setting unit 144 is equal to or greater than zero level, and set the reference signal according to the comparison result.

The PWM signal generator 146 may generate the two-phase PWM signals S1 to S4 for controlling the switching of the first to fourth switching elements Q1 to Q4 according to the reference signal set by the second comparison setting unit 145. Can be generated.

Accordingly, the controller 140 may provide the switching unit 120 with the two-phase PWM signals S1 to S4 for controlling the switching of the first to fourth switching elements Q1 to Q4. Control signals Sa and Sb for switching on / off the bidirectional switching elements Qa and Qb may be provided to form a current transfer path by the signals S1 to S4.

3 is a flowchart illustrating a method of driving an even-level inverter of the present invention, and FIG. 4 is a waveform graph of a signal according to the flowchart of FIG. 3.

Referring to FIG. 2 together with FIGS. 2 and 3, a three-phase sine signal Vabc_ref may be input to the scale controller 141 of the even-level inverter of the present invention, and Vabc_ref [0,1,2 because it is three-phase. ], As shown in FIG. 4A, may have a signal level of an AC power supply of approximately 300V or more (S1). Accordingly, the scale adjusting unit 141 may adjust the signal level scale of the three-phase sine signal Vabc_ref [0,1,2] by setting the modulation ratio to 1 as shown in FIG. 4B (Vabc_ref_m [0). , 1,2]) (S2).

Thereafter, the maximum / minimum detector 142 may detect the maximum voltage value and the minimum voltage value of the scaled three-phase sine signal (S3 of FIG. 3 and FIG. 4C).

Next, the operation unit 143 may calculate the detected maximum voltage value and the minimum voltage value, respectively, and the operation unit 143 may subtract the maximum voltage value detected at '1' or add the minimum voltage value to detect the maximum value. The voltage value and the minimum voltage value can be calculated respectively. The calculated maximum voltage value and the minimum voltage value may be scaled again by the scale adjusting unit 141 at a modulation ratio of 0.5 (S4 of FIG. 3 and (d) of FIG. 4).

Thereafter, the first comparison setting unit 144 sets the reference voltage value by comparing the maximum voltage value and the minimum voltage value calculated by the operation unit 143 (S5, S6, S7 of FIG. 3 and (e) of FIG. ), A two-phase modulated signal may be generated by calculating the set reference voltage value and the three-phase sine signal (S8 of FIG. 3 and (f) of FIG. 4).

Next, the second comparison setting unit 145 compares whether the level of the two-phase modulation signal from the first comparison setting unit 144 is equal to or greater than zero level (S9 in FIG. 3), and compares the reference signal according to the comparison result. (S10, S11 of FIG. 3, and (g) of FIG. 4).

Lastly, the PWM signal generator 146 controls the switching of the first to fourth switching elements Q1 to Q4 according to the reference signal set by the second comparison setting unit 145. S4) can be generated (S12, S13, S14 of FIG. 3 and (h) of FIG. 4).

5 to 7 are detailed diagrams illustrating the inverting operation of the even-level inverter of the present invention.

5 to 7 are diagrams showing current paths of respective levels of an even-level inverter according to an embodiment of the present invention. Hereinafter, throughout FIGS. 5 to 7, a path indicated by a solid line is a path through which an output voltage is transmitted through an output terminal ARM _A , and a current path indicated by a broken line is a voltage output through an output terminal ARM _A. This is the path of current to generate. In practice, the level of the output voltage measured at the output terminal ARM _A may be determined depending on how many of the series-connected capacitors C1 to C3 shown by the voltage divider 110 pass through the broken line.

First, the operation of the inverter circuit according to the present embodiment will be described with reference to FIG. 5 for explaining the voltage level generated in the mode 1 section from the current path. When the switching element Q4 is turned on by the voltage -V _B / 2 output from the voltage divider 110 in the mode 1 section, a 0-level voltage is output as shown in FIG. 5. Referring to the path shown in FIG. 5, since the current I _A follows the path passing only the switching element Q4 instead of the bidirectional switching elements Qa and Qb, the currents each have a voltage of Vdc / 3 level, and Since none of the three capacitors C1 through C3 connected in series passes, a 0-level voltage is output through the output terminal (ARM _A ).

On the other hand, when the switching element Q2 is turned on by the voltage output from the voltage divider 110 in the mode 1 section, as shown in FIG. 5, a 1-level voltage is output. That is, unlike in the case where the 0-level voltage is output in the mode 1, a current path through the bidirectional switching elements Qa and Qb is formed, and the current I _A passes through the bidirectional switching elements Qa and Qb. Capacitor C3 between DC LEV1 node and DC LEV0 node of 110 will be included in the path of current I _A. Therefore, a voltage corresponding to the level of Vdc / 3 is output through the output terminal ARM _A.

FIG. 6 is a diagram for describing a current path and an output voltage according to the mode 2 section. Referring to FIG. 6, when the switching element Q2 is turned on by the voltage output from the voltage divider 110 in the mode 2 section, the same current as that when the 1-level voltage shown in FIG. 5 is output. A path is formed. Accordingly, as in the case of FIG. 5, since the current I _A passes through the current path through the capacitor C3 connected between the DC LEV1 node and the DC LEV0 node, a voltage corresponding to the level of Vdc / 3 is output terminal ARM _A. Is output via

Meanwhile, referring to FIG. 6, when the switching element Q1 is turned on by the voltage output from the voltage divider 110 in the mode 2 section, the bidirectional switching elements Qa and Qb and the turned-on switching are turned on. A current path through element Q1 is generated. Referring to the current path shown in FIG. 6, after the current I _A input along the path shown by the broken line reaches the voltage divider 110, the capacitor C2 passes through the DC LEV2-> DC LEV1-> DC LEV0 nodes in order. And pass through C3. Thus, in the case shown in Fig. 6, a voltage having a level of 2Vdc / 3 is output to the output terminal ARM _A.

Referring to FIG. 7, the switching element Q1 is turned on by the voltage output from the voltage divider 110 in the mode 3 section, similar to the case of FIG. 6. That is, the current I _A reaching the voltage dividing unit 110 through the bidirectional switching elements Qa and Qb and the turned-on switching element Q1 is sequentially passed through the DC LEV2-> DC LEV1-> DC LEV0 node. Pass through C2 and C3. Thus, a voltage having a level of 2Vdc / 3 is transmitted to the output terminal ARM _A.

Finally, referring to FIG. 7, when the switching device Q3 is turned on by the voltage V _B / 2 in the mode 3 section, the switching device turned on without passing through the bidirectional switching devices Qa and Qb. The current I _A is directly transmitted to the node DC LEV3 of the voltage divider 110 only through Q3). Since the current I _A delivered to the node DC LEV3 forms a current path through all of the capacitors C1 to C3 corresponding to the DC power supply Vdc, a voltage having a level of Vdc is output through the output terminal ARM _A.

8 is an even level AC signal output from an even level inverter of the present invention.

Referring to FIG. 8, it can be seen that voltages having different levels are output in each of the modes 1 to 3 so that voltages having four different levels as a whole are output in the form of an AC waveform.

As described above, the even-level inverter of FIG. 1 forms different current paths as the plurality of switching elements Q1 to Q4 and the bidirectional switching elements Qa and Qb are selectively turned on or turned off. do. An output voltage in the form of an alternating current signal having four levels (0-3 LEVEL in FIGS. 5-7) is generated through the output terminal ARM _A from different current paths. Meanwhile, in the present invention, the bidirectional switching elements Qa and Qb are implemented without diodes, preferably only transistors, and the neutral point for outputting the intermediate level voltage from the voltage divider 110 includes a plurality of switching elements Q1 to Q4. Of course, by not connected to the bidirectional switching elements (Qa, Qb), there is an effect that can reduce the conduction loss and control the reactive power.

In addition, as described above, according to the present invention, the switching loss of the transistor of the even-level inverter is reduced by performing two-phase modulation based on the three-phase sine signal when driving the transistor of the even-level inverter. have.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not intended to limit the invention to the particular forms disclosed. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

110 ... division
120 ... switching part
130.Route Provider
140 ... control unit
141 Scale adjustment unit
142 ... max / min detector
143 ...
144 first comparison setting section
145 second comparison setting section
146 ... PWM signal generator

Claims (9)

A voltage divider which divides the input DC power into an even voltage;
A switching unit having a plurality of switching elements for switching the voltage divided by the voltage dividing unit;
A path providing unit having a bidirectional switching element providing a path through which the divided voltage is transferred between the plurality of switching elements; And
Control unit for controlling the switching of the plurality of switching elements of the switching unit by modulating the input three-phase sine signal into a two-phase PWM (pulse width modulation) signal
Even-level inverter comprising a.
The apparatus of claim 1, wherein the control unit
A scale adjusting unit which adjusts a scale of an input signal at a preset modulation ratio;
A maximum / minimum detector for detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sine signal;
An operation unit for calculating the detected maximum voltage value and the minimum voltage value, respectively;
A first comparison setting unit configured to compare the maximum voltage value and the minimum voltage value calculated by the operation unit, set a reference voltage value, and calculate a set reference voltage value and a three-phase sine signal to generate a two-phase modulation signal;
A second comparison setting section for comparing whether the level of the two-phase modulation signal is equal to or greater than zero level and setting a reference signal according to the comparison result; And
PWM signal generation unit for generating the two-phase PWM signal for controlling the switching of the plurality of switching elements in accordance with the set reference signal
Even-level inverter comprising a.
The method of claim 1,
And the plurality of switching elements of the switching unit are respectively connected to a node for outputting the divided power of the voltage dividing unit.
The method of claim 3,
And the bidirectional switching element of the path providing unit is connected to each node of the voltage divider through at least one of the plurality of switching elements.
The method of claim 1,
The voltage divider includes an even-level inverter including a plurality of capacitors connected in series between input power terminals to which the input DC power is input.
The method of claim 5,
And the voltage divider divides the input DC power into four voltage levels.
The method of claim 1,
The switching unit is provided with a plurality,
The path providing unit is an even-level inverter corresponding to a plurality of switching units.
A scale adjusting step of adjusting the scale of the input signal at a preset modulation ratio;
A maximum / minimum detection step of detecting a maximum voltage value and a minimum voltage value of the scaled three-phase sine signal;
Calculating each of the detected maximum voltage value and minimum voltage value;
A first comparison setting step of comparing a maximum voltage value and a minimum voltage value calculated by the calculator to set a reference voltage value, and calculating a set reference voltage value and a three-phase sine signal to generate a two-phase modulation signal;
A second comparison setting step of comparing whether the level of the two-phase modulation signal is equal to or greater than zero level and setting a reference signal according to the comparison result; And
PWM signal generation step of generating an even-level inverter by generating the two-phase PWM signal for controlling the switching of the plurality of switching elements in accordance with the set reference signal
Method of driving an even-level inverter comprising a.
9. The method of claim 8,
And the scaling step scales the input three-phase sine signal with a preset modulation ratio and scales the calculated maximum voltage value and minimum voltage value with another preset modulation ratio.

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