KR101451574B1 - The thin film transistor substrate and method for manufacturing the same - Google Patents

Abstract

A thin film transistor (TFT) substrate according to an embodiment of the present invention includes a gate line and a data line intersecting each other on a substrate, and a gate line and a data line formed at intersections of the gate line and the data line A TFT in which an active pattern and a gate electrode are laminated on the source / drain electrode and a first metal film pattern is formed under the source / drain electrode, a pixel electrode formed in a pixel region formed by crossing the gate line and the data line, .

Description

[0001] The present invention relates to a thin film transistor substrate and a manufacturing method thereof,

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly to a thin film transistor substrate used in a liquid crystal display device and a manufacturing method thereof.

A liquid crystal display typically displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. A liquid crystal display device is formed by a color filter substrate on which a color filter array is formed and a thin film transistor substrate on which a thin film transistor array is formed.

The thin film transistor substrate has a thin film transistor and a pixel electrode formed on the substrate for each cell region defined by the intersection of the gate line and the data line. A thin film transistor (hereinafter referred to as a TFT) supplies a data signal from a data line to a pixel electrode in response to a gate signal from a gate line. The pixel electrode formed of the transparent conductive layer supplies the data signal from the TFT to drive the liquid crystal. The liquid crystal is rotated according to the electric field formed by the data signal of the pixel electrode and the common voltage of the common electrode to control the light transmittance, thereby achieving the gradation. At this time, the common electrode may be formed at any one of the thin film transistor substrate and the color filter substrate, to which a common voltage is applied as a reference for liquid crystal driving.

The thin film transistor substrate of such a liquid crystal panel is formed through a plurality of mask processes. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a strip process, an inspection process, and the like.

However, since a large number of mask processes are required, the fabrication process is complicated, leading to a rise in manufacturing cost of the liquid crystal panel. As a result, the thin film transistor substrate has been developed to reduce the number of mask processes in the 5-mask process. For example, a conventional thin film transistor substrate manufacturing method can reduce the number of process steps by using a four-mask process by using a diffraction exposure mask. Furthermore, in recent years, by using a lift-off process, the manufacturing method of a thin film transistor substrate can be reduced to a three-mask process. Specifically, in a method of manufacturing a thin film transistor substrate using a three-mask process, a transparent conductive film is coated on a photoresist pattern for forming a contact hole, and then the transparent conductive film is patterned by removing the photoresist pattern by a lift-off method.

However, the lift-off method has a problem that a photoresist pattern may remain on the patterned transparent conductive film, thereby causing point defects.

In order to solve the above problems, the present invention provides a thin film transistor substrate and a method of manufacturing the thin film transistor substrate, which prevent the occurrence of point defects caused by using a lift-off method in a three mask process.

According to an aspect of the present invention, there is provided a thin film transistor array substrate comprising: a gate line and a data line crossing each other on a substrate; a gate electrode formed on an intersection of the gate line and the data line, A TFT in which an active pattern and a gate electrode are laminated on an upper portion of the electrode and a first metal film pattern is formed under the source / drain electrode; and a pixel electrode formed in a pixel region provided so as to cross the gate line and the data line.

A method of fabricating a thin film transistor array substrate according to an embodiment of the present invention includes sequentially forming a first metal film, a first insulating film, a second metal film, and an impurity layer on a substrate, Forming a first photoresist pattern using the first photoresist pattern; and forming a first pattern for a data line, a first pattern for a capacitor, a first pattern for a capacitor, Forming a second photoresist pattern on each of the plurality of patterns except for the first pattern for the capacitor; forming a source / drain electrode on the TFT pattern by an etching process using the second photoresist pattern; Forming an active layer, a second insulating film, and a third metal film on the substrate on which the source / drain electrodes are formed in order; Forming a first photoresist pattern on the first photoresist pattern; forming a third photoresist pattern on the first photoresist pattern using a second mask on the first photoresist pattern; A second pattern for a data line and a second pattern for a capacitor are formed, and a pattern for a gate pad and a pattern for a gate line are formed, respectively, and a part of the gate electrode pattern, Forming a gate electrode, a gate line, a data line, a storage capacitor, a gate pad, and a data pad on the gate electrode through an etching process using the fourth photoresist pattern; , A transparent conductive film is formed on the substrate, a fifth photoresist pattern is formed on the transparent conductive film using a third mask Forming a transparent conductive pattern for a pixel pad, a transparent conductive pattern for a data pad, and a transparent conductive pattern for a gate pad through an etching process using the fifth photoresist pattern.

According to the thin film transistor substrate and the method of manufacturing the same of the present invention, by performing the three mask process without using the lift-off method, it is possible to prevent the occurrence of point defects caused by using the lift- There is an effect that it can be prevented.

According to the thin film transistor substrate of the present invention and the method of manufacturing the same, the first metal film pattern 12b for TFT is formed as a light shielding film below the active pattern 20b corresponding to the channel region, (top gate staggered structure) It is possible to prevent an increase in leakage current due to photosensitivity of an active pattern generated in the TFT.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

8A and 8B are a plan view and a cross-sectional view of a thin film transistor substrate according to the present invention.

8A is a plan view showing one pixel region and a gate pad and a data pad formed on one side of the pixel region of the thin film transistor substrate according to the present invention, FIG. 8B is a cross-sectional view taken along the line I-I ' Sectional view of the data line and the storage capacitor region, a sectional view taken on line III-III ', that is, a sectional view of the gate pad region, a sectional view taken on line IV-IV' That is, it is a sectional view of the data pad region.

A gate line GL and a data line DL formed so as to intersect on a substrate 10, a TFT T as a switching element formed at each intersection thereof, And a pixel electrode 26b formed in a pixel region provided so as to cross the data line DL and the data line DL. A gate pad GP extending from the gate line GL and a data pad DP extending from the data line DP are formed.

The gate line GL is formed by sequentially stacking an active pattern 20f for a gate line, a second insulating film 22 and a third metal pattern 24f for a gate line on a substrate 10, The data line DL sequentially forms a first metal film pattern 12c for data lines, a first insulating film 14, a second metal film pattern 16c for a data line, an ohmic contact pattern for a data line 18c, a data line active pattern 20c, and a second insulating film 22 are stacked.

The TFT T is a top gate staggered structure TFT that sequentially forms a first metal film pattern 12b for a TFT, a first insulating film 14, a source / drain electrode The ohmic contact patterns 18f and 18g, the active pattern 20b, the second insulating film 22 and the gate electrode 24b are laminated. The ohmic contact patterns 18f and 18g, the active pattern 20b and the second insulating film 22 are provided with contact holes 23 for exposing the drain electrodes 16g. A part of the pixel electrode 26b contacts the drain electrode 16g through the contact hole 23 and a part of the pixel electrode 26b overlaps the storage capacitor to become an upper electrode of the storage capacitor Cst.

The storage capacitor Cst includes a first metal film pattern 12d for a capacitor which is a lower electrode, a first insulating film 14, an active pattern 20d for a capacitor, a second insulating film 22, (26b) are laminated. The active pattern 20d for the capacitor is a dielectric film of the storage capacitor Cst together with the first and second insulating films 14 and 22.

The gate pad GP sequentially forms an active pattern 20e for a gate pad, a second insulating film 22 and a third metal pattern 24e for a gate pad on the substrate 10, The data pad DP is formed by stacking a first metal film pattern 12e for a data pad, an insulating film 14, a second metal film pattern 16e for a data pad, And a transparent conductive pattern 26d for a data pad are laminated.

A method of manufacturing a thin film transistor substrate according to the present invention having such a structure will now be described with reference to FIGS. 1A and 1B to FIGS. 8A and 8B.

1A and 1B, a first metal film 12a, a first insulating film 14, a second metal film 16a and an impurity layer 18a are formed on a substrate 10, The first photoresist pattern 101 is formed on the impurity layer 18a.

The first metal film 12a and the second metal film 16a are formed of molybdenum (Mo) having a thickness of about 100 to 2000 angstroms. The thickness of the first metal film 12a and the second metal film 16a is optimally about 100 to 200 angstroms. is formed of a silicon nitride (SiNx) or silicon oxide (SiO ₂₎ approximately 850Å in thickness, and the impurity layer (18a) is formed in the impurity amorphous silicon layer.

The first photoresist pattern 101 is formed by photolithography using a first mask after forming a photoresist on the impurity layer 18a. At this time, the mask uses a diffraction exposure mask including a transmissive region through which light is entirely passed, a diffractive exposure region including a plurality of slits for transmitting a part of light and blocking a portion thereof, and a blocking region for blocking light. At this time, the diffraction exposure region is disposed in the region where the channel of the thin film transistor is to be formed and the region where the lower electrode of the storage capacitor is to be formed, and the blocking region is disposed in the region where the source / drain region, the data line and the data pad are to be formed. In addition, the thickness of the first photoresist pattern formed in the diffraction exposure region is formed to be lower than the thickness of the first photoresist pattern formed in the blocking region.

2A and 2B, a TFT pattern, a first pattern for a data line, a first pattern for a capacitor, and a pattern for a data pad are formed on a substrate 10, and the first pattern for a capacitor A second photoresist pattern 102 is formed on each of the patterns.

The TFT pattern is formed by stacking a first metal film pattern 12b for TFT, a first insulating film 14, a second metal film pattern 16b for TFT and an ohmic contact pattern 18b for TFT, 1 pattern is formed by stacking a first metal film pattern 12c for a data line, a first insulating film 14, a second metal film pattern 16c for a data line, and an ohmic contact pattern 18c for a data line, 1 pattern is formed by stacking a first metal film pattern 12d for a capacitor, a first insulating film 14, a second metal film pattern 16d for a capacitor and an ohmic contact pattern 18d for a capacitor, A first metal film pattern 12e for a pad, a first insulating film 14, a second metal film pattern 16e for a data pad, and an ohmic contact pattern 18e for a data pad are stacked.

The TFT pattern, the first pattern for the data line, the first pattern for the capacitor, and the pattern for the data pad are formed by patterning the first photoresist pattern 101 formed on the impurity layer 18a using the etching mask, Dry etching, wet etching of the second metal film 16a, and dry etching of the first insulating layer 14 and the first metal film 12a. The second photoresist pattern 102 is formed by performing an ashing process on the first photoresist pattern 101 to expose the TFT ohmic contact pattern 18b after the etch process is completed. At this time, the first photoresist pattern 101 formed on the capacitor pattern is removed to expose the ohmic contact pattern 18d for a capacitor.

Next, source / drain electrodes 16f and 16g and ohmic contact patterns 18f and 18g are formed on the substrate 10, as shown in FIGS. 3A and 3B.

The source / drain electrodes 16f and 16g and the ohmic contact patterns 18f and 18g are formed by using the second photoresist pattern 102 as the etching mask and the ohmic contact pattern 18b for TFT and the second metal film pattern 16b for TFT, Is dry-etched. At this time, the exposed second metal film pattern 16d for the capacitor as well as the ohmic contact pattern 18d for the capacitor are removed, and the first insulating film 14 is exposed. Next, the second photoresist pattern 102 is removed through an ashing process.

Next, as shown in Figs. 4A and 4B, an active layer 20a, a second insulating film 22, and a third metal film 24a are formed on the substrate 10, and the third metal film A third photoresist pattern 103 is formed on the first photoresist pattern 24a.

The third metal film 24a is formed of molybdenum (Mo), the second insulating film 22 is formed of a silicon nitride film (SiNx) or a silicon oxide film (SiO ₂ ) with a thickness of 2900-3100 angstroms, Is formed of a pure amorphous silicon layer having a thickness of about 1900 to 2100 ANGSTROM.

The third photoresist pattern 103 is formed by photolithography using a second mask after forming a photoresist on the third metal film 24a. At this time, the mask uses the diffraction exposure mask having a transmission region, a diffraction exposure region, and a blocking region. At this time, the diffraction exposure region is arranged in the region where the data line and the storage capacitor are to be formed, the region in which the contact hole exposing the drain electrode is to be formed, and the blocking region is arranged in the region where the gate line, the gate pad and the gate electrode are to be formed . In addition, the thickness of the third photoresist pattern formed in the diffraction exposure region is formed to be lower than the thickness of the third photoresist pattern formed in the blocking region.

5A and 5B, a gate electrode pattern in which a third metal pattern 24b for a gate electrode and a second insulating film 22 are laminated on a TFT pattern on a substrate 10, A second pattern for a data line in which a third metal pattern 24c for a data line and a second insulating film 22 are stacked on a first pattern for a capacitor, a third metal pattern 24d for a capacitor on a first pattern for a capacitor, A second pattern for a capacitor in which a second insulating film 22 is laminated, a pattern for a gate pad in which a third metal pattern 24e for a gate pad and a second insulating film 22 are laminated, a third metal pattern 24f for a gate line, And a second metal film 24f for a gate line and a third metal pattern 24f for a gate pad are formed on the gate insulating film 22, A fourth photoresist pattern 104 is formed on the pattern 24e.

The third metal pattern 24b and the second insulating film 22 for the gate electrode, the third metal pattern 24c and the second insulating film 22 for the data line, the third metal pattern 24d for the capacitor, The third metal pattern 24e for the gate pad and the second insulating film 22 and the third metal pattern 24f for the gate line and the second insulating film 22 are formed on the third metal layer 24a, 3 wet etching of the third metal layer 24a and dry etching of the second insulating film 22 using the photoresist pattern 103 as an etching mask. At this time, during the etching process using the third photoresist pattern, a part of the contact hole 23 for exposing the drain electrode 16g is formed in the gate electrode pattern.

After the etching process of the third metal layer 24a and the second insulating film 22 is completed, the fourth photoresist pattern 104 is partially removed from the third metal pattern 24b for the gate electrode, 3 metal pattern 24c and the third metal pattern 24d for the capacitor are exposed by performing an ashing process on the third photoresist pattern 103. [ Therefore, the fourth photoresist pattern 104 is formed only on a part of the third metal pattern 24b for the gate electrode, the third metal pattern 24f for the gate line, and the third metal pattern 24e for the gate pad.

6A and 6B, on the substrate 10, a gate electrode 24b, a data line DL, a gate line GL, a storage capacitor Cst, a gate pad GP, A pad DP is formed.

The lower electrode of the gate electrode 24b, the gate line GL, the data line DL and the storage capacitor Cst, the gate pad GP and the data pad DP are subjected to a wet etching process on the substrate 10 A portion of the third metal pattern 24b for the gate electrode, the third metal pattern 24c for the data line, and the third metal pattern 24d for the capacitor exposed due to the fourth photoresist pattern 104 are removed, The active layer 20a is dry-etched using the fourth photoresist pattern 104 as a mask to form an active pattern 20b for a gate electrode, an active pattern 20c for a data line, an active pattern 20d for a capacitor, A pattern 20e and an active pattern 20f for a gate line are formed and the fourth photoresist pattern 104 is removed by performing an ashing process. In other words, in the wet etching process, the third metal pattern 24f for the gate line, the third electrode pattern 24e for the gate pad, and the third electrode pattern 24b for the gate electrode are partially removed by the fourth photoresist pattern The third metal pattern 24c for the data line, the third metal pattern 24c for the capacitor, and the third metal pattern 24c for the data line are formed by the gate electrode 24b, the gate pad GP and the gate line GL, The data line DL and the storage capacitor Cst in which the second insulating film 22 is exposed are formed.

At this time, the storage capacitor Cst is formed by stacking the active pattern 20d for capacitors on the capacitor pattern in which the first metal film pattern 12d for the capacitor, the first insulating film 14 and the capacitor active pattern 20d, And a second insulating film 22 are stacked.

During the etching process using the fourth photoresist pattern 104, the ohmic contact pattern 18g as well as the active layer 20a exposed in the partially formed contact hole 23 are etched to complete the formation of the contact hole.

In addition, the ohmic contact pattern 18e for data pad is also removed during the dry etching of the active layer 20a.

Next, as shown in FIGS. 7A and 7B, a transparent conductive film 26 is formed on the substrate 10, and a fifth photoresist pattern 105 is formed on the transparent conductive film 26a.

The fifth photoresist pattern 105 is formed by photolithography using a third mask after forming a photoresist on the transparent conductive film 26a.

8A and 8B, a pixel electrode 26b, a transparent conductive pattern 26c for a gate pad, and a transparent conductive pattern 26d for a data pad are formed on the substrate 10, as shown in FIGS.

The pixel electrode 26b, the transparent conductive pattern 26c for the gate pad, and the transparent conductive pattern 26d for the data pad are formed by patterning the transparent conductive film 26a using the fifth photoresist pattern 105 as an etching mask. A part of the pixel electrode 26b contacts the drain electrode 16g through the contact hole 23 and a part of the pixel electrode 26b overlaps the second insulating film 22 for the storage capacitor Cst. Thus, the active pattern 20d for a capacitor stacked on the first capacitor forms a dielectric film of the storage capacitor together with the first insulating film 14 and the second insulating film 22, and the pixel electrode 26b forms an upper part of the storage capacitor Electrode.

As described above, according to the thin film transistor substrate and the method of manufacturing the same according to the present invention, by performing the 3-mask process without using the lift-off method, the point defects point defecet) can be prevented.

According to the thin film transistor substrate and the method of manufacturing the same according to the present invention, the first metal film pattern 12b for TFT is formed as a light shielding film under the active pattern 20b corresponding to the channel region, Top gate staggered structure It is possible to prevent an increase in leakage current due to photosensitivity of the active pattern generated in the TFT. In other words, in the top gate staggered structure TFT, when the light is exposed, holes and electrons are generated due to the photosensitivity of the active pattern, which causes the photocurrent to flow in the channel region even in the off state of the TFT The first metal film pattern 12b for the TFT is formed as a light shielding film under the active pattern 20b corresponding to the channel region according to the embodiment of the present invention, Top gate staggered structure It is possible to prevent an increase in leakage current due to photosensitivity of the active pattern generated in the TFT.

According to the thin film transistor substrate and the method of manufacturing the same according to the present invention, the active pattern for the capacitor together with the first and second insulating films is used as the dielectric film of the storage capacitor to have a capacity similar to that of the conventional storage capacitor.

In detail, the first insulating film 14 having a thickness of about 800 Å, the active pattern 20 d having a thickness of about 2000 Å, and the second insulating film 22 having a thickness of about 3000 Å, A surface charge is generated on each surface of the active pattern 20d due to the dielectric polarization phenomenon so that one side of the active pattern 20d in contact with the first insulating film 14 becomes the upper electrode, And the other side of the active pattern 20 in contact with the second insulating layer 22 serves as a lower electrode to form the storage capacitor with the pixel electrode 26. This allows the two capacitors to be connected in series . Therefore, the capacitance of two capacitors connected in series according to the present invention can be calculated through the following equation (1). Since the first and second insulating films are formed of a silicon nitride film, the dielectric constant epsilon of the material is 6.7 and the active pattern is formed of a pure amorphous silicon layer, the dielectric constant epsilon of the material is 11.7.

A storage capacitor formed on a conventional thin film transistor substrate has a structure in which a gate insulating film and a protective film of a silicon nitride film or a silicon nitride film are stacked between a metal film for a gate electrode and a metal film for a pixel electrode, The capacitance of the existing capacitor can be calculated through the above-described equation (1).

Thus, the ratio of the capacitance of the conventional storage capacitor and the capacitance of the storage capacitor according to the present invention calculated through Equation (1) becomes 1: 0.79. In addition, if the area of the storage capacitor of the present invention is increased by 1.27 times the area S of the existing storage capacitor, the same capacitance as the existing storage capacitor is obtained.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

FIGS. 1A and 1B to FIGS. 8A and 8B are process flow diagrams illustrating a method of manufacturing a thin film transistor substrate according to the present invention.

Claims (16)

A gate line and a data line formed so as to cross each other such that a plurality of pixel regions are defined, A TFT formed at an intersection between the gate line and the data line, A pixel electrode formed in each of the pixel regions, And a lower electrode formed to include a part disposed between the pixel electrode and the data line and overlapping at least a part of the pixel electrode, Wherein the data line is formed in a structure in which a first metal film, a first insulating film, a second metal film, and an impurity layer are sequentially stacked on a substrate, Wherein the gate line is formed by sequentially stacking an active layer, a second insulating film, and a third metal film on the substrate including the first metal film, the first insulating film, the second metal film, and the impurity layer, Wherein the pixel electrode is formed as a transparent conductive film on the substrate including the second insulating film, Wherein the lower electrode is formed of a structure in which the first metal film and the first insulating film are sequentially laminated on the substrate and is covered with the active layer and the second insulating film, And a storage capacitor formed in a region where the first metal film of the lower electrode and the pixel electrode overlap with each other with the first insulating film, the active layer and the second insulating film interposed therebetween. Board. The method according to claim 1, The TFT Source and drain electrodes overlapping the first metal film and formed of the second metal film on the first insulating film covering the first metal film, the source and drain electrodes being spaced apart from each other; An ohmic contact pattern formed on the source and drain electrodes as the impurity layer; The active layer formed on the first insulating film so as to cover the ohmic contact pattern; And a gate electrode formed of the third metal film on the second insulating film covering the active layer, Wherein the pixel electrode is connected to the drain electrode through a contact hole that penetrates the second insulating layer, the active layer, and the first insulating layer and exposes a part of the drain electrode. delete delete The method of claim 1, wherein A gate pad extending from the gate line; And a data pad extending from the data line, Wherein the gate pad is formed in a structure in which an active layer, a second insulating film, and a third metal film are sequentially stacked on the substrate including the first metal film, the first insulating film, the second metal film, and the impurity layer, And is covered with a transparent conductive pattern for a gate pad, Wherein the data pad is formed by sequentially stacking a first metal film, a first insulating film, and a second metal film on the substrate, and is covered with a transparent conductive pattern for a data pad made of the transparent conductive film. Board. Sequentially forming a first metal film, a first insulating film, a second metal film, and an impurity layer on a substrate; A first shielding region corresponding to a channel of the thin film transistor and a lower electrode of the storage capacitor, a first shielding region corresponding to the source and drain electrodes, a data line and a data pad, and a second shielding region corresponding to the first diffraction exposure region and the first shielding region. Forming a first photoresist pattern on the impurity layer using a first mask including a first transmissive region other than the first transmissive region; Patterning the first metal film, the first insulating film, the second metal film, and the impurity layer using the first photoresist pattern as a mask to pattern the source and drain electrodes, the data line, Forming a first metal film, a first insulating film, a second metal film, and an impurity layer in a stacked structure; Forming a second photoresist pattern corresponding to the source and drain electrodes, the data line, and the data pad by ashing the first photoresist pattern; Patterning the second metal film and the impurity layer in a state of using the second photoresist pattern as a mask to expose the first insulating film corresponding to a channel of the thin film transistor, Forming a first metal film and a first insulating film in a stacked structure; Removing the second photoresist pattern, and sequentially forming an active layer, a second insulating film, and a third metal film on the substrate; A second shielding region corresponding to the channel of the thin film transistor, the source and drain electrodes, the gate line and the gate pad, and a second shielding region corresponding to the source electrode and the drain electrode of the storage capacitor, Using a second mask including an area corresponding to a part of the second mask and including a second transmissive area other than the second diffraction exposure area and the second mask area, ; Patterning the second insulating film and the third metal film using the third photoresist pattern as a mask to form the gate line and the gate pad into a structure in which the second insulating film and the third metal film are stacked ; Forming a fourth photoresist pattern corresponding to the source and drain electrodes, the gate line, and the gate pad by ashing the third photoresist pattern; Patterning the active layer using the fourth photoresist pattern as a mask to form a contact hole exposing a part of the drain electrode; Removing the fourth photoresist pattern and forming a transparent conductive film on the substrate; A third masking region corresponding to the pixel electrode, the data pad, and the gate pad, and a third masking region other than the third masking region, Forming a resist pattern; And Forming a transparent conductive pattern for a data pad covering the data pad by patterning the transparent conductive film using the fifth photoresist pattern as a mask; forming a transparent conductive pattern for a data pad covering the data pad, And forming a conductive pattern on the thin film transistor substrate. delete delete The method according to claim 6, Forming a hole penetrating through the third metal film and the second insulating film in correspondence to a part of the drain electrode in the step of using the third photoresist pattern as a mask, Wherein the step of forming the contact hole exposes a part of the drain electrode through the active layer and the impurity layer following the hole in the step of using the fourth photoresist pattern as a mask . delete delete delete The method according to claim 6, In the step of using the fourth photoresist pattern as a mask, the third metal film and the impurity layer are further patterned, Further removing the third metal film on the data line, the data pad, and the lower electrode of the storage capacitor, Further removing an impurity layer of the data pad, And the third metal film between the contact hole and the pixel electrode is further removed. The method according to claim 6, In the step of using the first photoresist pattern as a mask, A lower electrode of the storage capacitor includes a part disposed between the pixel electrode and the data line, In the step of using the fifth photoresist pattern as a mask, Wherein the pixel electrode is formed to overlap with at least a part of the lower electrode of the storage capacitor, Wherein the first metal film of the lower electrode and the pixel electrode overlap each other with the first insulating film, the active layer, and the second insulating film interposed therebetween to generate the storage capacitor. Way. delete The method according to claim 6, The first metal film or the second metal film is formed of molybdenum (Mo) having a thickness of 100 to 2000 Å. The first insulating film is formed of a silicon nitride (SiNx) or silicon oxide (SiO ₂ ) film having a thickness of 750 to 850 Å, Wherein the second insulating layer is formed of a silicon nitride layer (SiNx) or a silicon oxide layer (SiO2) having a thickness of 2900 to 3100 Å, and the active layer is formed of a pure amorphous silicon layer having a thickness of 1900 to 2100 Å. Way.

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