KR101603243B1 - Method for Manufacturing Thin Film Transistor Array Substrate - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor array substrate in which the number of masks is reduced and an exposure process is reduced. The method includes forming a gate line forming portion and a data line forming portion in an intersecting direction, Preparing a substrate having a thin film transistor forming portion, a pixel region between the gate line and the data line forming portion, and a pad forming portion of each end of each of the gate line and the data line forming portion; A semiconductor layer forming layer and a data line forming metal are formed and then selectively removed using a first diffraction exposure mask process to form pad metal in the pad forming portion, data lines in the data line forming portion, gate line forming A storage electrode, a source electrode and a drain electrode spaced apart from each other in the thin film transistor forming portion, Forming a gate insulating film on the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode, and the drain electrode, and performing a second diffraction exposure mask process Etching the gate insulating film to form a pad contact hole and a pixel electrode forming hole by exposing and developing the second photoresist film using a photoresist pattern formed on the first photoresist pattern, Depositing a metal layer on the substrate including the second photoresist pattern; forming a second photoresist pattern on the substrate; And a metal layer on the second photosensitive film secondary pattern is lifted off to form a pad electrode in the pad forming portion, a pixel electrode of the pixel electrode forming hole, a gate line in the gate line forming portion, and a gate electrode in the thin film transistor forming portion, And forming a second electrode on the second electrode.

Liquid crystal display, LTPS (Low Temperature Poly Silicon), mask, diffraction exposure, lift off,

Description

[0001] The present invention relates to a method for manufacturing a thin film transistor array substrate,

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing a thin film transistor array substrate in which the number of masks is reduced and an exposure process is reduced.

BACKGROUND ART [0002] As an information society has developed, demands for display devices have increased in various forms. In response to these demands, a liquid crystal display, a plasma display panel, an electro luminescent display ) And vacuum fluorescent display (Vacuum Fluorescent Display) have been studied, and some of them have already been used as display devices in various devices.

Among them, a liquid crystal display (Liquid Crystal Display) is the most widely used as a substitute for a CRT (Cathode Ray Tube) for the purpose of a portable image display device because of its excellent image quality and light weight, thinness and low power consumption. A monitor for receiving and displaying a broadcast signal in addition to a mobile type of monitor such as a monitor of a computer, and a monitor for a computer.

In order for the liquid crystal display device to be used in various parts as a general screen display device, the key to development is how much high-quality images such as high definition, high brightness, and large area can be implemented while maintaining the features of light weight, thinness and low power consumption .

Hereinafter, a method of manufacturing a thin film transistor array substrate having a thin film transistor for driving in a conventional liquid crystal display device will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing a conventional thin film transistor array substrate.

As shown in FIG. 1, a conventional process for forming a thin film transistor array substrate is performed in the following order. .

First, a metal on the substrate 10 is deposited and selectively removed using a first mask (not shown) to form the gate electrode 11.

Next, a gate insulating film 12 is formed on the entire surface including the gate electrode 11.

Subsequently, an amorphous silicon layer 13a and an impurity layer 13b are sequentially deposited on the gate insulating film 12 and the impurity layer 13b and the amorphous silicon layer 13a (not shown) are formed by using a second mask (not shown) The semiconductor layer 13 is formed so as to cover a part of the periphery of the upper portion of the gate electrode 11.

A metal is deposited on the gate insulating film 12 including the semiconductor layer 13 and selectively removed using a third mask (not shown) (14a) and a drain electrode (14b) are formed.

The impurity layer 13b between the source electrode 14a and the drain electrode 14b is also removed through the over-etch in forming the source electrode 14a and the drain electrode 14b, .

After the protective film 15 is formed on the entire surface including the source / drain electrodes 14a / 14b, the semiconductor layer 13 and the gate insulating film 12, the protective film 15 is patterned into a fourth mask (not shown) The contact hole 25 is formed.

At this time, the contact hole 25 is formed so that the upper part of the drain electrode 14b is exposed.

A transparent electrode is deposited on the protective film 15 including the contact hole 25 and selectively removed using a fifth mask (not shown) to form the pixel electrode 26.

As described above, in the conventional liquid crystal display device, the thin film transistor array substrate is manufactured by using five masks, and processes such as coating, exposure, development, etching, and cleaning are required for each mask process. There is a problem that the yield is lowered as the number of mask processes is increased due to an error in the degree of alignment for each process.

Accordingly, efforts are being made to reduce the mask.

The method of forming the thin film transistor array of the conventional liquid crystal display device has the following problems.

In the conventional liquid crystal display device, the thin film transistor array is manufactured by using five masks, and a process such as a photoresist film coating, exposure, development, etching, and cleaning is required for each mask process. There is a problem that the yield increases as the number of mask steps increases.

Accordingly, efforts are being made to reduce the mask.

However, it is difficult to reduce the number of masks by the difference of the material layer used for each mask process and the difference in the region to be formed.

It is an object of the present invention to provide a method of manufacturing a thin film transistor array substrate in which the number of masks is reduced and the number of exposing steps is reduced.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array substrate including forming a gate line and a data line in an intersecting direction, forming a thin film transistor A pixel region between the gate line and the data line forming portion, and a pad forming portion at an end of each of the gate line and the data line forming portion, the semiconductor layer forming layer, Forming a data line, forming a data line, and selectively removing the metal line by using a first diffraction exposure mask process to form a pad metal in the pad forming portion, a data line in the data line forming portion, A source electrode and a drain electrode spaced apart from each other in the thin film transistor forming portion, Forming a gate insulating layer and a second photoresist layer over the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode, and the drain electrode; Forming a second photoresist pattern having a lower thickness between the source and drain electrodes by exposing and developing the second photoresist layer to remove the pad forming portion and the pixel region; Etching the gate insulating layer to form a pad contact hole and a pixel electrode forming hole, and performing ashing to a degree that low thickness between the source / drain electrodes of the second photoresist pattern is removed, Depositing a metal layer on the substrate including the second photoresist film secondary pattern; And a metal layer on the second photosensitive film secondary pattern is lifted off to form a pad electrode in the pad forming portion, a pixel electrode of the pixel electrode forming hole, a gate line in the gate line forming portion, and a gate electrode in the thin film transistor forming portion, And a step of forming the second electrode layer.

The step of using the first diffractive exposure mask step includes sequentially forming a first photosensitive film on the data line forming metal, and a step of forming the first photosensitive film by exposure and development using a first diffractive exposure mask A first photoresist pattern having a relatively thick thickness corresponding to a channel portion of the thin film transistor and having a relatively thick thickness with respect to the pad forming portion, the data line forming portion, and the gate line forming portion, Forming data line forming metal and semiconductor layer forming layer by using the first photoresist pattern, forming a pad metal in the pad forming portion, a data line in the data line forming portion, Forming a data line forming metal in the thin film transistor forming portion and a semiconductor layer on the lower portion; Forming a first photosensitive film pattern by ashing the second photosensitive film pattern, so the first to be removed every one of the low thickness corresponding to the channel portion of the thin film transistor group; And forming a semiconductor layer in the thin film transistor forming portion by removing the data line forming metal from the channel portion of the thin film transistor exposed using the first photoresist film secondary pattern to form source and drain electrodes spaced apart from each other, ; ≪ / RTI >

At this time, the first diffraction exposure mask has a transflective portion corresponding to the channel portion of the thin film transistor, and has a shielding portion for the pad formation portion, the data line formation portion, and the gate line formation portion.

The second diffraction exposure mask has a transflective portion corresponding to the channel portion and the gate line formation portion of the thin film transistor and may have a light shielding portion with respect to the pad formation portion and the pixel region.

In order to achieve the same object, a method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a gate line forming portion and a data line forming portion in a direction intersecting each other; forming a thin film transistor A pixel region between the gate line and the data line forming portion, and a pad forming portion at an end of each of the gate line and the data line forming portion, the semiconductor layer forming layer, Forming a data line, forming a data line, and selectively removing the metal line by using a first diffraction exposure mask process to form a pad metal in the pad forming portion, a data line in the data line forming portion, A source electrode and a drain electrode spaced apart from each other in the thin film transistor forming portion, Forming a gate insulating layer on the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode, and the drain electrode, removing the gate insulating layer from the pad forming portion to form a pad contact hole Depositing a transparent electrode and a gate line forming metal on the gate insulating film including the pad contact hole and selectively removing the transparent electrode and the gate line forming metal using a second diffraction exposure mask process, And forming a gate electrode in the gate line and a gate electrode in the thin film transistor forming portion. The method of manufacturing a semiconductor device according to the present invention includes the steps of:

Wherein the step of using the second diffraction exposure mask step includes sequentially forming a second photoresist layer on the gate line forming metal on the gate insulating layer including the pad contact hole, And a gate electrode formed on the gate electrode and the source electrode and the drain electrode in the gate line forming portion and the thin film transistor forming portion and having a relatively large thickness corresponding to a region between the source electrode and the drain electrode in the gate line forming portion and the thin film transistor forming portion, Forming a second photoresist pattern having a predetermined thickness and having a thickness that is different from that of the first photoresist pattern and removing the gate line forming metal and the transparent electrode using the second photoresist pattern; Forming a gate electrode in the thin film transistor forming portion; Comprising the steps of such an extent that to remove all the ashing the second photosensitive film pattern to form a second photosensitive film secondary pattern; And forming the pad electrode and the pixel electrode by removing the gate line forming metal of the pixel region and the pad forming unit exposed using the second photoresist pattern.

Here, the second diffraction exposure mask may have a light shielding portion corresponding to a region between the source electrode and the drain electrode of the channel portion of the gate line and the thin film transistor, and has semi-transmission corresponding to the pad forming portion and the pixel region.

Forming a shielding layer corresponding to the gate line forming portion, the data line forming portion, the thin film transistor forming portion, and the pad forming portion after the step of preparing the substrate; And forming a buffer layer on the substrate including the shielding layer.

In this case, the shielding layer and the buffer layer are patterned together by the first diffractive exposure mask process.

In order to achieve the same object, a method of manufacturing a thin film transistor array substrate according to the present invention includes: forming a gate line forming portion and a data line forming portion in a direction intersecting each other; forming a thin film transistor Forming a gate electrode, a pixel region between the gate line and the data line forming portion, and a pad defining portion of an end of each of the gate line and the data line forming portion, the shielding layer forming metal And forming a buffer layer, a semiconductor layer forming layer, and a data line forming metal, and then selectively removing them using a first diffraction exposure mask process to form pad metal in the pad forming portion, a data line in the data line forming portion, A storage electrode is formed in the gate line forming portion, a source electrode is formed in the thin film transistor forming portion, A gate electrode, a drain electrode, and a semiconductor layer, a buffer layer, and a shielding layer below the gate electrode, a data line, a storage electrode, a source electrode, and a drain electrode, The second photoresist layer is exposed and developed by using a second diffraction exposure mask to remove the pad formation portion and the pixel region, and a second photoresist pattern having a low thickness corresponding to the space between the source / Forming a pixel contact hole and a pixel electrode forming hole by etching the gate insulating film using the second photoresist pattern; forming a second photoresist pattern on the source / drain electrode of the second photoresist pattern, Forming a second photosensitive film secondary pattern by advancing the ashing to such an extent that a low thickness between the first and second photosensitive film secondary patterns is removed; Depositing a metal layer on the plate; And a metal layer on the second photosensitive film secondary pattern is lifted off to form a pad electrode in the pad forming portion, a pixel electrode of the pixel electrode forming hole, a gate line in the gate line forming portion, and a gate electrode in the thin film transistor forming portion, Thereby forming the second electrode.

The method of manufacturing a thin film transistor array substrate of the present invention has the following effects.

First, a thin film transistor array can be formed by a two-mask process while a thin film transistor array is formed by a conventional five-mask process. For example, it takes at least five steps such as photoresist application, exposure, development, stripping, and cleaning per mask process, which can have a minimum step reduction of at least 15 steps. Thus, with the reduction in the number of masks, the process time is reduced and the process cost is reduced.

Second, in the case of the structure having the shielding layer at the bottom, even if the shielding layer is formed on the thin film transistor substrate side with a separate mask, in this case, the black matrix layer on the color filter array substrate can be omitted, In view of the liquid crystal panel in which the substrate and the color filter array substrate are bonded together, the three mask reduction effect can be common.

Thirdly, in forming the shielding layer, it is possible to simultaneously form the source / drain electrode and the semiconductor layer in the state of having a buffer layer therebetween without patterning the same with a separate mask, Substrate fabrication is possible.

Fourth, the yield is ultimately improved according to the mask reduction effect described above.

Fifth, in the case of other low mask processes, development difficulty is high, but it is possible to simplify the low mask process by changing the process.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a thin film transistor array substrate of the present invention.

2, a thin film transistor array substrate according to the present invention includes a substrate 100, a gate line 101 (G-line) and a data line 102 (D-line) A pixel electrode 111c located between the gate line 101 and the data line 102 and electrically connected to the thin film transistor TFT is formed at a crossing portion of the data line 102 and the data line 102, PXL).

The thin film transistor TFT includes a gate electrode 101a protruded from the gate line 101 and a source electrode 102a and a drain electrode 102b on both sides of the gate electrode 101a, (Not shown in Fig. 2, refer to 110 in Fig. 3A) that is in contact with both the source electrode 102a and the drain electrode 102b.

A gate pad (G-PAD) is disposed at one end of the gate line 101. A data pad (D-PAD) is disposed at one end of the data line 102, (drive-IC) (not shown).

The pixel electrode 111c is formed of the same layer metal as the gate line 101. [

The storage electrode pattern 122a overlaps with the gate line 101 and is formed on the same layer as the data line 102 to form a storage capacitor Cst in the overlapped portion. In this case, the storage electrode pattern 122a may be formed to be in electrical contact with the pixel electrode 111c or protrude from the data line 102 integrally with the data line 102.

* First Embodiment *

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

A method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention will now be described with reference to FIG. 2, including a gate pad G-PAD, a data pad D-PAD, a data line D- ), A pixel electrode (PXL) 111c, a gate line (G-line) 101 (Cst), and a thin film transistor (TFT) formation region.

First, as shown in FIG. 3A, a semiconductor layer is continuously deposited on a substrate 100 by using a first diffraction exposure mask (not shown), then a data line forming metal is deposited and then selectively removed A gate pad metal 122b is formed in the gate pad forming portion, a data pad metal 112 is formed in the data pad forming portion, a data line 102 is formed in the data line forming portion, a storage electrode pattern 122a is formed in the gate line forming portion, 102a and a drain electrode 102b are formed. At this time, a semiconductor layer 120d (not shown) is formed under each of the gate pad metal 122b, the data pad metal 112, the data line 102, the storage electrode pattern 122a, the source electrode 102a and the drain electrode 102b. , 120c, 120b, 120a, and 110 are formed.

Here, the semitransmissive portions of the first diffraction exposure mask are patterned to correspond to the source / drain electrodes 102a / 102b, and the semiconductor layer 110 remains, and this region is defined as a channel region.

More specifically, an amorphous silicon layer, an impurity layer (including a semiconductor layer including an amorphous silicon layer and an impurity layer) and a data line forming metal are sequentially deposited, and then a first photoresist layer (not shown) is coated on the amorphous silicon layer .

A transflective portion corresponds to the channel region of the thin film transistor, and a first diffraction exposure mask (not shown) having a shielding portion corresponding to a channel region of the thin film transistor and a transmissive portion corresponding to a portion where the pattern is removed is used After the exposure is performed, the photoresist film is developed and patterned. When a photosensitive film having such a difference in exposure amount is developed by such exposure and development, the photosensitive film is removed from the portion corresponding to the transmissive portion, the portion corresponding to the light-shielding portion remains, The first portion of the photosensitive film pattern is formed with a certain thickness.

The data line forming metal, the impurity layer, and the amorphous silicon layer are etched using the first photoresist pattern as a mask, thereby forming the gate pad metal (the first semiconductor layer 120d, 120c, 120b, 120a) A data line metal layer 112, a storage electrode pattern 122a, an impurity layer and a data line forming metal layer 102a and 102b corresponding to the thin film transistor forming region, an amorphous silicon layer 122b, A laminated pattern of the first layer remains.

In this case, although the semiconductor layers 120d, 120c, 120b and 120a are not separately shown, an amorphous silicon layer and an impurity layer are laminated from the bottom.

Next, a first photoresist pattern (not shown) is formed by applying an ashing process to the first photoresist pattern to remove the remaining first photoresist pattern corresponding to the transflective portion.

Then, the data line forming metal corresponding to the exposed transflective portion is removed, and the exposed impurity layer is removed to form the semiconductor layer 110 having the source / drain electrodes 102a and 102b and the channel region below the source / . The channel region corresponds to the amorphous silicon layer in the region from which the impurity layer is removed.

Meanwhile, when the first photoresist layer is a negative photoresist layer, the shape of the first diffraction exposure mask is such that the transmissive portion and the light-shielding portion are formed in the above-described manner .

As shown in FIG. 3B, the gate pad metal 122b, the data pad metal 112, the data line 102, the storage electrode pattern 122a, the source / drain electrodes 102a / 102b, The gate insulating film 130 is deposited on the substrate 100 including the first photoresist pattern 140 and then the second photoresist film is coated and then the second photoresist pattern 140 ).

In this case, the transmissive portion of the second diffraction exposure mask is defined corresponding to the gate pad metal 122b, the data pad metal 112, and the pixel electrode formation portion, and the transflective portion is defined by the source of the thin film transistor forming portion / Drain electrodes 102a / 102b and on the storage electrode pattern 122a. In this case, the transflective portion can partially overlap with the source / drain electrodes 102a / 102b.

Therefore, after development of the second photoresist film, the second photoresist pattern 140 is removed corresponding to the transmissive portion, and the portion corresponding to the transflective portion is patterned to remain a part of the thickness.

As shown in FIG. 3C, the gate insulating layer 130 is etched using the second photoresist pattern 140 as a mask to form a pixel electrode defining hole 150a in the pixel electrode forming portion, And a gate pad contact hole 150b and a data pad contact hole 150c are formed in the gate electrode portion and the data pad contact hole 150c, respectively.

As shown in FIG. 3D, the second photoresist pattern 140 partially remaining in thickness corresponding to the transflective portion is ashed and removed. In this process, the thickness of the second photoresist pattern 140 in the remaining regions corresponding to the remaining light-shielding portions is also partially removed to form the second photoresist film secondary pattern 140a.

 Next, a metal layer 160 is deposited on the entire surface of the substrate 100 including the second photoresist film secondary pattern 140a.

In this process, the metal layer 160 is formed in the gate pad contact hole 150b, the data pad contact hole 150c, and the pixel electrode defining hole 150a together with the upper portion of the second photoresist pattern 140a. And remains on the exposed gate insulating film 130.

Next, as shown in FIG. 3E, the second photoresist pattern 140a and the upper metal layer 160 are lifted off by using a photoresist stripper.

The metal layer remaining on the gate pad metal 122b is connected to the gate pad electrode 111a while the metal layer remaining on the data pad metal 112 is connected to the data pad electrode 111b, The remaining metal layer is a pixel electrode 111c, the metal layer remaining on the storage electrode pattern 122a is a gate line 101, and the metal layer formed over the source electrode 102a to the drain electrode 102b is a gate electrode 101a ).

The configuration of FIG. 3E corresponds to the above-described plane configuration of FIG.

Through such a process, the thin film transistor array can be formed into a two-mask process. In this case, the total number of masks is reduced compared to the conventional structure, and the number of steps can be reduced from at least 12 steps to as many as 30 steps, considering at least four steps in each mask process.

In addition, by reducing the mask, the improvement of the yield can be expected with the reduction of the process time and the process cost.

In this case, the metal layer 160 may be formed of a transparent electrode, or may be formed as a reflective electrode, depending on the case. And the thin film transistor array may be implemented in a reflection mode.

Alternatively, the pixel electrode made of the metal layer may be provided in only a part of the region where the gate line and the data line intersect, and the remaining region may be made transparent so as to increase the transparency.

* Second Embodiment *

4A to 4C are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

The method of manufacturing the thin film transistor array substrate according to the second embodiment of the present invention follows the procedure of the first diffractive exposure mask process of the first embodiment described above, as shown in FIG. 4A.

4A, the amorphous silicon layer and the semiconductor layers 210, 220a, 220b, 220c, and 220d of the impurity layer are sequentially deposited on the substrate 200 by using a first diffraction exposure mask A gate pad metal 222b is formed on the gate pad forming portion, a data pad metal 212 is formed on the data pad forming portion 212, a data pad 212 is formed on the data pad forming portion 222, A storage electrode pattern 222a, a source electrode 202a, and a drain electrode 202b are formed in the gate line forming portion. A semiconductor layer 220d is formed below each of the gate pad metal 222b, the data pad metal 212, the data line 202, the storage electrode pattern 222a, the source electrode 202a and the drain electrode 202b. , 220c, 220b, 220a, and 210 are formed.

In this case, the semitransmissive portions of the first diffraction exposure mask are patterned to correspond to the source / drain electrodes 202a / 202b, so that the data line forming metal constituting the source / drain electrodes 202a / 202b is removed, Layer 210 remains, which is defined as the channel region.

As shown in FIG. 4B, on the substrate 200 including the gate pad metal 222b, the data pad metal 212, the data line 202, the storage electrode pattern 222a, the source / drain electrodes 202a and 202b, A gate insulating layer 230 is deposited and a photoresist layer (not shown) is applied to the gate pad portion and the data pad portion to expose and develop the photoresist pattern using a mask having a transparent portion corresponding to the gate pad portion and the data pad portion . Then, the gate insulating layer of the gate pad portion and the data pad portion exposed using the photoresist pattern is etched to form a gate pad contact hole 230a and a data pad contact hole 230b.

As shown in FIG. 4C, on the gate insulating layer 230 including the gate pad contact hole 230a and the data pad contact hole 230b, the pixel electrode forming metal layers 240a, 240b, 240c, 240d, and 240e, And the line-forming metal (the same layer as 250 and 250a) is continuously deposited.

Next, a photoresist film (not shown) is coated on the gate line forming metal, and a photoresist pattern (not shown) is formed by performing an exposure and a development process using a second diffraction exposure mask (not shown).

In the second diffraction exposure mask, a transflective portion is defined corresponding to the gate pad portion, the data pad portion, and the pixel electrode formation portion. A light shielding portion is defined corresponding to the gate line formation portion and the gate electrode formation portion, . In this case, the photoresist layer may be formed using a photoresistive photosensitive material. If a negative photosensitive material is used, the transmissive portion and the light-shielding portion of the second diffraction exposure mask may be reversed.

Accordingly, after the development of the photoresist film, the photoresist pattern corresponding to the gate pad portion, the data pad portion, and the pixel electrode formation portion is left with a certain thickness due to the difference in exposure amount by the second diffraction exposure mask, A portion of the photoresist pattern corresponding to the portion where the gate electrode is formed is entirely coated with the photoresist pattern, and the photoresist pattern is removed in the remaining regions.

Then, using the photoresist pattern as a mask, the gate line forming metal and the pixel electrode forming metal of the exposed portion are etched so that only the gate pad portion, the data pad portion, the pixel electrode forming portion, the gate line forming portion, It leaves. In this process, a gate line is formed in the gate line forming portion by stacking the gate line forming metal and the pixel electrode forming metal, and a gate electrode formed integrally with the gate line is formed in the gate electrode forming portion.

Then, in order to expose the gate line forming metal in the pad portion and the pixel electrode forming portion where the photoresist pattern is partially thickened, an ashing process is performed to remove the thickness.

In this case, the exposed gate line forming metal is etched and removed in the pad portion (the gate pad portion and the data pad portion) and the pixel electrode forming portion.

Next, the photoresist pattern is stripped and removed.

As described above, in the method of manufacturing a thin film transistor array substrate according to the second embodiment of the present invention described above, the thin film transistor array is manufactured using three masks. In this case, as compared with the two mask process of the first embodiment, And a transparent electrode is provided on the pixel electrode. In the case of implementing the transmission mode, the second embodiment described above can be implemented while reducing the mask.

* Third Embodiment *

5A to 5E are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a third embodiment of the present invention.

The manufacturing method of the thin film transistor array substrate according to the third embodiment described below is different from the first embodiment in that a shielding layer is formed under the semiconductor layers 320a, 320b, 320c, 320d, 301a, 301b, 301c, 301d, and 301e are formed. That is, the forming process after the shielding layer is the same, and a detailed description thereof will be omitted.

The reason why the shielding layers 301a, 301b, 301c, 301d and 301e are provided is that when light is transmitted to the semiconductor layers 320a, 320b, 320c, 320d and 320 by the backlight unit This is to prevent the photocurrent that can be generated.

First, as shown in FIG. 5A, a metal layer is deposited on a substrate 300, a first photoresist layer (not shown) is coated on the metal layer, and then the first photoresist layer is exposed and developed (D-PAD), a data line forming portion (D-line), a gate line forming portion (D-line), and the like are formed on the gate insulating layer by etching the metal layer using the patterned first photoresist layer. Shielding layers 301c, 301d, 301b, 301a, and 301e are formed in the G-line Cst and the TFT, respectively.

Next, a buffer layer 310 is formed on the substrate 300 including the shielding layers 301c, 301d, 301b, 301a, and 301e.

Subsequently, a semiconductor layer 320c, 320d, 320b, 320a, and 320 made of an amorphous silicon layer and an impurity layer are sequentially deposited using a first diffraction exposure mask (not shown), and then a data line forming metal A gate pad metal 332c is formed in the gate pad forming portion and a data pad metal 332d is formed in the data pad forming portion 332c. A data line 332b is formed in the data line formation portion, a storage electrode pattern 332a, a source electrode 322a, and a drain electrode 322b are formed in the gate line formation portion. At this time, a semiconductor layer 320c (not shown) is formed under each of the gate pad metal 332c, the data pad metal 332d, the data line 332b, the storage electrode pattern 332a, the source electrode 322a and the drain electrode 322b. , 320d, 320b, 320a, and 320 are formed.

Here, the semitransmissive portions of the first diffraction exposure mask are patterned corresponding to the source / drain electrodes 322a / 322b, so that the semiconductor layer 320 remains, and this region is defined as a channel region.

More specifically, an amorphous silicon layer, an impurity layer (including a semiconductor layer including an amorphous silicon layer and an impurity layer) and a data line forming metal are sequentially deposited, and then a second photoresist layer (not shown) is coated on the amorphous silicon layer, the impurity layer .

A transflective portion corresponds to the channel region of the thin film transistor, and a first diffraction exposure mask (not shown) having a light shielding portion corresponding to a channel region of the thin film transistor and a transmissive portion corresponding to a portion where the pattern is removed is used After the exposure is performed, the photoresist film is developed and patterned. When a photosensitive film having such a difference in exposure amount is developed by such exposure and development, the photosensitive film is removed from the portion corresponding to the transmissive portion, the portion corresponding to the light-shielding portion remains, The second portion of the photosensitive film pattern is formed with a certain thickness.

The data line forming metal, the impurity layer and the amorphous silicon layer are etched using the second photoresist pattern as a mask so that the gate pad metal (the first semiconductor layer 320a, the second semiconductor layer 320c, the second semiconductor layer 320b, A data line metal 332d, a data line 332b, a storage electrode pattern 332a, an impurity layer and a data line forming metal 322a and 322b corresponding to the thin film transistor forming region, an amorphous silicon layer 332b, A laminated pattern of the first layer remains.

In this case, although the semiconductor layers 320c, 320d, 320b, 320a, and 320 are not shown separately, an amorphous silicon layer and an impurity layer are laminated from the bottom.

Next, a first photoresist pattern (not shown) is formed by applying an ashing process to the first photoresist pattern to remove the remaining first photoresist pattern corresponding to the transflective portion.

Then, the data line forming metal corresponding to the exposed transflective portion is removed, and the exposed impurity layer is removed to expose the semiconductor layer 320 having the source / drain electrodes 322a and 322b and the channel region below the source / drain electrodes 322a and 322b . The channel region corresponds to the amorphous silicon layer in the region from which the impurity layer is removed.

Meanwhile, when the first photoresist layer is a negative photoresist layer, the shape of the first diffraction exposure mask is such that the transmissive portion and the light-shielding portion are formed in the above-described manner .

5B, the gate pad metal 332c, the data pad metal 332d, the data line 332b, the storage electrode pattern 332a, the source / drain electrodes 322a / 322b, A third insulating film 340 is deposited on the substrate 300 including the first photoresist pattern 340 and then the third photoresist pattern 350 is coated with the second photoresist pattern 350 by using the second diffraction exposure mask ).

In this case, the transmissive portion of the second diffraction exposure mask is defined corresponding to the gate pad metal 332c, the data pad metal 332d, and the pixel electrode formation portion, and the transflective portion is defined by the source / Drain electrodes 322a / 322b, and on the storage electrode pattern 332a. In this case, the transflective portion can partially overlap with the source / drain electrodes 322a / 322b.

Therefore, after development of the third photosensitive film, the third photosensitive film pattern 350 is removed corresponding to the transmissive portion, and the portion corresponding to the transflective portion is patterned to remain a part of the thickness.

5C, the gate insulating layer 340 is etched using the third photoresist pattern 350 as a mask to form gate pad contact holes 345a and data pad contact holes 345b And a pixel electrode defining hole 345c is formed in the pixel electrode forming portion.

As shown in FIG. 5D, the third photoresist pattern 350 partially remaining in thickness corresponding to the transflective portion is ashed and removed. In this process, the thickness of the third photoresist pattern 350 in the remaining region corresponding to the remaining light-shielding portions is also partially removed to form the second photoresist film secondary pattern 350a.

 Next, a metal layer 360 is deposited on the entire surface of the substrate 300 including the third photoresist film secondary pattern 350a.

In this process, the metal layer 360 is formed in the gate pad contact hole 345a, the data pad contact hole 345b, and the pixel electrode defining hole 345c together with the upper portion of the third photosensitive-film secondary pattern 350a. And remains on the exposed gate insulating film 340.

Next, as shown in FIG. 5E, the third photoresist pattern 350a and the metal layer 360 thereon are lifted off by using a photoresist stripper.

The metal layer remaining on the gate pad metal 332c is connected to the gate pad electrode 361c while the metal layer remaining on the data pad metal 332d is connected to the data pad electrode 361d, The metal layer formed over the source electrode 322a to the drain electrode 322b is electrically connected to the gate electrode 361a through the pixel electrode 361b, the metal layer remaining on the storage electrode pattern 332a, ).

The shielding layers 301a, 301b, 301c, 301d, and 301e may replace the functions of the black matrix layer of the color filter array substrate facing the TFT array substrate. In the third embodiment, When the color filter array substrate in which the black matrix layer of the black matrix layer on the array substrate side is removed and the thin film transistor array substrate manufactured in the third embodiment described above are attached together, The same effects as those obtained can be obtained.

In addition, since the black matrix layer is substituted for the shielding layer on the side of the thin film transistor array substrate, the black matrix layer on the side of the color filter array substrate can be omitted, the cohesion margin can be reduced, It is feasible.

* Fourth Embodiment *

6A to 6K are cross-sectional views illustrating a method of manufacturing a thin film transistor array substrate according to a fourth embodiment of the present invention.

In the fourth embodiment described below, the shielding layer 401a is etched to the same width as the semiconductor layers 403a of the respective regions, as compared with the first embodiment, .

First, as shown in FIG. 6A, a shielding forming metal 401, a buffer layer 402, a semiconductor layer 403 in which an amorphous silicon layer and an impurity layer are continuously deposited, and a data line shaped metal 404 ).

6B, a first photoresist layer is coated on the data line forming metal layer 404, and then the first photoresist layer is exposed and developed using a first diffraction exposure mask (not shown) Pattern 410 is formed.

In the first diffraction exposure mask, a transflective portion corresponds to a channel region of the thin film transistor (TFT), and the remaining pattern forming portions (a gate pad forming portion, a data pad forming portion, a data line forming portion, a gate line forming portion, Film transistor forming portion excluding the channel) has a shape corresponding to a shielding portion and a portion where a pattern is removed corresponds to a transmitting portion.

The first photoresist pattern 410 remains thin to correspond to the channel region of the thin film transistor and the remaining thin film except for the gate pad forming portion, the data pad forming portion, the data line forming portion, the gate line forming portion, The transistor forming portion is left with a relatively thick thickness, and the other region is removed.

6C, the data line forming metal 404 and the impurity layer, the semiconductor layer 403 of the amorphous silicon layer, the buffer layer 402, and the shielding metal layer 403 are formed using the first photoresist pattern 410 as a mask. The data line forming portion, the data line forming portion, the gate line forming portion, and the thin film transistor forming portion are sequentially removed from the top to form the data line forming metal The semiconductor layers 403a, the buffer layer 402a, and the shielding forming metal 401a of the impurity layer, the amorphous silicon layer remain. The data line forming metal 414a is defined as a gate pad metal, a data pad metal, a data line, and a storage electrode pattern in the gate pad forming portion, the data pad forming portion, the data line forming portion, and the gate line forming portion, respectively. do. The data line forming metal 404a remaining in the thin film transistor (TFT) forming portion is divided into a source electrode and a drain electrode through a subsequent process.

Then, as shown in FIG. 6D, an ashing process is applied to the first photoresist pattern to remove the first photoresist pattern 410 remaining in the channel region, thereby forming a first photoresist pattern 410a.

Then, the data line forming metal 404a corresponding to the exposed transflective portion is removed and the exposed portion of the impurity layer 403a is removed to form the source / drain electrodes 412a and 412b and the channel A semiconductor layer 405 having a region is formed. The channel region corresponds to the amorphous silicon layer in the region from which the impurity layer is removed.

Meanwhile, when the first photoresist layer is a negative photoresist layer, the shape of the first diffraction exposure mask is such that the transmissive portion and the light-shielding portion are formed in the above-described manner .

Next, as shown in FIG. 6E, the first photoresist film secondary pattern 410a is removed.

The gate insulating layer 420 is deposited on the substrate 400 including the gate pad metal, the data pad metal, the data line, the storage electrode pattern 414a, the source / drain electrodes 412a / 412b, .

Next, as shown in FIG. 6G, a second photoresist pattern 430 is formed by applying a second photoresist layer over the gate insulating layer 420 and performing an exposure and a development process using a second diffraction exposure mask (not shown) do.

At this time, the transmissive portion of the second diffraction exposure mask is defined corresponding to the data line forming metal 414a on the gate pad metal, the data pad metal, and the pixel electrode forming portion, and the transflective portion is defined in the thin film transistor forming portion Between the source / drain electrodes 412a / 412b and on the data line formation metal 414a on the storage electrode pattern. In this case, the transflective portion can partially overlap with the source / drain electrodes 412a / 412b.

Therefore, after development of the second photoresist layer, the second photoresist layer pattern 430 is removed corresponding to the transmissive portion, and the portion corresponding to the transflective portion remains patterned to some thickness.

The gate insulating layer 420 is etched using the second photoresist pattern 430 as a mask so that gate pad contact holes 435a and data pad contact holes 435b are formed in the gate pad portion and the data pad portion, And a pixel electrode defining hole 435c is formed in the pixel electrode forming portion to form a gate insulating film pattern 420a.

As shown in FIG. 6I, the second photoresist pattern 430 partially remaining in thickness corresponding to the transflective portion is ashed and removed. In this process, the thickness of the second photoresist pattern 430 in the remaining region corresponding to the remaining light-shielding portions is also partially removed to form the second photoresist pattern 430a.

 Next, as shown in FIG. 6J, a metal layer 440 is deposited on the entire surface of the substrate 400 including the second photoresist film secondary pattern 430a.

In this process, the metal layer 440 is formed in the gate pad contact hole 435a, the data pad contact hole 435b, and the pixel electrode defining hole 435c together with the upper portion of the second photoresist pattern 430a, Remains on the exposed gate insulating film pattern 420a.

Next, as shown in FIG. 6K, the second photoresist pattern 430a and the upper metal layer 440 are lifted off by using a photoresist stripper.

The metal layer remaining in the gate pad contact hole 435a is electrically connected to the gate pad electrode 440d and the metal layer remaining in the data pad contact hole 435b is electrically connected to the data pad electrode 440e, The metal layer remaining on the gate insulating layer pattern 420a of the gate line forming portion is the gate line 440b and the metal layer remaining on the gate electrode forming portion of the source electrode 412a extends from the source electrode 412a to the drain electrode 412b The formed metal layer functions as the gate electrode 440a.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1 is a cross-sectional view of a conventional thin film transistor array substrate

2 is a plan view showing a thin film transistor array substrate according to the present invention.

FIGS. 3A to 3E are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a first embodiment of the present invention

4A to 4C are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a second embodiment of the present invention

5A to 5E are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a third embodiment of the present invention

6A to 6K are cross-sectional views showing a manufacturing method of a thin film transistor array substrate according to a fourth embodiment of the present invention

Description of the Related Art [0002]

100: substrate 101: gate line

101a: gate electrode 102: data line

102a: source electrode 102b: drain electrode

110: semiconductor layer 111a: gate pad electrode

111b: Data pad electrode 111c: Pixel electrode

112: data lines 120a, 120b, 120c and 120d: semiconductor layers

122a: storage electrode pattern 122b: gate pad metal

130: gate insulating film 140: photosensitive film pattern

150a: pixel electrode defining hole 150b: gate pad contact hole

150c: Data pad contact hole

Claims (10)

A thin film transistor forming portion at an intersection of the gate line and the data line forming portion and a pixel region between the gate line and the data line forming portion and the gate line and the data line forming portion in a direction crossing each other, Preparing a substrate on which a pad forming portion of each end of each of the data line forming portions is defined; Forming a semiconductor layer forming layer and a data line forming metal on the substrate by using a first diffraction exposure mask process to selectively remove pad metal in the pad forming portion and data lines in the data line forming portion, Forming a gate electrode, a storage electrode in the gate line forming portion, a source electrode and a drain electrode spaced apart from each other in the thin film transistor forming portion, and a semiconductor layer under the storage electrode; A gate insulating layer and a second photoresist layer are formed on the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode and the drain electrode, and then the second photoresist layer is exposed and developed using a second diffraction exposure mask Forming a second photoresist pattern having a low thickness between the source electrode and the drain electrode, wherein the pad formation region and the pixel region are removed; Etching the gate insulating layer using the second photoresist pattern to form a pad contact hole and a pixel electrode forming hole; Forming a second photoresist pattern in the second photoresist pattern by advancing the ashing to such an extent that a low thickness corresponding to the gap between the source electrode and the drain electrode of the second photoresist pattern is removed; Depositing a metal layer on the substrate including the second photoresist pattern; And Removing the metal layer on the second photoresist pattern on the second photoresist layer by lift-off to form a pad electrode, a pixel electrode of the pixel electrode formation hole, a gate line in the gate line formation portion, and a gate electrode in the thin film transistor formation portion And forming a plurality of thin film transistor array substrates on the substrate. A thin film transistor forming portion at an intersection of the gate line and the data line forming portion and a pixel region between the gate line and the data line forming portion and the gate line and the data line forming portion in a direction crossing each other, Preparing a substrate on which a pad forming portion of each end of each of the data line forming portions is defined; Forming a semiconductor layer forming layer and a data line forming metal on the substrate by using a first diffraction exposure mask process to selectively remove pad metal in the pad forming portion and data lines in the data line forming portion, Forming a gate electrode, a storage electrode in the gate line forming portion, a source electrode and a drain electrode spaced apart from each other in the thin film transistor forming portion, and a semiconductor layer under the storage electrode; Forming a gate insulating layer on the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode, and the drain electrode, and removing the gate insulating layer from the pad forming portion to form a pad contact hole; A transparent electrode and a gate line forming metal are deposited on the gate insulating film including the pad contact hole and the transparent electrode and the gate line forming metal are selectively removed using a second diffraction exposure mask process, And forming a gate electrode on the gate line and a gate electrode on the thin film transistor forming portion. The method of manufacturing a thin film transistor array substrate according to claim 1, 3. The method according to claim 1 or 2, Wherein the step of using the first diffractive exposure mask process comprises: Forming a first photosensitive film on the data line forming metal in order; The first photoresist layer is exposed and developed by using a first diffraction exposure mask to form a first photoresist layer having a thickness corresponding to a channel portion of the thin film transistor and having a relative thickness to the pad forming portion, Forming a first photoresist pattern having a thick thickness and removing the first photoresist pattern with respect to the remaining regions; Forming a data line on the data line forming portion, a storage electrode in the gate line forming portion, and a thin film transistor in the gate line forming portion, wherein the data line forming metal and the semiconductor layer forming layer are removed using the first photoresist pattern, Forming a data line forming metal in the transistor forming portion and a semiconductor layer in the lower portion; Forming a first photoresist film secondary pattern by ashing the first photoresist pattern to such an extent that all of the low thickness corresponding to the channel portion of the thin film transistor is removed; And Forming a semiconductor layer on the source and drain electrodes spaced apart from each other by removing the data line forming metal in the channel portion of the thin film transistor exposed using the first photoresist film secondary pattern and the thin film transistor forming portion; And forming a thin film transistor array substrate on the substrate. The method of claim 3, Wherein the first diffraction exposure mask has a transflective portion corresponding to a channel portion of the thin film transistor and has a shielding portion for the pad forming portion, the data line forming portion, and the gate line forming portion. Way. The method according to claim 1, Wherein the second diffraction exposure mask has a transflective portion corresponding to a channel portion and a gate line formation portion of the thin film transistor and has a transmissive portion with respect to the pad formation portion and the pixel region. 3. The method according to claim 1 or 2, After the step of preparing the substrate, Forming a shielding layer corresponding to the gate line forming portion, the data line forming portion, the thin film transistor forming portion, and the pad forming portion; And Further comprising forming a buffer layer on the substrate including the shielding layer. The method according to claim 6, Wherein the shielding layer and the buffer layer are patterned together by the first diffraction exposure mask process. 3. The method of claim 2, Wherein the step of using the second diffractive exposure mask process comprises: Forming a second photoresist film on the gate line forming metal in order on the gate insulating film including the pad contact hole; The second photoresist film is exposed and developed by using a second diffraction exposure mask to form the pad formation portion and the pixel region so as to have a low thickness corresponding to a region between the source electrode and the drain electrode of the gate line formation portion and the thin film transistor formation portion Forming a second photoresist pattern having a relatively thick thickness corresponding to a region of the first photoresist pattern, and removing the second photoresist pattern with respect to the remaining regions; Forming a gate line in the gate line forming portion and a gate electrode in the thin film transistor forming portion by removing the gate line forming metal and the transparent electrode using the second photoresist pattern; Forming a second photoresist pattern by ashing the second photoresist pattern to such an extent that all of the low thickness of the second photoresist pattern is removed; And And forming the pad electrode and the pixel electrode by removing the gate line forming metal in the pixel region and the exposed pad forming portion using the second photoresist pattern. ≪ / RTI > 9. The method of claim 8, Wherein the second diffraction exposure mask has a semi-transparent portion corresponding to the pad forming portion and the pixel region, and has a shielding portion corresponding to a region between the source electrode and the drain electrode of the channel portion of the gate line and the thin film transistor. A method of manufacturing a transistor array substrate. A thin film transistor forming portion at an intersection of the gate line and the data line forming portion and a pixel region between the gate line and the data line forming portion and the gate line and the data line forming portion in a direction crossing each other, Preparing a substrate on which a pad forming portion of each end of each of the data line forming portions is defined; Forming a shielding layer forming metal and a buffer layer, a semiconductor layer forming layer, and a data line forming metal on the substrate, and selectively removing the metal and the buffer layer, the semiconductor layer forming layer, and the data line forming metal using the first diffraction exposure mask process, Forming a semiconductor layer, a buffer layer, and a shielding layer under the data lines, the storage electrodes in the gate line forming portion, the source and drain electrodes spaced apart from each other in the thin film transistor forming portion, and the data line in the line forming portion; A gate insulating layer and a second photoresist layer are formed on the entire surface of the substrate including the pad metal, the data line, the storage electrode, the source electrode and the drain electrode, and then the second photoresist layer is exposed and developed using a second diffraction exposure mask Forming a second photoresist pattern having a low thickness between the source electrode and the drain electrode, wherein the pad formation region and the pixel region are removed; Etching the gate insulating layer using the second photoresist pattern to form a pad contact hole and a pixel electrode forming hole; Forming a second photoresist pattern in the second photoresist pattern by advancing the ashing to such an extent that a low thickness corresponding to the gap between the source electrode and the drain electrode of the second photoresist pattern is removed; Depositing a metal layer on the substrate including the second photoresist pattern; And Removing the metal layer on the second photoresist pattern on the second photoresist layer by lift-off to form a pad electrode, a pixel electrode of the pixel electrode formation hole, a gate line in the gate line formation portion, and a gate electrode in the thin film transistor formation portion And forming a plurality of thin film transistor array substrates on the substrate.

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