KR101429914B1 - Liquid Crystal Display Device and Method For Fabricating the Same - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device including a thin film transistor using polysilicon, which can reduce parasitic capacitance without decreasing the aperture ratio or increasing the process Structure and a method for producing the same.

In order to achieve the above object, a liquid crystal display device according to the present invention comprises a data line formed in a region where a part of the gate insulating film 102 and the interlayer insulating film 112 are removed, A parasitic capacitance is reduced and an etch stopper 112d is provided on a region of the base insulating film formed on the substrate so as to overlap with the data line so that uniform image quality can be secured.

Polysilicon, etch stopper 112d, parasitic capacitance, vertical crosstalk

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device,

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly to a liquid crystal display device using polysilicon.

In accordance with the development of the information society, various flat panel display devices have been spotlighted in place of the conventional CRT (Cathode Ray Tube) in order to display visual information. Examples of such flat panel display devices include a plasma display panel (PDP) (Field Emission Display Device), an LCD (Liquid Crystal Display Device), and an OLED (Organic Light Emitting Diode).

2. Description of the Related Art Flat panel displays generally include a flat panel display panel having a plurality of pixels in which two substrates are arranged opposite to each other and arranged in a matrix.

As a method of driving the plurality of pixels arranged in the matrix form, there is a passive matrix method in which pixels are driven by using two electrodes crossing each other, and a switching element for driving a pixel for each pixel is provided There is an active matrix method.

2. Description of the Related Art At present, a liquid crystal display device, which is a typical flat panel display device used in various fields ranging from a display screen of a mobile phone to a monitor of a personal computer and a display screen of a large-sized television, is mostly implemented by adopting an active matrix method. Thin film transistors using amorphous silicon are mainly used as switching elements in pixels.

However, in the case of a thin film transistor using amorphous silicon, there is a limit to the improvement of the device characteristics due to limitations of the electron mobility and the stability to light, thereby realizing a premium liquid crystal display device having a high display quality .

In order to overcome such limitations, the development of thin film transistors using poly-silicon has received attention.

Particularly, since the polycrystallization technique of amorphous silicon using an excimer laser was developed in the late 1980's, the development of a liquid crystal transistor using polycrystalline silicon is further accelerated.

In the case of using an excimer laser, the heat treatment time of the pulsed excimer laser is very short as 30 to 200 nanoseconds, so that the amorphous silicon can be polycrystallized without thermal damage to the glass substrate .

As described above, since it is possible to use polysilicon thin film transistor elements having excellent electrical characteristics as compared with amorphous silicon, it becomes possible to realize a premium liquid crystal display device having excellent electrical characteristics.

However, in the case of a liquid crystal display device including a thin film transistor using polysilicon as described above, it is still mainly used for a small display device such as a display screen of a small mobile phone or a notebook computer due to an increase in process cost.

Such a compact display device realizes a screen by driving a liquid crystal interposed between two substrates mainly by a vertical electric field.

1 is a cross-sectional view illustrating a twisted nematic mode (hereinafter referred to as "TN mode") of a liquid crystal display device implemented using polysilicon. In Fig. 1, only components necessary for explanation are shown for convenience, and the remaining components are omitted. Like reference numerals refer to like elements throughout the following drawings.

1, the conventional TN mode liquid crystal display comprises a first substrate 10a and a second substrate 10b which are bonded together and facing each other, and a liquid crystal layer 70 interposed between the two substrates .

The first substrate 10a includes a gate line 105 and a data line 60 crossing the gate line 105 and the insulating film to define a pixel region, (Not shown) formed at the intersection of the data lines, a protective film 20 formed to cover the data lines, and a pixel electrode 30 formed on the protective film and connected to the thin film transistor.

The second substrate includes a black matrix 50 defining a pixel region to correspond to a pixel region of the first substrate, a color filter (not shown) formed on the pixel region, And a common electrode 40 formed thereon.

That is, the liquid crystal display of the TN mode drives the liquid crystal by an electric field vertically formed between the pixel electrode provided on the first substrate and the common electrode provided on the second substrate, so that the light irradiated from the separately provided light source To implement an image.

For reference, FIG. 1 shows a state in which the alignment state of two substrates is largely deviated.

However, in a liquid crystal display device of a vertical electric field provided with a thin film transistor using polysilicon as described above, liquid crystal is driven by an electric field formed between two substrates. Therefore, There is a problem that display quality may be lowered due to the light transmitted from the region where it is not normally driven.

That is, in the region (A) corresponding to the upper portion of the pixel electrode in FIG. 1, the liquid crystal is normally driven, but in the region where the pixel electrode is not formed, the liquid crystal is not normally driven. I have a problem that can seem like a bird.

The black matrix 50 is formed of a material capable of blocking light in order to prevent light from leaking in a region where the liquid crystal is not normally driven. However, as shown in FIG. 1, if the aligned state of the two bonded substrates is not good, There may arise a problem that light leaks from the region C where the matrix is formed and the region B between the region A where the pixel electrode is formed.

As described above, in order to solve the problem that light leaks in accordance with the cemented state, a method has been proposed in which the pixel electrode is extended to the region corresponding to the upper portion of the data line, as shown in Fig. That is, when the pixel electrode 30 is formed to have the region D overlapping the black matrix 50, the liquid crystal above the pixel electrode is normally driven, so that even if the state of adhesion is not good, have.

However, when the pixel electrode 30 and the data line 60 are formed to overlap with each other, the protective film 20 interposed between the pixel electrode 30 and the data line 60 is an insulator, so that a kind of parasitic capacitance Cdp, There is a problem that a problem occurs.

The parasitic capacitance affects the level shift voltage Vp of the pixel voltage charged in the pixel electrode as shown in Equation 1 below. Accordingly, when the parasitic capacitance increases, a coupling occurs between the pixel voltage charged in the pixel electrode and the data signal supplied to the data line, thereby causing a problem such as vertical crosstalk .

(Vp: level shift voltage, CLC: capacitance due to liquid crystal layer, Cst: storage capacitance, Cdp: parasitic capacitance between pixel electrode and data line, Vgh: gate high voltage, Vgl: gate low voltage)

Therefore, a method of increasing the storage capacitance to reduce the influence of the parasitic capacitance has been proposed. However, in this case, the aperture ratio is reduced.

The present invention provides a structure of a liquid crystal display device and a method of manufacturing the same that can reduce a parasitic capacitance without decreasing an aperture ratio or increasing a process in a liquid crystal display device including a thin film transistor using polysilicon .

According to an aspect of the present invention, there is provided a liquid crystal display device including a thin film transistor using polysilicon,

A semiconductor layer 112a to 112d formed in the thin film transistor region and having a source region 112a and a drain region 112b; A gate insulating film 102 formed on the entire surface of the substrate including the semiconductor layers 112a to 112d and the etch stopper 112d and an etch stopper 112d formed in the region of the etch stopper 112d, A gate electrode formed on the entire surface of the substrate including the gate line 105 and the gate electrode and having a region branched from the gate line 105 and overlapped with the semiconductor layers 112a to 112d; The interlayer insulating film 112 and a part of the interlayer insulating film 112 and the gate insulating film 102 are removed so that the first contact hole 135 and the drain region 112b exposing the source region 112a A data line region 138 exposing the second contact hole 136 and the etch stopper 112d for exposing the data line region 138 and a data line formed above the etch stopper 112d of the data line region 138, A source electrode 116 connected to the source region 112a through the first contact hole 135 and a drain electrode 117 connected to the drain region 112b through the second contact hole 136, A protective film formed on the entire surface of the substrate including the data line, the source electrode 116 and the drain electrode 117 and a third contact hole through which a part of the protective film is removed to expose a part of the drain electrode 117. [ And a pixel electrode connected to the electrode (117).

A liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention,

The pixel electrode and the data line are designed to overlap with each other without adding a separate process, thereby solving the problem of leakage light according to the degree of adhesion and reducing parasitic capacitance, thereby improving defects such as vertical crosstalk . In addition, since the distance between the data line and the pixel electrode can be uniformly formed over the entire screen by using the etch stopper 112d, it is possible to realize a high display quality.

3, a data line 115 is formed in a region where a gate insulating film 102 and a part of an interlayer insulating film 112 are removed to form a pixel electrode (not shown) The parasitic capacitance due to the coupling between the data lines 115 and 125 and the data line 115 is reduced and an etch stopper (not shown) is formed on the base insulating film 101 formed on the substrate 100, 112d so as to ensure uniform image quality characteristics.

For reference, reference numeral 122, which is not described, is a protective film.

Next, a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4A is a plan view of a liquid crystal display device according to a first embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line I-I 'in FIG.

4A and 4B, in the liquid crystal display according to the first embodiment of the present invention,

A base insulating film 101 formed on the entire surface of the substrate 100 and having a thin film transistor region T and an etch stopper 112d region ES and a source region 112a formed in the thin film transistor region and doped with impurity ions, A semiconductor layer 112a to 112d having a drain region 112b and an etch stopper 112d formed in an area of the etch stopper 112d and the semiconductor layers 112a to 112d and an etch stopper 112d, A gate line 105 formed on the gate insulating film 102 and a region overlapping the semiconductor layers 112a to 112d on the gate insulating film 102 An interlayer insulating film 112 formed on the entire surface of the substrate 100 including the gate line 105 and the gate electrode 105a and the interlayer insulating film 112 formed on the source region 112a and the drain region 112b, The gate insulating film ( A first contact hole 135 and a second contact hole 136 formed by removing a part of the interlayer insulating film 112 and the interlayer insulating film 112 from the gate insulating film 102 and the interlayer insulating film 112, A data line region 138 formed by removing a part of the insulating film 112 and a source electrode 116 and a second contact hole 136 connected to the source region 112a through the first contact hole 135, A data line 115 formed in the data line region 138 and a drain electrode 117 connected to the drain region 112b via the substrate 100 (including the source electrode 116 and the drain electrode 117) A third contact hole 137 in which a part of the protection film is removed to expose a part of the drain electrode 117 and a drain electrode 117 through the third contact hole, And a pixel electrode 125 formed in the pixel region so as to be connected to the pixel electrode.

The etch stopper 112d may be formed of the same layer as the semiconductor layers 112a to 112d and the etch stopper 112d may be formed to have an etch selectivity different from that of the gate insulating film 102 and the interlayer insulating film 112 .

It is preferable that the base insulating film is not exposed through the data line region 138 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112.

The substrate may be a glass substrate, a plastic substrate, a metal foil substrate, or the like.

The base insulating film 101 may be made of an inorganic insulating material such as silicon oxide.

The base insulating film prevents an impurity such as an ion component from being eluted from the substrate, and prevents leakage current to the substrate, thereby improving device characteristics. Further, it has an effect of improving the unstable adhesion state between the semiconductor layers 112a to 112d and the substrate.

In addition, the semiconductor layers 112a to 112d are formed of a polysilicon layer crystallized through an excimer laser annealing method or the like, for example, an amorphous silicon layer deposited on the substrate. The semiconductor layers 112a to 112d have a thin film transistor region in which a thin film transistor is to be formed and an etch stopper region 112d in which an etch stopper 112d is to be formed.

In addition, the semiconductor layers 112a to 112d have a source region 112a and a drain region 112b formed by implanting n-type impurity ions. It is also possible to implant p-type impurity ions.

That is, the remaining region of the polysilicon layer except for the thin film transistor region and the etch stopper 112d is patterned and removed.

The etch stopper 112d may be formed in a region of the etch stopper 112d of the polysilicon layer and may be formed of a different layer from the semiconductor layers 112a to 112d but may be formed of the same layer as the semiconductor layers 112a to 112d .

The etch stopper 112d may be formed of any material having a different etch selectivity from the gate insulating film 102 and the interlayer insulating film 112. [

The gate insulating film 102 is formed to cover the entire surface of the substrate including the semiconductor layers 112a to 112d and the etch stopper 112d and is formed of an inorganic insulating film such as silicon oxide or silicon nitride.

A gate line 105 for receiving a gate signal for driving each pixel from the outside and a gate electrode 105a formed by branching from the gate line 105 are formed on the gate insulating film 102. [

The gate electrode 105a is formed in a region corresponding to the upper portion of the semiconductor layer 112a to 112d on the gate insulating layer 102 and may be formed of a metal such as molybdenum (Mo), aluminum (Al), copper (Cu) Cr), or the like, or an alloy thereof may be formed to have a single layer or a multi-layer structure.

The interlayer insulating film 112 is formed on the entire surface of the substrate so as to cover the gate line 105 and the gate electrode, and is also formed of an inorganic insulating film such as silicon oxide or silicon nitride.

The source electrode 116 may be formed in the first contact hole 135 formed by removing the gate insulating film 102 and a part of the interlayer insulating film 112 to expose the source region 112a of the semiconductor layers 112a to 112d, And the drain electrode 117 is formed by partially removing the gate insulating layer 102 and the interlayer insulating layer 112 to expose the drain region 112b of the semiconductor layers 112a to 112d And is formed to cover the second contact hole 136. That is, the source electrode 116 is electrically connected to the source region 112a of the semiconductor layers 112a to 112d through the first contact hole 135, and the drain electrode 117 is electrically connected to the second contact hole 136 To the drain region 112b of the semiconductor layers 112a to 112d.

On the other hand, a source electrode 116 is formed to be branched from the data line, and the drain electrode 117 is formed to face the source electrode 116.

In addition, since the parasitic capacitance increases when the source electrode 116 and the gate electrode overlap, it is preferable to arrange the source electrode 116 and the gate electrode so that the overlapping region is minimized.

The data line 115 is formed in the data line region 138 where the gate insulating film 102 and the interlayer insulating film 112 are partially removed to expose a portion of the etch stopper 112d. That is, the etch stopper 112d prevents the base insulating film 101 from being etched when the data line region 138 is formed by removing the gate insulating film 102 and the interlayer insulating film 112. [

The protective layer 122 isolates the data line from the source electrode 116 and the drain electrode 117 and protects the data line from the outside. The protective layer 122 is formed of an inorganic insulating material such as silicon oxide or silicon nitride, layer structure of an organic insulating material such as a photo acryl.

Particularly preferably, it is preferable to form a low dielectric constant material having a dielectric constant (epsilon) value of 3.0 or less, such as photoacrylic, benzocyclobutene (BCB) and the like.

The pixel electrode 125 is formed to cover a third contact hole 137 formed by removing a part of the protective layer 122 to expose a part of the drain electrode 117. That is, the pixel electrode 125 is electrically connected to the drain electrode 117 through the third contact hole.

The pixel electrode 125 is preferably formed of a transparent conductive material such as indium tin oxide (ITO) or zinc-tin oxide (IZO) .

The pixel electrode 125 is preferably formed to have a region overlapping the data line 115.

4A, the liquid crystal display according to the first embodiment of the present invention has a storage capacitance of a front gate type so as to overlap with the gate line 105f at the previous stage .

As described above, in the liquid crystal display device according to the first embodiment of the present invention, in the liquid crystal display device including the thin film transistor using polysilicon, the etch stopper 112d is formed on the base insulating film and the etch stopper 112d The data line is formed on the etch stopper 112d by removing the gate insulating film 102 and the interlayer insulating film 112 so as to expose the upper surface of the etch stopper 112d.

The liquid crystal display according to the first embodiment of the present invention is configured to overlap the pixel electrode and the data line 190 to prevent the problem of leakage of light in a region where the liquid crystal is not normally driven, The distance between the data lines is increased and the parasitic capacitance can be reduced. That is, since the capacitance is proportional to the area of the overlapped electrode and is inversely proportional to the distance between the two electrodes as shown in Equation 2 below, the data line is formed in the region where the gate insulating film 102 and the interlayer insulating film 112 are removed It is possible to increase the distance between the pixel electrode and the data line to reduce parasitic capacitance due to coupling.

(C: capacitance,?: Dielectric constant, d: distance, A: overlap area)

Also, since the etch stopper 112d is provided under the data line, it is possible to uniformly etch the gate insulating film 102 and the interlayer insulating film 112 when they are etched.

Next, a liquid crystal display device according to a second embodiment of the present invention will be described with reference to Figs. 5A and 5B.

FIG. 5A is a plan view of a liquid crystal display device according to a second embodiment of the present invention, and FIG. 5B is a cross-sectional view taken along line II-II 'in FIG. 5A.

5A and 5B, in the liquid crystal display according to the second embodiment of the present invention,

A base insulating film 101 formed on the entire surface of the substrate 100 and having a thin film transistor region, a storage region and an etch stopper 112d region; a source region 112a formed in the thin film transistor region and doped with impurity ions, A second semiconductor layer 112c formed in the storage region; an etch stopper 112d formed in the region of the etch stopper 112d; A gate line 105 formed on the gate insulating film 102 and a gate line 105 branched from the gate line 105 and formed on the semiconductor substrate 102. The gate line 105 is formed on the entire surface of the substrate including the gate lines 112a to 112d and the etch stopper 112d. A gate electrode 105a formed so as to have a region overlapping with the first semiconductor layer 112a to 112d and a second semiconductor layer 112b which is substantially parallel to the gate line 105 and overlapped with the second semiconductor layer 112a to 112d, An interlayer insulating film 112 formed on the entire surface of the substrate including the gate line 105, the common line, and the gate electrode; and the source region 112a and the drain region 112b, A first contact hole 135 and a second contact hole 136 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112 to expose a portion of the etch stopper 112d A data line region 138 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112 and a source electrode 116 connected to the source region 112a through the first contact hole 135, A drain electrode 117 connected to the drain region 112b through the second contact hole 136, a data line 115 formed in the data line region 138, A protective film 122 formed on the entire surface of the substrate including the gate electrode 117, A third contact hole 137 in which a part of the protective film is removed to expose a part of the electrode 117 and a pixel electrode 125 formed in the pixel region to be connected to the drain electrode 117 through the third contact hole, And a control unit.

The pixel electrode may have a region overlapping the drain electrode 117.

The etch stopper 112d may be formed of the same layer as the semiconductor layers 112a to 112d and the etch stopper 112d may be formed to have an etch selectivity different from that of the gate insulating film 102 and the interlayer insulating film 112 .

It is preferable that the base insulating film is not exposed through the data line region 138 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112.

The protective layer 122 isolates the data line from the source electrode 116 and the drain electrode 117 and protects the data line from the outside. The protective layer 122 is formed of an inorganic insulating material such as silicon oxide or silicon nitride, layer structure of an organic insulating material such as a photo acryl.

Particularly preferably, it is preferable to form a low dielectric constant material having a dielectric constant (epsilon) value of 3.0 or less, such as photoacrylic, benzocyclobutene (BCB) and the like.

Unlike the liquid crystal display according to the first embodiment of the present invention, the pixel electrode 125 is formed so as not to overlap with the previous gate line 105f.

As described above, the liquid crystal display device according to the second embodiment of the present invention is designed so that the common lines are overlapped with the pixel electrodes and have a storage capacitance in a storage capacitance manner. Since the liquid crystal display device according to the first embodiment of the present invention is the same as the liquid crystal display device according to the first embodiment of the present invention, the description of other components will be replaced with the above description.

As described above, when the auxiliary capacitance is provided by using the common line, a more stable charging characteristic can be ensured and the display quality can be improved.

Next, a liquid crystal display device according to a third embodiment of the present invention will be described.

6 is a cross-sectional view of a liquid crystal display device according to a third embodiment of the present invention.

As shown in FIG. 6, in the liquid crystal display according to the third embodiment of the present invention,

A semiconductor device comprising: a base insulating film formed on a front surface of a substrate and having a thin film transistor region; a semiconductor layer formed on the thin film transistor region and having a source region and a drain region in which impurity ions are implanted; A gate insulating film 102 formed on the entire surface of the substrate including the semiconductor layers 112a to 112d; a gate line 105 formed on the gate insulating film 102; A gate electrode 105a formed on the semiconductor layer 102 so as to have an area overlapping with the semiconductor layers 112a to 112d; an interlayer insulating film 112 formed on the entire surface of the substrate including the gate line 105 and the gate electrode; A first contact hole 135 and a second contact hole 136 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112 to expose the source region 112a and the drain region 112b, A part of the base insulating film A data line region 138 formed by removing a part of the gate insulating film 102 and the interlayer insulating film 112 to expose the source region 112a and the source electrode 112a through the first contact hole 135, A drain electrode 117 connected to the drain region 112b through the first contact hole 116 and the second contact hole 136 and a data line 115 formed on the base insulating film exposed in the data line region 138, A protective film 122 formed on the entire surface of the substrate including the source electrode 116 and the drain electrode 117 and a third contact hole 137 in which a part of the protective film is removed to expose a part of the drain electrode 117, And a pixel electrode 125 formed in the pixel region to be connected to the drain electrode 117 through the third contact hole.

That is, the liquid crystal display according to the third embodiment of the present invention increases the distance between the pixel electrode and the data line even with a simple structure that does not include the etch stopper 112d separately under the data line 115, Thereby providing an effect of reducing the capacitance.

In the liquid crystal display device according to the third embodiment of the present invention, the description of other constituent elements will be replaced with the above description.

Next, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described.

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention includes:

Forming a base insulating film having a thin film transistor region and an etch stopper region on a substrate; forming semiconductor layers 112a to 112d and an etch stopper 112d on the base insulating film; Forming a gate insulating film 102 on the entire surface of the substrate including the gate electrodes 112a to 112d and the etch stopper 112d and then forming a gate electrode on the semiconductor layers 112a to 112d; Implanting ions into the semiconductor layers 112a to 112d to form a source region 112a and a drain region 112b; forming an interlayer insulating film 112 on the entire surface of the substrate including the gate electrode; Removing the gate insulating film 102 and a part of the interlayer insulating film 112 to expose the source region 112a, the drain region 112b and the etch stopper 112d; Forming a drain electrode 117 connected to the source electrode 116 and the drain region 112b and forming a data line on the etch stopper 112d; Forming a protective film on the entire surface of the substrate including the electrode 117 and the data line, removing the protective film to expose a part of the drain electrode 117 to form a contact hole, And forming the pixel electrode to be connected to the pixel electrode (117).

A method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to FIGS. 7A to 7F.

7A to 7F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

7A to 7F show a region of the liquid crystal display according to the first embodiment of the present invention in which the portions I to I 'are cut.

7A, a base insulating film 101 is formed on a substrate 100 so as to have a thin film transistor region T and an etch stopper 112d region ES.

The base insulating film 101 may be formed by depositing an inorganic material such as silicon oxide on a substrate by a method such as a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

Next, an amorphous silicon layer is deposited on the base insulating layer and patterned. Then, the amorphous silicon is crystallized through an excimer laser annealing method or the like to form semiconductor layers 112a to 112d 112 and an etch stopper 112d.

At this time, the method of patterning the amorphous silicon layer can be performed by, for example, a photolithography method using a photoresist.

Next, a gate insulating film 102 is formed on the entire surface of the substrate including the semiconductor layers 112a to 112d and the etch stopper 112d. The gate insulating layer 102 may also be formed by depositing an inorganic material such as silicon oxide or silicon nitride.

Next, as shown in FIG. 7B, a conductive material layer is formed on the gate insulating layer 102, and then the conductive material layer is patterned to branch off from the gate line 105 and the gate line 105 to form the semiconductor layer 112a The gate electrode 105a is formed so as to have a region overlapping with the upper portion.

The conductive material layer may be formed of a single layer or a multilayer structure made of a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr)

The method of patterning the conductive material layer can also be formed by a photolithography method or the like.

Next, as shown in FIG. 7C, using the gate electrode as a mask, n-type impurity ions are implanted into the semiconductor layers 112a to 112d to form a source region 112a and a drain region 112b. It is also possible to implant p-type impurity ions.

More specifically, after a photoresist is coated on a substrate, a photoresist pattern is formed to expose only the regions corresponding to the regions above the semiconductor layers 112a to 112d, and impurity ions A gate electrode may also act as a mask to form a self-aligned source region 112a and a drain region 112b. As described above, after the source region 112a and the drain region 112b are formed, the photoresist pattern is removed.

Next, as shown in FIG. 7D, an interlayer insulating film 112 is formed to cover the entire surface of the substrate including the gate line 105 and the gate electrode. The interlayer insulating layer 112 may be formed by depositing an inorganic insulating material such as silicon oxide or silicon nitride and may be formed of a material having the same etching selectivity as the gate insulating layer 102.

A first contact hole 135 for exposing the source region 112a by removing the gate insulating film 102 and a part of the interlayer insulating film 112 and a second contact hole 135 for exposing the drain region 112b, Holes 136 are formed. The data line region 138 in which the data line is to be formed is defined by removing a portion of the gate insulating film 102 and the interlayer insulating film 112 to expose the etch stopper 112d.

Next, as shown in FIG. 7E, a source electrode 116 connected to the source region 112a through the first contact hole 135 and a source electrode 116 connected to the drain region 112b through the second contact hole 136 Drain electrodes 117 are formed. At the same time, a data line 112d is formed on the etch stopper 112d exposed through the data line region 138. [

The first and second contact holes and the data line region 138 may be formed by applying photoresist on the interlayer insulating layer 112 and then forming the first and second contact holes and the data line region 138 The photoresist is selectively removed to expose only the portion, and the exposed portions are removed by dry etching or wet etching. At this time, if the interlayer insulating film 112 and the gate insulating film 102 are formed of a material having the same etch selectivity, it is possible to form the interlayer insulating film 112 by one step.

Next, a conductive material layer is deposited on the entire substrate including the first and second contact holes and the data line region 138, and then the conductive material layer is patterned to form the source electrode 116, the drain electrode 117, Line.

7F, a protective film 122 is formed on the entire surface of the substrate including the source electrode 116, the drain electrode 117 and the data line, and then a protective film 122 is formed to expose a part of the drain electrode 117. Next, The second contact hole 122 is removed to form the third contact hole 137. The third contact hole may also be formed in the same manner as the method of forming the first and second contact holes 136 described above.

Next, a transparent conductive material is deposited to cover the third contact hole, and then the transparent conductive material is patterned to form the pixel electrode 125 to be connected to the drain electrode 117.

The transparent conductive material may be made of a material such as indium tin oxide (ITO) or indium-zinc oxide (IZO).

In the above description, the etch stopper 112d is formed of the same layer as the semiconductor layers 112a to 112d, but it is also possible to form the etch stopper 112d by patterning the etch stopper 112d as a separate layer.

A data line is formed on the data line region 138 formed by removing the interlayer insulating film 112 and the gate insulating film 102 at the same time so as to expose a part of the base insulating film without forming the etch stopper 112d, It is also possible to reduce the parasitic capacitance due to the coupling between the electrode and the data line.

As described above, in the method of manufacturing a liquid crystal display device including a thin film transistor using polysilicon, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention is characterized in that a pixel electrode and a data line So that the problem of leakage light according to the degree of adhesion can be solved and the parasitic capacitance can be reduced to improve defects such as vertical crosstalk. In addition, since the distance between the data line and the pixel electrode can be uniformly formed over the entire screen by using the etch stopper 112d, it is possible to realize a high display quality.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

FIG. 1 is a cross-sectional view illustrating a state in which alignment of two substrates is poor in a conventional TN mode liquid crystal display device. FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.

3 is a cross-sectional view showing a main portion of a liquid crystal display device according to an embodiment of the present invention.

4A is a plan view of a liquid crystal display device according to the first embodiment of the present invention.

4B is a cross-sectional view taken along the line I-I 'in FIG.

5A is a plan view of a liquid crystal display device according to the first embodiment of the present invention.

FIG. 5B is a cross-sectional view taken along line II-II 'in FIG. 5A. FIG.

6 is a sectional view of a liquid crystal display device according to a third embodiment of the present invention.

7A to 7F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

 Description of the Related Art

10a: first substrate 10b: second substrate

20, 122: protective film 30, 125: pixel electrode

40: common electrode 50: black matrix

60, 115: data line 70: liquid crystal layer

101: base insulating film 102: gate insulating film 102:

105 : Gate line 105 105a: gate electrode

112: semiconductor layers 112a to 112d 112a: source region 112a

112b: a drain region 112b; 112c: a second semiconductor layer 112a to 112d;

112d: etch stopper 112d 116: source electrode 116:

117: drain electrode 117 135: first contact hole 135:

136: second contact hole 136: 138: data line area 138:

137: Third contact hole ST: Storage area

T: thin film transistor region ES: etch stopper 112d region

106: Common line

Claims (10)

A substrate having a base insulating film having a thin film transistor region and an etch stopper region; A semiconductor layer formed in the thin film transistor region and having a source region and a drain region; An etch stopper formed in the etch stopper region; A gate insulating film formed on the entire surface of the substrate including the semiconductor layer and the etch stopper; A gate electrode formed on the gate insulating film and having a region branched from the gate line and overlapping the semiconductor layer; An interlayer insulating film formed on the entire surface of the substrate including the gate line and the gate electrode; A data line region for exposing the first contact hole and the drain region, the second contact hole exposing the source region and the etch stopper, the second contact hole exposing a portion of the interlayer insulating film and the gate insulating film; A data line formed above the etch stopper in the data line region from which the interlayer insulating film and the gate insulating film are removed; a source electrode branched from the data line and connected to the source region through the first contact hole; A drain electrode connected to the drain region; A protective film formed on the entire surface of the substrate including the data line, the source electrode, and the drain electrode; And a pixel electrode connected to the drain electrode through a third contact hole from which a part of the protective film is removed to expose a part of the drain electrode. The method according to claim 1, Wherein the semiconductor layer is formed of a polysilicon layer. 3. The method of claim 2, Wherein the etch stopper is formed of the same layer as the semiconductor layer. The method of claim 1, wherein Wherein the etch stopper has an etch selectivity different from that of the gate insulating film and the interlayer insulating film. The method according to claim 1, And the pixel electrode is formed to overlap with the data line. The method according to claim 1, Wherein the protective film comprises a low dielectric material having a relative dielectric constant of 3.0 or less. The method according to claim 1, Wherein the pixel electrode is formed to have a region overlapping the gate line of the previous stage. The method according to claim 1, And a common line formed in the same layer as the gate line and having a region overlapping the pixel electrode. delete Depositing amorphous silicon on a substrate having a base insulating film having a thin film transistor region and an etch stopper region; Crystallizing the amorphous silicon and patterning the amorphous silicon to form a semiconductor layer on the thin film transistor region and forming an etch stopper in the etch stopper region; Forming a gate insulating film on the entire surface of the substrate including the semiconductor layer and the etch stopper; Forming a gate line on the gate insulating film and a gate electrode branched from the gate line and having a region overlapping with the semiconductor layer; Forming a source region and a drain region in the semiconductor layer; Forming an interlayer insulating film on the entire surface of the substrate including the gate line and the gate electrode; Removing a part of the interlayer insulating film and the gate insulating film to form a second contact hole exposing a first contact hole and a drain region exposing a source region and a data line region exposing the etch stopper; A source electrode connected to the source region through the first contact hole, a drain electrode connected to the drain region through the second contact hole, data on the etch stopper in the data line region from which the interlayer insulating film and the gate insulating film are removed, Forming a line; Forming a protective film over the entire substrate including the source electrode and the drain electrode and the data line; And And forming a pixel electrode connected to the drain electrode through a third contact hole in which a part of the protective film is removed to expose a part of the drain electrode.

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