KR20070055678A - Liquid crystal display panel and method of manufacturing the same - Google Patents

Abstract

The present invention provides a liquid crystal panel capable of reducing parasitic capacitance while blocking light leakage in a high-aperture structure using an organic insulating film, and a method of manufacturing the same.

To this end, the present invention and the top plate including a black matrix for separating the sub-pixel region; A lower plate facing the upper plate and the liquid crystal layer therebetween; The lower plate may include a gate line formed on the substrate; A data line crossing the gate line and a first insulating layer therebetween to divide the sub pixel region; A thin film transistor connected to the gate line and the data line, an active layer having a channel forming the channel of the thin film transistor and overlapping the data line and protruding to both sides of the data line, and covering the data line and the thin film transistor. A liquid crystal panel including an organic insulating layer and a pixel electrode formed on the organic insulating layer in the sub pixel region and connected to the thin film transistor through a contact hole penetrating through the organic insulating layer, and partially overlapping a wing portion of the active layer; The manufacturing method is disclosed.

Description

Liquid crystal display panel and its manufacturing method {LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME}

1 is a perspective view showing a data line region in a conventional liquid crystal panel.

2 is a plan view illustrating a portion of a thin film transistor substrate of a liquid crystal panel according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′ and II-II ′.

4 is a cross-sectional view illustrating a data line region of a liquid crystal panel to which the thin film transistor substrate illustrated in FIG. 3 is applied.

5A through 5D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 3.

6 is a plan view illustrating a portion of a color filter on thin film transistor array (COA) substrate of a liquid crystal panel according to another exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the COA substrate shown in FIG. 6 taken along lines III-III ′ and IV-IV ′. FIG.

8A to 8C are cross-sectional views illustrating various data line region structures of a liquid crystal panel to which the COA substrate illustrated in FIG. 6 is applied.

9A through 9E are cross-sectional views illustrating a method of manufacturing the COA substrate shown in FIG. 7.

 <Description of Symbols for Main Parts of Drawings>

10, 170: color filter substrate

12, 22, 142, 172, 242, 272: insulated substrate

14, 174, 274 black matrix 16, 176, 252 color filter

18, 178, 278: common electrode 20, 160: thin film transistor substrate

24, 144, 244: gate insulating film 26, 104, 204: data line

28, 150, 250: inorganic protective film 30, 152: organic protective film

32, 118, 218: pixel electrode 102, 202: gate line

108, 208: gate electrode 110, 210: source electrode

112 and 212 drain electrodes 114 and 214 contact holes

116, 216: active layer 146, 246: ohmic contact layer

260: color filter on thin film transistor array (COA) substrate

270: top plate 280: storage line

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel capable of reducing parasitic capacitance components while blocking light leakage, and a method of manufacturing the same.

The liquid crystal display displays an image by using the electrical and optical characteristics of the liquid crystal. Specifically, the liquid crystal display includes a liquid crystal display panel (hereinafter referred to as a liquid crystal panel) for displaying an image through a pixel matrix, and a driving circuit for driving the liquid crystal panel. The liquid crystal display includes a backlight unit for supplying light from the rear side of the liquid crystal panel because the liquid crystal panel is a non-light emitting element. The liquid crystal panel displays an image by adjusting the transmittance of light emitted from the backlight unit because the liquid crystal array state of each sub-pixel is changed according to the video signal. Such liquid crystal displays are widely used from small display devices to large display devices such as mobile communication terminals, portable computers, and liquid crystal televisions.

Specifically, the liquid crystal panel has a structure in which a liquid crystal layer is formed between the color filter substrate on which the color filter array is formed and the thin film transistor substrate on which the thin film transistor array is formed. The color filter array includes a black matrix for dividing the sub pixel areas, a color filter formed for each sub pixel, a common electrode for supplying a common voltage, and the like. The thin film transistor array includes a gate line and a data line for dividing the sub pixel areas in a cross structure, a pixel electrode formed for each sub pixel, and a thin film transistor connected between the gate line and the data line and the pixel electrode for each sub pixel. In addition, the thin film transistor substrate further includes a protective film formed between the thin film transistor and the pixel electrode to protect the thin film transistor. An inorganic insulating film or an organic insulating film is used as the protective film. An organic insulating film having a higher dielectric constant and a thickness than that of the inorganic insulating film is used to increase the aperture ratio of the pixel electrode. Since the parasitic capacitance between the data line and the pixel electrode can be reduced by such an organic insulating film, the aperture ratio is increased by overlapping the pixel electrode with both sides of the data line.

1 is an enlarged cross-sectional view of a data line region in a liquid crystal panel to which a conventional organic insulating layer is applied. The liquid crystal panel illustrated in FIG. 1 includes a color filter substrate 10 and a thin film transistor bonded together with a liquid crystal layer 19 therebetween. A substrate 20 is provided.

The color filter substrate 10 has a black matrix 14 overlapping the data line 26 of the lower plate 20 on the upper insulating substrate 10, and color filters of different colors adjacent to the black matrix 14 are formed. The color filter 16 is formed to overlap, and has a structure in which a common electrode is formed on the color filter 16. In the thin film transistor substrate 20, the data line 26 is formed on the lower insulating substrate 22 with the gate insulating layer 24 interposed therebetween, and the inorganic protective layer 28 and the organic protective layer 30 covering the data line 26 are formed. ) Is formed, and the pixel electrode 32 separated based on the data line 26 is formed on the organic passivation layer 30. The pixel electrode 32 is formed to overlap both sides of the data line 26 by the organic passivation layer 30, thereby increasing the aperture ratio of the pixel electrode 32.

However, in the conventional liquid crystal panel illustrated in FIG. 1, the line widths of the black matrix 14 and the data line 26 must be increased in order to block light leakage, thereby increasing the overlapping area with the pixel electrode 32. Referring to FIG. 1, it can be seen that at least half of the line width of the data line 26 overlaps the pixel electrode 32 due to an increase in the line width of the data line 26 for blocking light leakage. Thus, even when the organic passivation layer 30 is applied, the parasitic capacitance is increased due to an increase in the overlapping area between the data line 26 and the pixel electrode 32, so that the voltage charged in the pixel electrode 32 is fluctuated, such as dark vertical lines. Degradation problem occurs. In addition, each of the data line 26 and the pixel electrode 32 is formed by a separate mask process using a split exposure method. In this case, the overlapped area of the data line 26 and the pixel electrode 32 for each divided exposure area due to a process error. In this case, parasitic capacitance variation occurs, which causes a problem of deterioration of image quality such as local vertical lines.

Accordingly, an object of the present invention is to provide a liquid crystal panel and a method of manufacturing the same, which can reduce parasitic capacitance while blocking light leakage in a high opening ratio structure using an organic insulating layer.

In order to achieve the above object, the liquid crystal panel according to the embodiment of the present invention and the top plate including a black matrix for separating the sub-pixel region; A lower plate facing the upper plate and the liquid crystal layer therebetween; The lower plate may include a gate line formed on the substrate; A data line crossing the gate line and a first insulating layer therebetween to divide the sub pixel area; A thin film transistor connected to the gate line and the data line, an active layer having a channel forming the channel of the thin film transistor and overlapping the data line and protruding to both sides of the data line, and covering the data line and the thin film transistor. And an organic insulating layer and a pixel electrode formed on the organic insulating layer of the sub pixel region and connected to the thin film transistor through a contact hole penetrating through the organic insulating layer and partially overlapping a wing portion of the active layer.

The data line is smaller than the line width of the black matrix superimposed thereon, and the active layer is formed larger or smaller than the line width of the black matrix superimposed thereon. The pixel electrode extends inwardly of the overlapped portion of the black matrix and the active layer to overlap a portion of the active layer. At least one side of both sides of the data line is formed to overlap one side of the pixel electrode, and the pixel electrode extends inwardly of an overlapped portion of the black matrix and the data line to overlap a portion of the data line. do.

The degree of overlap between the data line and the pixel electrode is different at both sides of the data line, and the data line and the active layer are asymmetrically disposed with respect to the black matrix. In other words, the black matrix is disposed to protrude more than one side of the active layer, and the active layer is disposed to protrude more than the other side of the black matrix. In contrast, the active layer may be formed to protrude more than both sides of the black matrix. The wing of this active layer blocks light leakage. The pixel electrode overlaps the entire wing of the active layer protruding toward the sub pixel area.

The upper plate may include a color filter formed in the sub-pixel area; A common electrode is further provided to cover the color filter.

The lower plate further includes an inorganic insulating film superimposed below the organic insulating film; The contact hole is formed to penetrate the inorganic insulating film.

The organic insulating film includes a color filter formed in the sub pixel region; The color filter is formed to overlap the color filter of an adjacent sub-pixel at a portion overlapping the data line. The lower plate further includes a storage line overlapping the drain electrode of the thin film transistor with the insulating layer interposed therebetween to form a storage capacitor; A contact hole connecting the drain electrode and the pixel electrode is formed at a position overlapping the storage line.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a liquid crystal panel, comprising: preparing a top plate including a black matrix for dividing a sub pixel region; Manufacturing a lower plate facing each other with the upper plate and the liquid crystal layer interposed therebetween; The manufacturing of the lower plate may include forming a gate line formed on a substrate; Forming a data line crossing the gate line and the insulating layer to separate the sub pixel area; Forming a thin film transistor connected to the gate line and the data line; Forming a channel of the thin film transistor and forming an active layer overlapping along the data line and having wing portions protruding to both sides of the data line; Forming an organic insulating film covering the data line and the thin film transistor; Forming a pixel electrode connected to the thin film transistor through a contact hole penetrating through the organic insulating layer on the organic insulating layer in the sub pixel region so that a portion of the active layer overlaps with a wing of the active layer.

The active layer is formed in one mask process using a diffraction exposure mask or a halftone mask together with the source electrode and the drain electrode included in the data line and the thin film transistor.

The manufacturing of the upper plate may include forming a color filter in the sub-pixel area; And forming a common electrode covering the color filter.

The manufacturing of the lower plate further includes forming an inorganic insulating film superimposed below the organic insulating film; The contact hole is formed to penetrate the inorganic insulating film.

Forming the organic insulating layer includes forming a color filter in the sub pixel region; The color filter is formed to overlap the color filter of an adjacent sub-pixel at a portion overlapping the data line.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 2 to 9E.

FIG. 2 is a plan view illustrating a thin film transistor substrate of a liquid crystal panel according to an exemplary embodiment of the present invention, and FIG. 3 illustrates a data line region and a thin film transistor region of the thin film transistor substrate illustrated in FIG. 1, respectively. 4 is a cross-sectional view taken along the line II ′, and FIG. 4 is a cross-sectional view showing the color filter substrate corresponding to the area together with the data line area shown in FIG.

2 and 3 include a gate line 102 and a data line 104 formed to intersect a gate insulating layer 144 therebetween on a lower substrate 142, and a thin film transistor adjacent to an intersection thereof. 106 and the pixel electrode 118 formed in the sub pixel area provided in the intersection structure.

The gate line 102 and the data line 104 are formed to intersect with the gate insulating layer 144 therebetween to define a sub pixel area in which the pixel electrode 118 is formed.

The thin film transistor 106 supplies the data signal supplied to the data line 104 to the pixel electrode 118 in response to the scan signal supplied to the gate line 102. For this purpose, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a pixel electrode 118 facing the source electrode 110. An active layer 116 and a source electrode overlapping the gate electrode 108 with the drain electrode 112 and the gate insulating layer 144 connected therebetween to form a channel between the source electrode 110 and the drain electrode 112. An ohmic contact layer 146 formed on the active layer 116 except for the channel part is provided for ohmic contact with the 110 and the drain electrode 112.

The active layer 116 and the ohmic contact layer 146 may be formed to overlap the data line 104 formed by the same mask process. In particular, the active layer 116 further includes wings 116A protruding to both sides of the source / drain pattern including the data line 104 and the source electrode 110 and the drain electrode 114.

The passivation layer protecting the data line 104 and the thin film transistor 106 is formed in a dual structure in which the inorganic passivation layer 150 and the organic passivation layer 152 are stacked. Herein, the inorganic passivation layer 150 blocks the contact between the organic passivation layer 152 and the active layer 116 of the thin film transistor 106 so that the inorganic passivation layer 150 may be formed by chemical reaction between the organic passivation layer 152 and the active layer 116. Prevents deterioration of properties. The organic passivation layer 152 is formed to have a higher dielectric constant and thicker than the inorganic passivation layer 150 so that the pixel electrode 118 can overlap the gate line 102 and the data line 104 without the influence of parasitic capacitance. The aperture ratio of is improved.

The pixel electrode 118 is formed in the pixel region defined by the intersection of the gate line 102 and the data line 104, and the pixel electrode 118 is formed through the contact hole penetrating the organic passivation layer 152 and the inorganic passivation layer 150. 114 is connected to the drain electrode 112 of the thin film transistor 106. The pixel electrode 118 charges a data signal supplied from the thin film transistor 106 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to the potential difference, the liquid crystals positioned on the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy, and the amount of light incident through the pixel electrode 118 from a light source (not shown) is controlled to be transmitted to the color filter substrate.

In addition, the pixel electrode 118 is overlapped with the wing portion of the active layer 116 by the organic passivation layer 152 whose upper and lower portions overlap the gate line 102 and the left and right sides overlap the lower portion of the data line 104. It is formed to overlap at least one side of the line (104). In particular, the wing 116A of the active layer 116 overlapping the pixel electrode 118 serves to block light leakage, thereby reducing the overlapping area between the data line 104 and the pixel electrode 118. In other words, the line width of the data line 104 can be reduced than the black matrix 174 formed in the color filter substrate 170 as shown in FIG. 4. Both sides of the pixel electrode 118 extend inwardly of the active layer 116 overlapping the black matrix 174 to overlap the wing 116A of the active layer 116, and also overlap a portion of the data line 104. do.

Referring to FIG. 4, the color filter substrate 170 includes a black matrix 174 overlapping the data line 104 under the upper insulating substrate 172, and a color of another color adjacent below the black matrix 174. The color filter 176 is formed to overlap with the filter, and has a structure in which a common electrode 178 is formed below the color filter 176. The color filter substrate 170 faces the thin film transistor substrate 160 and the liquid crystal layer therebetween. The black matrix 174 overlaps with the data line 104 and the active layer 116, in particular the active layer 116 has a larger line width than the black matrix 174 and blocks light leakage through its wings 116A. As a result, the data line 104 can be formed with a line width smaller than that of the black matrix 174. In this case, the data line 104 and the active layer 116 are formed asymmetrically based on the black matrix 174. In other words, the black matrix 174 is aligned to the left of the active layer 116, and the active layer 116 is aligned to the right of the black matrix 174 so that the line widths of the black matrix 174 and the active layer 116 are changed. It is possible to effectively block light leakage through both sides of the data line 104 without increasing. In addition, the degree of overlap between the pixel electrode 118 and the active layer 116 and the degree of overlap between the pixel electrode 118 and the data line 104 are different from each other at both sides of the data line 104.

For example, the conventional data line 26 shown in FIG. 1 had to be formed to be 14 μm or more larger than the line width of the black matrix 14 superimposed thereon for blocking light leakage. On the other hand, in the present invention, since the wing portion 116A of the active layer 116 overlapping the pixel electrode 118 serves to block light leakage, the line width of the data line 104 is changed as shown in FIG. 4. It is possible to form small to about 6 ~ 7㎛ smaller than the line width of the black matrix 174 formed in the). In other words, the line width of the data line 104 according to the present invention can be reduced to less than half of the conventional one. Accordingly, in the conventional data line 26, the overlapping degree of the pixel electrode 32 is 8.5 μm or more in combination with the left and right, while the data line 104 of the present invention adds the overlapping degree of the pixel electrode 118 in the left and right. Since the parasitic capacitance between the data line 104 and the pixel electrode 118 can be reduced to about 2 to 4 μm, the parasitic capacitance of the data line 104 and the pixel electrode 118 is significantly reduced to a level within 20% of the conventional one. In this case, the active layer 116 is formed to have a line width larger than that of the black matrix 174 to block light leakage, and the line width of the wing portion 116A is formed to protrude to both sides of the data line 104 by adding left and right.

As described above, in the liquid crystal panel according to the present invention, the wing 116A of the active layer 116 overlapping one side of the pixel electrode 118 with the organic passivation layer 152 and the inorganic passivation layer 150 therebetween serves to block light leakage. By doing so, it is possible to reduce the line width of the data line 104 than the black matrix 174. As a result, the parasitic capacitance is reduced by more than 80% due to the reduction of the overlap area between the data line 104 and the pixel electrode 118, thereby reducing dark vertical lines due to parasitic capacitance and decreasing parasitic capacitance variation due to split exposure error. As a result, the image quality can be improved. In addition, in the liquid crystal panel according to the present invention, the vane portion 116A of the active layer 116 protruding to both sides of the data line 104 is overlapped with the pixel electrode 118 having a constant potential corresponding to the data voltage. Without the need for tomography, noise falls due to mutual interference between a driving frequency of a lamp driven by a pulse width modulation (PWM) method and a frame frequency of a liquid crystal panel can be prevented.

5A and 5D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 3.

Referring to FIG. 5A, a gate metal pattern including a gate line 102 and a gate electrode 108 connected to the gate line 102 is formed on the lower insulating substrate 142 by a first mask process. Specifically, the gate metal layer is formed on the lower insulating substrate 142 through a deposition method such as a sputtering method. As the gate metal layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and the like and alloys thereof are laminated and used in a single layer or a multilayer structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate metal pattern including the gate line 102 and the gate electrode 108.

Referring to FIG. 5B, a gate insulating layer 144 is formed on a lower insulating substrate 142 on which a gate metal pattern is formed, and a data line 104, a source electrode 110, and a drain electrode (eg, a second mask process) are formed thereon. A semiconductor pattern including a source / drain metal pattern including 112 and an active layer 116 and an ohmic contact layer 146 superimposed thereunder is formed along the source / drain metal pattern. The semiconductor pattern and the source / drain metal pattern are formed by one mask process using a diffraction exposure mask or half tone.

In detail, the gate insulating layer 144, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower insulating substrate 142 on which the gate metal pattern is formed. For example, the gate insulating film 144, the amorphous silicon layer, and the n + amorphous silicon layer are formed by a PECVD method, and the source / drain metal layer is formed by a sputtering method. An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the gate insulating layer 144, and molybdenum (Mo), aluminum (Al), chromium (Cr), and the like may be used as the source / drain metal layer. It is laminated | stacked and used by this single layer or multilayer structure. Then, a photoresist pattern having a step is formed by applying photoresist on the source / drain metal layer and then exposing and developing the photolithography process using a diffraction exposure or a halftone mask. Subsequently, the data line 104, the source electrode 110, and the drain electrode 112 are patterned by patterning the source / drain metal layer, the n + amorphous silicon layer, and the amorphous silicon layer under the etching process using a stepped photoresist pattern. A semiconductor pattern is formed including the source / drain metal pattern, including the ohmic contact layer 146 and the active layer 116 thereunder. At this time, the source electrode 110 and the drain electrode 112 of the source / drain metal pattern has a structure connected to each other. Next, a relatively thin portion of the photoresist pattern is removed by an ashing process using plasma, and the exposed source / drain metal pattern and the ohmic contact layer 146 are removed to separate the source electrode 110 and the drain electrode 112. And expose the active layer 116. Both sides of the source / drain metal pattern and the ohmic contact layer 146 are etched once more along the ashed photoresist pattern, so that the active layer 116 protrudes to both sides of the source / drain metal pattern and the ohmic contact layer 146. Have (116A). The ashed photoresist pattern is then removed by a strip process.

Referring to FIG. 5C, the inorganic passivation layer 150 and the organic passivation layer 152 including the contact hole 114 are formed on the gate insulating layer 144 on which the source / drain metal pattern is formed, by the third mask process. Specifically, the inorganic protective film 150 is formed on the gate insulating film 144 on which the source / drain metal pattern is formed by a deposition method such as PECVD, and is organic by a spin coating or spinless coating method. The protective film 152 is formed. An inorganic insulating material such as the gate insulating film 144 described above is used as the inorganic protective film 150, and an organic insulating material such as an acryl-based organic compound, BCB, or PFCB is used as the organic protective film 1520. The contact hole 114 is formed through the organic passivation layer 152 and the inorganic passivation layer 150 to expose the drain electrode 112 by a photolithography process and an etching process using a third mask.

Referring to FIG. 5D, the pixel electrode 118 connected to the drain electrode 112 is formed on the organic passivation layer 152 through the contact hole 114 in the fourth mask process. The pixel electrode 118 is coated with a transparent conductive material such as ITO, TO, IZO, or ITZO on the organic passivation layer 152 by a deposition method such as sputtering, and then patterned by a photolithography process and an etching process using a fourth mask. It is formed in the sub pixel area and is connected to the drain electrode 112 through the contact hole 114. Here, the pixel electrode 118 is formed such that its upper and lower sides overlap the gate line 102, its left and right sides overlap the wing portion 116A of the active layer 116, and at least one side thereof overlaps the data line 204. do.

As described above, the thin film transistor substrate of the liquid crystal panel according to the present invention is formed by a four-mask process and increases the aperture ratio of the pixel electrode 118 using the organic passivation layer 152, and the pixel electrode 118 and the active layer 116. The parasitic capacitance between the data line 104 and the pixel electrode 118 can be reduced by overlapping the wing portions 116A.

FIG. 6 is a plan view illustrating a portion of a color filter on thin film transistor array (hereinafter referred to as COA) substrate of a liquid crystal panel according to another exemplary embodiment of the present invention, and FIG. 7 is a data line region and a thin film of the COA substrate illustrated in FIG. 6. Sectional drawing which cut | disconnected the transistor area | region along the III-III ', IV-IV' line | wire.

The COA substrate 260 illustrated in FIGS. 6 and 7 has the same configuration except that the color filter 252 is formed instead of the organic passivation layer 152 as compared to the thin film transistor substrate 160 illustrated in FIGS. 2 and 3. Since elements are provided, detailed descriptions of overlapping components will be omitted.

In the COA substrate 260 illustrated in FIGS. 6 and 7, the gate line 202 and the data line 204 are formed to intersect with the gate insulating film 244 interposed therebetween, thereby forming the pixel electrode 218. The pixel region is defined, and the thin film transistor 206 is formed between the gate line 202 and the data line 204 and the pixel electrode 218. The thin film transistor 206 is connected to the pixel electrode 218 facing the gate electrode 208 connected to the gate line 202, the source electrode 210 connected to the data line 204, and the source electrode 210. The active layer 216 and the source electrode 210 overlapping the gate electrode 208 with the drain electrode 212 and the gate insulating film 244 interposed therebetween to form a channel between the source electrode 210 and the drain electrode 212. And an ohmic contact layer 246 formed on the active layer 216 except for the channel portion for ohmic contact with the drain electrode 212. Here, the active layer 216 and the ohmic contact layer 246 are formed to overlap the data line 204 formed by the same mask process, and in particular, the active layer 216 may include the data line 204, the source electrode 210, and the drain electrode. And wing portions 216A protruding to both sides of the source / drain pattern including 214. The drain electrode 212 overlaps the storage line 280 formed in parallel with the gate line 102 and the gate insulating layer 244 to form a storage capacitor, and a contact hole overlapping the storage line 280. The pixel electrode 118 is connected to the pixel electrode 118 through 214. The storage capacitor keeps the data signal charged in the pixel electrode 218 stable.

In addition, an inorganic passivation layer 250 is formed as a passivation layer protecting the data line 204 and the thin film transistor 106, and R, G, and B color filters 252 are formed on the inorganic passivation layer 250 for each sub-pixel region. do. The color filter 252 is formed to partially overlap the color filters 252 of different colors adjacent to the data line 204. Since the color filter 252 uses a photoresist or color resin in which pigments of R, G, and B are mixed, the color filter 252 also serves as the above-described organic protective film. Each of the R, G, and B color filters 252 is formed in a dot form of a sub pixel unit or a stripe form of a column line unit.

The pixel electrode 118 is formed on the R, G, and B color filters 252 by being separated in units of sub pixels, and the drain electrode (through the contact hole 214 penetrating through the color filter 252 and the inorganic passivation layer 250). 212). In addition, the pixel electrode 218 is overlapped with the wing portion of the active layer 216 by the color filter 252, and the upper and lower portions thereof overlap the gate line 202 and the left and right sides overlap the lower portion of the data line 204. It is formed to overlap both sides of the line 204. In particular, the wing portion 216A of the active layer 216 overlapping the pixel electrode 218 serves to block light leakage, thereby reducing the overlapping area between the data line 204 and the pixel electrode 218. In other words, the line width of the data line 204 can be reduced than the black matrix 274 formed on the upper plate 270 as shown in FIGS. 8A to 8C.

8A to 8C, the upper plate 270 is formed with a black matrix 274 overlapping the data line 204 under the upper insulating substrate 272, and the common electrode 278 covering the black matrix 274. ) Has a formed structure. The upper plate 270 faces the COA substrate 260 and the liquid crystal layer therebetween. The black matrix 274 overlaps the data line 204 and the active layer 216, in particular the active layer 216 has a larger line width than the black matrix 274 and blocks light leakage through its wings 216A. As a result, the data line 204 can be formed with a line width smaller than that of the black matrix 274. In this case, the data line 204 and the active layer 216 are formed asymmetrically based on the black matrix 274. In other words, the black matrix 274 is aligned to the left side of the active layer 216, and the active layer 216 is aligned to the right side of the black matrix 274, thereby reducing the line widths of the black matrix 274 and the active layer 216. It is possible to effectively block light leakage through both sides of the data line 204 without increasing. In addition, the degree of overlap between the pixel electrode 218 and the active layer 216 and the degree of overlap between the pixel electrode 218 and the data line 204 may be different at both sides of the data line 204.

Referring to FIG. 8A, the line width of the data line 204 is smaller than the black matrix 274 and the active layer 216 is formed larger than the black matrix 274 based on the black matrix 274. The data line 204 and the active layer 216 are disposed to the right side with respect to the black matrix 274 of the upper plate 270 so that the left side of the black matrix 274 protrudes to the left side of the active layer 216. It is possible to effectively block light leakage through both sides of the (204). In addition, the degree of overlap between the data line 204, the active layer 216, and the pixel electrode 218 is larger than the left side with respect to the data line 204. Accordingly, when the alignment layer is rubbed at an angle of 45 degrees with respect to the data line 204, light leakage due to a misalignment of the right portion of the data line 204 may be effectively blocked.

FIG. 8B illustrates the case where the line widths of the data line 204 and the active layer 216 are increased in comparison with FIG. 8A, even though the data line 204 and the active layer 216 are shifted to the right with respect to the black matrix 274. The 216 protrudes from the left side of the black matrix 274 to effectively block light leakage through both sides of the data line 204. At this time, the overlapping degree between both sides of the data line 204 and the pixel electrode 218 is increased than in FIG. 8A, but since the line width of the data line 204 is smaller than that of the black matrix 274, the parasitic capacitance is reduced. The reduction effect can be obtained.

FIG. 8C illustrates a case in which the line width of the data line 204 is further reduced and the line width of the active layer 216 is smaller than that of the black matrix 274 in comparison with FIG. 8A. The data line 204 and the active layer 216 may have a black matrix 274. Are arranged to the right of). Accordingly, the pixel electrode 218 positioned on the right side of the data line 204 does not overlap the data line 204, but the wing 216A of the active layer 216 protrudes to both sides of the data line 204. In addition, the black matrix 274 biased to the right of the active layer 216 may effectively block light leakage through both sides of the data line 204. In addition, since only one side of the data line 204 overlaps the pixel electrode 218, the parasitic capacitance may be further reduced.

As described above, in the liquid crystal panel according to the present invention, the wing 216A of the active layer 216 overlapping one side of the pixel electrode 218 with the color filter 252 and the inorganic passivation layer 250 therebetween serves to block light leakage. By doing so, the line width of the data line 204 can be reduced than that of the black matrix 274. As a result, the parasitic capacitance is reduced by more than 80% due to the reduction of the overlapping area between the data line 204 and the pixel electrode 218, thereby reducing dark vertical lines due to parasitic capacitance and decreasing parasitic capacitance variation due to split exposure error. As a result, the image quality can be improved. In addition, in the liquid crystal panel according to the present invention, the vane portion 216A of the active layer 216 protruding to both sides of the data line 204 overlaps the pixel electrode 218 having a constant potential corresponding to the data voltage, thereby providing a separate light difference. Without the need for tomography, noise falls due to mutual interference between a driving frequency of a lamp driven by a pulse width modulation (PWM) method and a frame frequency of a liquid crystal panel can be prevented.

9A and 9E are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor substrate illustrated in FIG. 7.

Referring to FIG. 9A, a gate metal pattern including a gate line 202, a gate electrode 208 connected to a gate line 202, and a storage line 280 is formed on a lower insulating substrate 242 in a first mask process. Is formed. Specifically, the gate metal layer is formed on the lower insulating substrate 242 through a deposition method such as a sputtering method. As the gate metal layer, molybdenum (Mo), aluminum (Al), chromium (Cr), and the like and alloys thereof are laminated and used in a single layer or a multilayer structure. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate metal pattern including the gate line 202, the gate electrode 208, and the storage line 280.

Referring to FIG. 9B, a gate insulating layer 244 is formed on a lower insulating substrate 142 on which a gate metal pattern is formed, and a data line 104, a source electrode 210, and a drain electrode are formed thereon by a second mask process. A semiconductor pattern including a source / drain metal pattern including 212 and an active layer 216 and an ohmic contact layer 246 superimposed thereunder is formed along the source / drain metal pattern. The semiconductor pattern and the source / drain metal pattern are formed by one mask process using a diffraction exposure mask or half tone.

In detail, the gate insulating layer 144, the amorphous silicon layer, the n + amorphous silicon layer, and the source / drain metal layer are sequentially formed on the lower insulating substrate 242 on which the gate metal pattern is formed. For example, the gate insulating film 244, the amorphous silicon layer, and the n + amorphous silicon layer are formed by a PECVD method, and the source / drain metal layer is formed by a sputtering method. An inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used as the gate insulating layer 144, and molybdenum (Mo), aluminum (Al), chromium (Cr), and the like may be used as the source / drain metal layer. It is laminated | stacked and used by this single layer or multilayer structure. Then, a photoresist pattern having a step is formed by applying photoresist on the source / drain metal layer and then exposing and developing the photolithography process using a diffraction exposure or a halftone mask. Subsequently, the data line 204, the source electrode 210, and the drain electrode 212 are patterned by patterning the source / drain metal layer, the n + amorphous silicon layer, and the amorphous silicon layer under the etching process using a photoresist pattern having a step difference. A semiconductor pattern including a source / drain metal pattern, and an ohmic contact layer 246 and an active layer 216 thereunder is formed. At this time, the source electrode 210 and the drain electrode 212 of the source / drain metal pattern has a structure connected to each other. Next, a relatively thin portion of the photoresist pattern is removed by an ashing process using plasma, and the source / drain metal pattern and the ohmic contact layer 246 are removed to separate the source electrode 210 and the drain electrode 212. And expose the active layer 216. Both sides of the source / drain metal pattern and the ohmic contact layer 246 are etched once more along the ashed photoresist pattern, so that the active layer 216 protrudes to both sides of the source / drain metal pattern and the ohmic contact layer 246. Will have 216A. The ashed photoresist pattern is then removed by a strip process.

Referring to FIG. 9C, an inorganic passivation layer 250 including a contact hole 214 is formed on a gate insulating layer 244 on which a source / drain metal pattern is formed by a third mask process. In the inorganic passivation layer 250, the inorganic passivation layer 150 is formed on the gate insulating layer 244 on which the source / drain metal pattern is formed by a deposition method such as PECVD. As the inorganic protective film 250, an inorganic insulating material such as the gate insulating film 244 described above is used.

Referring to FIG. 9D, R, G, and B color filters 252 are formed in each sub pixel area on the inorganic passivation layer 250 by the fourth to sixth mask processes. Specifically, an R color filter is formed by applying an R photoresist and patterning the photolithography process using a fourth mask, and the G and B color filters 252 are sequentially formed in the same manner using the fifth and sixth masks. Is formed. In this case, the R, G, and B color filters 252 may be formed in a dot form in a sub pixel unit or a stripe form in a column unit, and the contact hole 214 may be formed to penetrate the color filter 252. In other words, when the color filter 252 is formed, a contact hole 214 overlapping the contact hole 214 penetrating through the inorganic passivation layer 250 is formed.

Referring to FIG. 9E, a pixel electrode 218 connected to the drain electrode 212 is formed on the color filter 252 through the contact hole 214 in a seventh mask process. The pixel electrode 218 is coated on the color filter 252 with a transparent conductive material such as ITO, TO, IZO, or ITZO by a deposition method such as sputtering, and then patterned by a photolithography process and an etching process using a seventh mask. It is formed in the sub pixel area and is connected to the drain electrode 212 through the contact hole 214. Here, the pixel electrode 218 is formed such that upper and lower portions thereof overlap the gate lines 202, left and right sides thereof overlap the wing portions 216A of the active layer 216, and at least one side thereof overlaps the data lines 204. do.

As described above, the COA substrate of the liquid crystal panel according to the present invention is formed by a seven-mask process and increases the aperture ratio of the pixel electrode 218 by the color filter 252 which is an organic material, and the pixel electrode 218 and the active layer 216. By overlapping the wing portions 216A, the parasitic capacitance may be reduced by reducing the overlap area between the data line 204 and the pixel electrode 218.

As described above, the liquid crystal panel and the method of manufacturing the same according to the present invention serve to block light leakage from the wing portion of the active layer overlapping one side of the pixel electrode with the organic insulating layer and the inorganic insulating layer interposed therebetween so that the line width of the data line is higher than that of the black matrix. Can be reduced. Accordingly, the parasitic capacitance is reduced due to the reduction of the overlap area between the data line and the pixel electrode, and the dark vertical lines due to the parasitic capacitance are slowed down, and the variation in the parasitic capacitance due to the segmentation exposure error is reduced, thereby improving image quality.

In addition, the liquid crystal panel and the method of manufacturing the liquid crystal panel according to the present invention overlap the pixel electrode having a constant potential corresponding to the data voltage by the wing portions of the active layer protruding from both sides of the data line, thereby eliminating the need for a separate light blocking layer (PWM). It is possible to prevent a noise waterfall due to mutual interference between the driving frequency of the lamp driven by the method and the frame frequency of the liquid crystal panel.

In addition, the liquid crystal panel and the method of manufacturing the same according to the present invention can reduce the manufacturing cost by simplifying the process by forming a thin film transistor substrate in a four mask process, or by forming a COA substrate in a seven mask process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (30)

An upper plate including a black matrix separating the sub pixel areas; A lower plate facing the upper plate and the liquid crystal layer therebetween; The lower plate, A gate line formed on the substrate; A data line crossing the gate line and a first insulating layer therebetween to divide the sub pixel region; A thin film transistor connected to the gate line and the data line; An active layer forming a channel of the thin film transistor and having wings formed to overlap the data line and protrude to both sides of the data line; An organic insulating layer covering the data line and the thin film transistor; And a pixel electrode formed on the organic insulating layer in the sub pixel region and connected to the thin film transistor through a contact hole penetrating through the organic insulating layer, and partially overlapping a wing portion of the active layer. The method of claim 1, And the data line is smaller than the line width of the black matrix superimposed thereon, and the active layer is formed larger or smaller than the line width of the black matrix superimposed thereon. The method of claim 1, And the pixel electrode extends inwardly of the overlapped portion of the black matrix and the active layer to overlap a portion of the active layer. The method of claim 1, And at least one side of both sides of the data line overlaps one side of the pixel electrode. The method of claim 4, wherein And the pixel electrode extends in an overlapping portion of the black matrix and the data line to overlap a portion of the data line. The method of claim 1, The degree of overlap between the data line and the pixel electrode is different at both sides of the data line. The method of claim 1, And the data line and the active layer are asymmetrically disposed with respect to the black matrix. The method of claim 7, wherein And the black matrix is disposed to protrude more than one side of the active layer, and the active layer is disposed to protrude more than the other side of the black matrix. The method of claim 7, wherein The active layer is characterized in that the liquid crystal panel formed to protrude more than both sides of the black matrix. The method of claim 1, The wing of the active layer is a liquid crystal panel, characterized in that to block light leakage. The method of claim 1, And the pixel electrode overlaps the entire wing portion of the active layer protruding toward the sub pixel area. The method of claim 1, The top plate is A color filter formed in the sub pixel area; And a common electrode covering the color filter. The method of claim 1, The bottom plate is An inorganic insulating film superimposed below the organic insulating film; The contact hole also penetrates the inorganic insulating film. The method of claim 1, The organic insulating film A color filter formed in the sub pixel region; And the color filter is formed to overlap the color filter of an adjacent sub-pixel at a portion overlapping the data line. The method of claim 14, A storage line overlapping the drain electrode of the thin film transistor with the insulating layer interposed therebetween to form a storage capacitor; And a contact hole connecting the drain electrode and the pixel electrode to a position overlapping the storage line. Manufacturing a top plate including a black matrix separating the sub pixel regions; Manufacturing a lower plate facing each other with the upper plate and the liquid crystal layer interposed therebetween; The step of manufacturing the lower plate Forming a gate line formed on the substrate; Forming a data line crossing the gate line and the insulating layer to separate the sub pixel area; Forming a thin film transistor connected to the gate line and the data line; Forming a channel of the thin film transistor and forming an active layer overlapping along the data line and having wing portions protruding to both sides of the data line; Forming an organic insulating layer covering the data line and the thin film transistor; And forming a pixel electrode connected to the thin film transistor through a contact hole penetrating through the organic insulating layer on the organic insulating layer of the sub pixel region so that a portion of the active layer overlaps with a wing of the active layer. Method of preparation. The method of claim 16, And the active layer is formed by one mask process using a diffraction exposure mask or a halftone mask together with the source electrode and the drain electrode included in the data line and the thin film transistor. The method of claim 16, And the data line is smaller than a line width of the black matrix superimposed thereon, and the active layer is formed larger or smaller than the line width of the black matrix superimposed thereon. The method of claim 16, And the pixel electrode extends inwardly of the overlapped portion of the black matrix and the active layer to overlap a portion of the active layer. The method of claim 16, And at least one side of both sides of the data line overlaps one side of the pixel electrode. The method of claim 20, And the pixel electrode extends inwardly of an overlapped portion of the black matrix and the data line and overlaps a portion of the data line. The method of claim 16, And a degree of overlap between the data line and the pixel electrode is different at both sides of the data line. The method of claim 16, And the data line and the active layer are asymmetrically disposed with respect to the black matrix. The method of claim 23, And the black matrix is disposed to protrude more than one side of the active layer, and the active layer is arranged to protrude more than the other side of the black matrix. The method of claim 24, The active layer is a method of manufacturing a liquid crystal panel, characterized in that formed to protrude more than both sides of the black matrix. The method of claim 16, And the pixel electrode overlaps the entire wing portion of the active layer protruding toward the sub pixel region. The method of claim 16, The step of manufacturing the top plate, Forming a color filter in the sub-pixel area; And forming a common electrode covering the color filter. The method of claim 16, The manufacturing step of the lower plate, Forming an inorganic insulating film overlying the organic insulating film; And the contact hole is formed to penetrate the inorganic insulating layer. The method of claim 16, Forming the organic insulating film Forming a color filter in the sub pixel region; And the color filter is formed to overlap the color filter of an adjacent sub-pixel at a portion overlapping the data line. The method of claim 29, The step of manufacturing the lower plate Forming a storage line overlapping the drain electrode of the thin film transistor with the insulating layer interposed therebetween to form a storage capacitor; And a contact hole connecting the drain electrode and the pixel electrode to overlap the storage line.

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