KR101419235B1 - Liquid Crystal Display Device and Method for Manufacturing the Same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device for reducing a gate-to-source storage capacitance value to reduce a kickback voltage (DELTA Vp) to thereby obtain a stable image by preventing a filcher, A gate line and a data line crossing each other on the first substrate and defining a pixel region; a source electrode protruding from the data line and a plurality of And a pixel electrode formed in the pixel region and a second electrode formed between the first and second substrates so as to reduce an overlap area between the source electrode and the drain electrode and the gate line, And a liquid crystal layer.

Kickback voltage (ΔVp), Cgs (capacitance between gate and source), common line, afterimage improvement

Description

[0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that reduces flicker by reducing a gate-source storage capacitance value to reduce a kickback voltage (DELTA Vp), thereby obtaining a stable image and a method of manufacturing the same.

In general, a liquid crystal display device includes first and second substrates opposed to each other and a liquid crystal layer filled between the first and second substrates, and a plurality of pixels for performing a display operation are formed on the first substrate These pixels drive a liquid crystal by a signal applied through wirings to perform display. In this case, the wiring includes a gate line for transmitting a scanning signal and a data line for transmitting an image signal, and each pixel is connected to one gate line and one data line.

A thin film transistor is formed at an intersection of the gate line and the data line to drive the pixels. The thin film transistor includes a gate electrode protruded from the gate line, a source electrode protruded from the data line, And one drain electrode. Here, the drain electrode is connected to the pixel electrode formed in the pixel. A common electrode is formed on the entire surface of the second substrate.

In addition, a common line passing through a portion of the pixel electrode is formed parallel to the gate line, and a storage capacitor Cst is formed at a portion overlapping the pixel electrode.

Here, a liquid crystal capacitor Clc is formed between the drain electrode and the common electrode in a circuit.

At this time, the parasitic capacitance Cgs generated in the overlapped portion between the source electrode and the gate electrode of the thin film transistor (TFT) changes from the on voltage Von to the off voltage Voff when the gate voltage Vg changes from the on voltage Von to the off voltage Voff. ) Only on the side to drop. At this time, the degree of lowering is called a kickback voltage (ΔVp), and ΔVp is expressed by the following equation.

? Vp =

At this time,? Vg is the difference between the gate on / off voltages (Voff, Von). As can be seen from this equation, ΔVp is proportional to Cgs and ΔVg, and inversely proportional to Cst.

Hereinafter, a conventional method of manufacturing a liquid crystal display device will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views showing a conventional method of manufacturing a liquid crystal display device.

A conventional liquid crystal display device is manufactured in the following order.

First, as shown in FIG. 1A, a metal is deposited on a substrate 10 and selectively removed to form a gate line (not shown) and a gate electrode 11 formed in the same layer.

As shown in FIG. 1B, the gate line and the gate electrode 11 are formed on the entire surface of the substrate 10 by a gate insulating film 12.

Then, an amorphous silicon layer 13a and an impurity layer 13b are deposited on the entire surface including the gate insulating layer 12.

Next, a metal layer (the same layer as the metal layers 14a and 14b) is deposited on the impurity layer 13b, and a photoresist layer (not shown) is coated thereon.

The photoresist layer is selectively patterned to define a data line and a semiconductor layer forming portion. At this time, corresponding to the channel portion of the semiconductor layer forming portion, the photosensitive film pattern is formed by exposing and developing through a halftone mask or diffraction exposure mask (not shown) so that the thickness of the photosensitive film becomes lower.

Then, the metal layer, the impurity layer, and the amorphous silicon layer are selectively removed using the photoresist pattern (not shown) as a mask to form a data line (not shown) and a semiconductor layer forming portion.

Then, the photoresist pattern is ashed to remove the thickness corresponding to the relatively low thickness portion, thereby leaving the photoresist pattern in the semiconductor layer forming portion except for the channel portion.

Then, the metal layer and the impurity layer corresponding to the channel portion are sequentially removed using the photoresist pattern as a mask. At this time, source / drain electrodes 14a and 14b spaced apart from each other by a channel portion are formed. A semiconductor layer 13 is formed in which the amorphous silicon layer 13a and the impurity layer 13b are laminated on the lower side and the impurity layer 13b is removed corresponding to the channel portion.

As shown in FIG. 1C, a protective layer 15 is formed on the entire surface of the substrate 10 including the source / drain electrodes 14a / 14b. The passivation layer 15 is selectively removed to expose a portion of the drain electrode 14b to form a passivation layer hole 15a.

As shown in FIG. 1d, the protective film hole 15a is buried, a transparent electrode is deposited on the entire surface, and the transparent electrode is selectively removed to form the pixel electrode 16.

In the conventional liquid crystal display device thus formed, a Cgs (gate-to-source capacitance) component is generated at a portion where the gate electrode 11 and the source / drain electrodes 14a / 14b overlap with each other, DELTA Vp), which causes a flicker on the screen.

The conventional liquid crystal display device has the following problems.

A capacitance Cgs between the gate and source is generated at a portion overlapping between the gate electrode and the source electrode, which causes a large overlap area and a large kickback voltage Vp.

In this case, the kickback voltage lowers the pixel voltage and causes the deterioration of the brightness. In addition, the kickback voltage becomes an additional factor due to the resistance of the line, the capacitance, and the like, thereby causing a deviation in each region of the liquid crystal panel, .

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device and a method of manufacturing the same that prevent flicker by reducing a gate-source storage capacitance value to reduce a kickback voltage (DELTA Vp) Well, that is the purpose.

According to an aspect of the present invention, there is provided a liquid crystal display device including first and second substrates facing each other, a gate line and a data line crossing each other on the first substrate and defining a pixel region, A source electrode protruding from the data line and a drain electrode spaced apart from the source electrode and a groove provided in the gate line so as to reduce an overlap area between the source electrode and the drain electrode and the gate line, And a liquid crystal layer filled between the pixel electrode and the first and second substrates.

And a black matrix layer is further formed on the lower side of the gate line in correspondence with the groove. The black matrix layer is made of a shielding metal. For example, the shielding metal may be chromium (Cr).

Further, a buffer layer made of an inorganic insulating film may be further formed between the black matrix layer and the gate line.

Further, a common electrode alternating with the pixel electrode may be further formed in the pixel region.

The grooves may be formed of first and second grooves spaced apart from each other and formed in the gate line direction, or the grooves may be formed of first and second grooves spaced apart from each other and formed in the data line direction.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including the steps of: preparing first and second substrates facing each other; forming, on the first substrate, Forming source and drain electrodes corresponding to the grooves and spaced apart from each other, forming a data line connected to the source electrode and intersecting the gate line to define a pixel region, Forming a pixel electrode in a pixel region, and forming a liquid crystal layer between the first and second substrates.

The method may further include forming a black matrix layer on the lower side of the gate line in correspondence to the groove.

The liquid crystal display of the present invention and its manufacturing method as described above have the following effects.

It is possible to reduce the parasitic capacitance Cgs by minimizing the overlap area between the gate electrode and the source / drain electrode by forming a groove in the portion where the gate electrode and the source / drain electrode correspond to each other. As a result, the voltage applied to the pixel electrode is not reduced and the stable value can be maintained by reducing the kickback voltage value due to the parasitic capacitance. As a result, the image quality stabilization and the flicker reduction effect can be obtained.

Hereinafter, a liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view of a liquid crystal display device of the present invention, and FIG. 3 is a cross-sectional view taken along line I-I 'of FIG.

2 and 3, the liquid crystal display of the present invention includes a first substrate 100, a second substrate (not shown, opposite substrate) facing each other, A gate line 101 and a data line 102 defining a pixel region and a source electrode 102a protruded from the data line 102 and a drain electrode 102b spaced apart from the data line 102 on the gate line 101, A groove 135 provided in the gate line 101 and a gate electrode provided in the pixel region so as to reduce an overlap area between the source electrode 102a and the drain electrode 102b and the gate line 101, And a liquid crystal layer (not shown) filled between the pixel electrode 103, the common electrode 104, and the first and second substrates 100 (not shown).

The groove 135 is formed to reduce a parasitic capacitance Cgs generated at a portion overlapping the gate line 101 and the source / drain electrodes 102a / 102b. In the groove 135, The parasitic capacitance at the overlapped portion of the source electrode 102a and the drain electrode 102b corresponding to the predetermined area of the gate line 101 can be reduced. At this time, the larger the area of the groove 135 corresponding to the source electrode 102a and the drain electrode 102b and from which the gate line 101 is partially removed, the proportion of the parasitic capacitance between the gate and source can be reduced proportionally The resistance of the gate line 101 may be increased if the size of the groove 135 is abnormally large as the case may be. This is because the resistance of the gate line 101 does not affect the image quality The size and position of the area of the groove 135 are determined.

A black matrix layer is further formed under the gate line 101 including the groove 135 to cover the exposed semiconductor layer 121 in the groove 135. [ This is because, when light is incident on the semiconductor layer 121, a current (Photo current) may flow due to light even when the voltage of the thin film transistor (TFT) is turned off at this portion. And shields light through the matrix layer 131. The black matrix layer may be formed of a light shielding metal such as a light shielding resin or chromium (Cr). In the latter case, the thickness of the black matrix layer 131 can be further reduced, and the step with the non-generation portion can be minimized.

When the black matrix layer 131 is a light shielding metal, a buffer layer 112 is further provided between the gate line 101 and the black matrix layer 131 to isolate the two layers. In this case, the black matrix layer 131 is a pattern in which no voltage is applied in a floating state.

2, the grooves 135 may be formed of first and second grooves spaced apart from each other in the direction of the gate line 101, or the grooves may extend in the direction of the data line 102 (See FIG. 5B) formed therebetween, which are spaced apart from each other.

As shown in the figure, the pixel region may have a structure in which the pixel electrode and the common electrode are alternated with each other, or may have a structure in which pixel electrodes are formed in the pixel region as a whole. In the former case, the liquid crystal is driven by the transverse electric field composition between the pixel electrode 103 and the common electrode 104 in the pixel region. In the latter case, a common electrode (not shown) The liquid crystal is driven by the vertical electric field composition between the pixel electrode and the common electrode. In either case, a structure including the groove 135 corresponding to the source / drain electrodes 102a / 102b of the liquid crystal display device of the present invention may be applied.

In addition, a common line 111 is formed parallel to the gate line 101 and spaced therefrom, a plurality of common electrodes 104 branched from the common line 111 to the pixel region are formed, The common electrode connection part 104b is connected to the common electrode connection part 104b passing through the drain electrode 102b and the common electrode connection part 104b is overlapped with the pixel electrode connection part 103a, .

The drain electrode 102b and the pixel electrode connection portion 103a are connected to each other through a protection film hole 116a and the common electrode connection portion 104b is connected to the common line 111, And a storage capacitor is formed at an overlap portion between the pixel electrode connection portion 103a and the pixel electrode connection portion 103a.

On the other hand, in the above-described drawings, the semiconductor layer 121 is formed of a double layer of the impurity layer 121b removed in correspondence with the amorphous silicon layer 121a and the channel portion, and is also formed below the data line 102. [ This is a case where the semiconductor layer and the source / drain electrode are formed using the same mask. In some cases, when the semiconductor layer is formed using a separate mask, the semiconductor layer may be omitted from the lower side of the data line, Only the intersection of the gate line and the data line can be formed. In the former case, it is preferable that the black matrix layer is formed so as to correspond to the lower side of the semiconductor layer forming portion where the gate line and the common line (common electrode connecting portion) are not formed. In the latter case, The black matrix layer can be formed only at the intersection of the data line and the data line.

Hereinafter, a method of manufacturing the liquid crystal display device of the present invention will be described.

4A to 4G are process cross-sectional views showing a method of manufacturing the liquid crystal display device of the present invention.

In the method of manufacturing a liquid crystal display of the present invention, a black matrix layer 131 is formed on a first substrate 100, as shown in FIG. 4A. Here, the black matrix layer 131 is formed corresponding to a portion corresponding to a groove to be formed in a gate line and a portion where a semiconductor layer is to be formed. At this time, the black matrix layer 131 is advantageously formed of a light-shielding metal in order to maintain a low thickness. In the case of a light-shielding metal, the buffer layer 112 is formed for insulation from a gate line formed on the upper portion. Is formed on the entire surface of the first substrate 100 including the black matrix layer 131.

A gate line 101 having a metal layer deposited on the buffer layer 112 and selectively removing the metal layer to form a groove 135 in an upper portion of the black matrix layer 131, A common line 111 and a common electrode connection portion 104b parallel to the common electrode connection portion 104 and a common electrode 104 formed between the common electrode connection portion 104b and the common line 111 are formed .

4C, a gate insulating layer 114, an amorphous silicon layer (not shown) is formed on the buffer layer 112 including the gate line 101, the common line 111, the common electrode connecting portion 104b and the common electrode 104. [ The impurity layer 121a, the impurity layer 121b, and the metal layer 102e.

Next, the entire surface of the metal layer 102e is coated with the photoresist layer 125.

A transmissive portion 202 is defined on the photoresist layer 125 in correspondence with the data line and the semiconductor layer formation portion, a transflective portion 203 is defined in correspondence with the channel portion of the semiconductor layer formation portion, Thereby preparing the mask 200 in which the shielding portion 201 is defined. Here, the photoresist layer 125 is a negative photoresist layer, and when the photoresist layer 125 is a positive photoresist, the mask 200 has a reversed phase.

4D, the photoresist layer 125 is exposed and developed through the mask 200 to form a photoresist pattern 125a. At this time, after the photoresist film corresponding to the light-shielding portion 201 is removed, the metal layer 102e, the impurity layer 121b, and the amorphous silicon layer 121a are sequentially removed from the exposed portion. At this time, although not shown, the data line 102 and the semiconductor layer forming portions 121a and 121b forming the intersection with the gate line 101 are formed.

Then, the photoresist pattern is ashed so that the thickness of the photoresist layer corresponding to the channel portion is removed to form a photoresist pattern 125a.

4E, channels are defined by removing the exposed metal layer 102e and the underlying impurity layer 121b using the photoresist pattern 125a as a mask. A structure in which the amorphous silicon layer 121a and the removed impurity layer 121b are stacked is referred to as a semiconductor layer 121. A metal layer on both sides of the channel is connected to a source electrode 102a and a drain electrode 102b.

4F, a protective layer 116 is deposited on the entire surface including the semiconductor layer 121, the source / drain electrodes 102a and 102b and the data line 102 so that a part of the drain electrode 102b is exposed. Thereby forming a protective film hole 116a.

4G, a transparent electrode is deposited and buried in the protective film hole 116a to selectively remove the transparent electrode, and is electrically connected to the drain electrode 102b and has a shape alternating with the common electrode 104 The pixel electrode 103 is formed.

5A and 5B are plan views showing embodiments of the liquid crystal display device of the present invention.

5A and 5B illustrate possible embodiments of the liquid crystal display device according to the present invention. FIG. 5A is a plan view of a liquid crystal display device according to the present invention, in which grooves 135a formed on the gate line 101 are spaced apart in a direction crossing the gate line 101 And FIG. 5B shows two grooves 135b spaced in a direction parallel to the gate line, as shown in FIG. In this case, the black matrix layer 131 is positioned below the grooves 135a and 135b, and the lower black matrix layer 131 is observed on the plane through the grooves 135a and 135b.

The shape of the groove may be changed according to the shapes of the source and drain electrodes 102a and 102b and corresponds to a portion where the source and drain electrodes 102a and 102b overlap the gate line 101 The parasitic capacitance Cgs between the gate and source is reduced by the provision of the grooves 135a and 135b, and the value of the kickback voltage (Vp) can be finally reduced.

)이 산출되는 식에 의해 상기 기생 용량 Cgs 값에 킥백 전압(ΔVp)이 비례하기 때문에, 상기 기생 용량 Cgs를 줄이게 되어 킥백 전압을 줄일 수 있게 되고, 결과적으로 인가하는 데이터 전압에 대하여 하강하는 전압 값이 최소화되어, 상기 킥 백 전압에 기인한 플리커를 방지할 수 있다. That is, the kickback voltage (? Vp =

) Is proportional to the value of the parasitic capacitance Cgs, the parasitic capacitance Cgs is reduced to reduce the kickback voltage. As a result, the voltage value falling to the applied data voltage Can be minimized, and flicker due to the kickback voltage can be prevented.

Hereinafter, the factors affecting the kick back voltage and the degree of the influence will be examined through the experimental results.

FIG. 6 is a graph showing the relationship between the parasitic capacitance Cgs, the storage capacitor Cst, and the kickback voltage.

As shown in FIG. 6, it is found that the parasitic capacitance Cst is increased by setting the storage capacitor Cst to the same condition, and the kickback voltage? Vp is increased.

This kickback voltage DELTA Vp corresponds to a value obtained by subtracting a common voltage (Vcom_flicke_min) at which the flicker becomes minimum at an intermediate value (Vdata_center) of the data gradation voltage experimentally.

7 is a Pareto analysis table showing influencing factors on the common voltage deviation? Vcom.

7, the common voltage DELTA Vcom at which the flicker for each gray level is minimized depends on the thickness of the gate insulating film GI, the degree of overlap between the gate electrode and the source / drain electrodes, the width CD of the source electrode, The thickness of the gate electrode, the width of the pixel electrode (CD), and the like. The three most important factors are the thickness of the gate insulating film GI, the degree of overlap between the gate electrode and the source / It can be seen that the larger the parasitic capacitance (Cgs) is, the larger the width (CD) is related to the parasitic capacitance (Cgs), and the greater the flicker phenomenon.

The liquid crystal display of the present invention and the manufacturing method thereof reduce the overlap area between the gate electrode (gate line) and the source / drain electrodes in order to reduce the parasitic capacitance (Cgs), thereby reducing the parasitic capacitance and ultimately, It is possible to minimize the phenomenon.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Will be apparent to those of ordinary skill in the art.

1A to 1D are sectional views showing a conventional method of manufacturing a liquid crystal display device

2 is a plan view showing a liquid crystal display device according to the present invention.

3 is a cross-sectional view taken along line I-I '

4A to 4G are cross-sectional views showing the steps of the method for manufacturing the liquid crystal display device of the present invention

5A and 5B are plan views showing embodiments of the liquid crystal display device of the present invention

6 is a graph showing the relationship between the parasitic capacitance Cgs, the storage capacitor Cst, and the kickback voltage

FIG. 7 is a graph showing the relationship between the common voltage deviation < RTI ID = 0.0 >

DESCRIPTION OF REFERENCE NUMERALS FOR REFERENCE NUMERALS OF THE DRAWINGS

100: substrate 101: gate line

102a: source electrode 102b: drain electrode

103: pixel electrode 103a: pixel electrode connection portion

104: common electrode 104b: common electrode connection portion 111: common line 112: buffer layer

114: gate insulating film 116: protective film

116a: Protection film hole 121: Semiconductor layer

121a: amorphous silicon layer 121b: impurity layer

Claims (10)

First and second substrates facing each other; A gate line including data lines and at least one groove which define a pixel region crossing each other on the first substrate; A source electrode protruding from the data line and a drain electrode formed on the gate line, the source electrode being overlapped with the groove; A black matrix layer formed under the gate line and covering the groove; A pixel electrode formed in the pixel region; And And a liquid crystal layer filled between the first and second substrates. delete The method according to claim 1, Wherein the black matrix layer is made of a light shielding metal. The method of claim 3, Wherein the light-shielding metal is chromium. The method according to claim 1, Further comprising a buffer layer made of an inorganic insulating film between the black matrix layer and the gate line. The method according to claim 1, And a common electrode alternating with the pixel electrode is formed in the pixel region. The method according to claim 1, Wherein the grooves include first and second grooves spaced apart from each other and formed in the gate line direction. The method according to claim 1, Wherein the grooves are formed of first and second grooves spaced apart from each other and formed in the data line direction. Preparing first and second substrates facing each other; Forming a black matrix layer on the first substrate; Forming a gate line in one direction on the black matrix layer on the first substrate, the gate line having at least one groove covered by the black matrix layer; Forming a data line overlapping the groove and forming a source electrode formed on the gate line and a drain electrode spaced apart from the source electrode, the data line being connected to the source electrode and intersecting the gate line to define a pixel region; Forming a pixel electrode in the pixel region; And And forming a liquid crystal layer between the first substrate and the second substrate. delete

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