KR101414647B1 - Light emtting device package and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a semiconductor device, and more particularly, to a light emitting device package and a manufacturing method thereof. This invention comprises a carrier comprising a conductive semiconductor, the carrier comprising a mounting portion having a second surface recessed inwardly from a first surface; A first bonding metal layer located inside the second surface of the carrier; A metal structure located on the first bonding metal layer and including a first electrode; A semiconductor structure for implementing a light emitting device located on the metal structure; A passivation layer located on the first side; And a second electrode in contact with the semiconductor structure and located on the passivation layer.

Description

[0001] Light emitting device package and method for manufacturing same [0002]

The present invention relates to a semiconductor device, and more particularly, to a light emitting device package and a manufacturing method thereof.

A light emitting diode (LED), which is one of the light emitting devices, is a light emitting device manufactured using a semiconductor manufacturing process. Since the luminescence phenomenon was observed by applying a voltage to a semiconductor device in the 1920s, it began to be put to practical use at the end of the 1960s.

Since then, researches and developments have been made to improve the efficiency of LED steadily. In particular, there is a growing interest in LEDs having optical characteristics enough to replace conventional light sources. In addition, studies on LED packages and lighting devices using them have been actively conducted along with an increase in research on LEDs.

It is also a point light source and small-sized optical device, and its application fields are very broad in all industries including display, signal, display, lighting, bio, telecommunication, mobile phone, LCD and automobile industry.
The technology of the background of the present invention is disclosed in Korean Patent Laid-Open Publication No. 10-2009-0008036.

It is an object of the present invention to provide a method of manufacturing a light emitting device package that can integrate a chip manufacturing process and a package manufacturing process and improve a manufacturing process efficiency.

Another object of the present invention is to provide a wafer level light emitting device package capable of improving heat dissipation efficiency and reliability.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a carrier comprising a conductive semiconductor, the carrier including a mounting portion having a second surface recessed inwardly from a first surface; A first bonding metal layer located inside the second surface of the carrier; A metal structure located on the first bonding metal layer and including a first electrode; A semiconductor structure for implementing a light emitting device located on the metal structure; A passivation layer located on the first side; And a second electrode in contact with the semiconductor structure and located on the passivation layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a semiconductor structure on a first substrate; Forming a metal structure including a first electrode on the semiconductor structure; Forming a first alignment structure on the first substrate; Forming a first bonding metal layer on a second substrate comprising a conductive semiconductor and forming a second alignment structure to be coupled to the first alignment structure such that the first bonding metal layer is aligned with the metal structure; Forming a passivation layer on the second substrate; Coupling the first substrate and the second substrate such that the first alignment structure and the second alignment structure are coupled and the first bonding metal layer is bonded to the metal structure; Removing the first substrate; And forming a second electrode on the semiconductor structure.

The present invention has the following effects.

First, when a light emitting device package is manufactured using a silicon semiconductor substrate having an alignment structure, a second substrate to be a package body (carrier) in a growth substrate without requiring a chip separation process in a light emitting device manufacturing process, It is possible to reduce the number of processing steps, thereby resulting in improved productivity and economical efficiency.

In addition, this is more effective when a plurality of light emitting device packages are simultaneously fabricated on a large-area substrate because it uses a semiconductor process-based technique. Moreover, since no separate alignment equipment or bonding equipment is required, process difficulty can be reduced.

The light emitting device package manufactured by such a process has a simple structure, can greatly improve the heat emission efficiency, and can improve the reliability because the semiconductor structure is integrated into the package.

1 to 8 are diagrams showing an example of manufacturing a light emitting device package. FIG. 1 is a sectional view showing a state in which a semiconductor layer for a light emitting device is formed on a first substrate.
2 is a cross-sectional view showing a state in which a semiconductor structure and an alignment structure are formed.
3 is a cross-sectional view showing a state in which a metal structure is formed.
4 is an enlarged view of a semiconductor structure and a metal structure.
5 is a cross-sectional view showing the alignment of the first substrate and the second substrate.
6 is a cross-sectional view showing a state in which a first substrate and a second substrate are coupled.
7 is a cross-sectional view showing a state in which the first substrate is removed.
8 is a cross-sectional view showing a state in which a second electrode and a lens or a cap layer are formed.
9 is a cross-sectional view showing an example of a light emitting device package.
10 is a cross-sectional view showing a state in which a light emitting device package is mounted on a circuit board.
11 is a cross-sectional view showing another example of manufacturing the light emitting device package.
12 is a cross-sectional view showing still another example of manufacturing a light emitting device package.
13 is a cross-sectional view showing an example of a light emitting device package manufactured by the example of Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. Rather, the intention is not to limit the invention to the particular forms disclosed, but rather, the invention includes all modifications, equivalents and substitutions that are consistent with the spirit of the invention as defined by the claims.

It will be appreciated that when an element such as a layer, region or substrate is referred to as being present on another element "on," it may be directly on the other element or there may be an intermediate element in between .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and / or regions, such elements, components, regions, layers and / And should not be limited by these terms.

As shown in FIG. 1, a semiconductor layer 110 for implementing a light emitting device is formed on a first substrate 100 in order to manufacture a light emitting device package. Here, the semiconductor layer 110 may be formed of a nitride semiconductor. It goes without saying that the semiconductor layer 110 may be formed using a semiconductor material of another material substrate. For example, various compound semiconductors such as gallium arsenide (GaAs) -based semiconductors may be used.

The first substrate 100 can form a nitride-based semiconductor, and a different substrate such as sapphire, silicon carbide (SiC), and silicon (Si) or a gallium nitride substrate can be used.

In this embodiment, a case where a semiconductor layer 110 using a nitride-based semiconductor is formed on a silicon substrate 100 will be described as an example. The silicon substrate 100 may be made of insulating silicon or high resistance silicon.

Silicon (Si) has different etch characteristics depending on the crystal surface due to the nature of the material. When a proper etch species is employed, a well aligned etch pattern can be obtained according to the etch rate difference depending on the crystal face. These characteristics are well known for wet body processing technology and can be usefully used mainly in manufacturing MEMS and MOEMS devices.

Then, the semiconductor layer 110 is divided into individual device regions and etched to form a semiconductor structure 120 for implementing a light emitting device, as shown in FIG.

The first substrate 100 is then etched to form a first alignment structure 102 for the implementation of a wafer level package. At this time, the mesa structure 101 may be formed on the semiconductor structure 120 side.

The mesa structure 101 and the first alignment structure 102 may be formed by etching the surface of the first substrate 100 on which the semiconductor structure 120 is formed to a predetermined depth up to the inner surface 103 And may be formed symmetrically with respect to the semiconductor structure 120 on both sides.

The mesa structure 101 and the first alignment structure 102 can be etched using a silicon processing technique. The etched surface is a crystal plane of the [111] direction of silicon (Si) As is well known in the art.

Therefore, it is very advantageous when a wafer-level package is manufactured by combining together the second alignment structure 202 (see FIG. 5), which is then aligned with the first alignment structure 102.

3, a metal structure 130 may be formed on the semiconductor structure 120 so that the electrical connection and the structural connection of the semiconductor structure 120 are performed.

4, the semiconductor structure 120 includes an n-type semiconductor layer 121 disposed on the first substrate 100, an active layer (not shown) disposed on the n-type semiconductor layer 121 122, and a p-type semiconductor layer 123 located on the active layer 122.

In some cases, at least one buffer layer (not shown) may be included between the n-type semiconductor layer 121 and the first substrate 100. Such a buffer layer may comprise a low temperature buffer layer and a high temperature buffer layer.

The metal structure 130 may include a first electrode 131 and a first bonding metal layer 133 that are in contact with the p-type semiconductor layer 123. The first electrode 131 and the first Between the bonding metal layers 133, a diffusion preventing layer 132 may be further included.

Next, as shown in FIG. 5, a second substrate 200 capable of performing a carrier function is provided, and a second alignment structure 202 is formed to be coupled to the first alignment structure 102 described above. The second substrate 200 may be a conductive low-resistance silicon (Si) semiconductor substrate.

The second substrate 200 may be provided with a groove 204 coupled with the mesa structure 101 formed on the first substrate 100 together with the second alignment structure 202, And can function as a light emitting element mounting portion when a wafer level package is later formed.

In addition, a bonding region is defined in advance on a portion of the second substrate 200 that is aligned with the metal structure 130 of the first substrate 100.

The second bonding metal layer 210 may be located in this bonding region. The second bonding metal layer 210 may be bonded to the metal structure 130 and may serve as an electrical connection with the semiconductor structure 120 at the same time as bonding.

A passivation layer 220 may be formed on the second substrate 200 except for the second bonding metal layer 210. The passivation layer 220 may protect the second substrate 200 in the process of removing the first substrate 100 and may also protect the semiconductor structure 120 .

The first substrate 100 and the second substrate 200 may be aligned along the line A such that the first alignment structure 102 and the second alignment structure 202 are coupled to each other, The first alignment structure 102 and the second alignment structure 202 can be automatically aligned without a separate alignment process.

As shown in FIG. 6, in the second substrate 200, the first alignment structure 102 and the second alignment structure 202 are aligned and combined with the first substrate 100. At this time, the metal structure 130 may be bonded to the second bonding metal layer 210 by a thermal process, and the first bonding metal layer 133 and the second bonding metal layer 210 of the metal structure 130 may be bonded to each other do.

Next, as shown in FIG. 7, the first substrate 100 is removed through a wet etching process so that the semiconductor structure 120 is exposed.

In some cases, a step of removing the buffer layer or a step of cleaning the exposed surface may be added to the exposed surface of the semiconductor structure 120.

In this case, as described above, the groove 204 coupled with the mesa structure 101 may serve as a mounting portion where the semiconductor structure 120 and the metal structure 130 constituting the light emitting device are located. The sloped surface may help the light emitted from the semiconductor structure 120 to be reflected and emitted to the outside.

8, a second electrode 230 may be formed on the upper surface of the semiconductor structure exposed in this process. The second electrode 230 may be formed on the second substrate 200 As shown in FIG. The second electrode 230 extended in this manner can be easily coupled with the circuit when it is mounted on the circuit board in the future.

A lens or cap layer 240 may be formed on or coupled to the mounting portion 204.

In addition, a passivation layer (not shown) may be formed to cover the upper surface of the semiconductor structure 120, and if the passivation layer 220 does not completely cover the side surface of the semiconductor structure 120, The side surface of the semiconductor structure 120 can be covered so that the structure 120 can be protected.

Next, when separated into individual packages along line B, the wafer level package 300 in the state shown in Fig. 9 is completed.

That is, the package 300 includes a carrier 203 formed of a low-resistance (conductive) silicon (Si) substrate having a mounting portion 204. The metal layers 210 and 130 are located on the mounting portion 204 side, The semiconductor structure 120 is located on the metal layers 210 and 130.

The metal layers 210 and 130 may include a second bonding metal layer 210 and a metal structure 130 and the second bonding metal layer 210 may be located inside the carrier 203.

A passivation layer 220 is disposed on the upper surface of the mounting portion 204 and the carrier 203 and a second electrode 230 is disposed on the upper surface of the semiconductor structure 120 along the upper surface of the passivation layer 220.

At this time, the passivation layer 220 covers and protects part or all of the side surface of the semiconductor structure 120, and may cover the upper surface of the semiconductor structure 120, as the case may be.

A lens or cap layer 240 is positioned on the mounting portion 204 where the semiconductor structure 120 is located and a lens or cap layer 240 is formed on the lens or cap layer 240 to convert the wavelength of light emitted from the semiconductor structure 120 The wavelength conversion material 250 may be included.

Optionally, such a wavelength converting material 250 may be located in the form of a layer on the semiconductor structure 120.

The wafer-level package 300 may be mounted on the circuit board 400 in the state shown in FIG.

The package 300 is positioned and electrically coupled to the first pad 410 located on the circuit board 400 and the first pad 420 is electrically connected to the second electrode 230 of the package 300 And the wire 430. As shown in Fig. At this time, the bonding of the wire 430 may be performed by the solder bumps 431 and 432.

The second substrate 200 formed of the carrier 203 directly on the growth substrate (the first substrate 100) without the chip separation process in the manufacturing process of the light emitting device, So that the process steps can be reduced, and the mass productivity and the economical efficiency can be improved.

Also, since the semiconductor process-based technology is used, it is more effective when a plurality of light emitting device packages 300 are manufactured simultaneously on a large area substrate. Moreover, since no separate alignment equipment or bonding equipment is required, process difficulty can be reduced.

The light emitting device package 300 manufactured by this process has a simple structure and can greatly improve the heat emission efficiency and reliability can be improved since the semiconductor structure 120 is integrated into the package 300 .

11 and 12 show another embodiment of manufacturing a package by an alignment structure.

11 shows an example in which the first substrate 100 and the second substrate 200 are aligned and fabricated using only the mesa structure 101. FIG.

The mesa structure 101 is formed on the first substrate 100 on both sides of the light emitting device structure including the semiconductor structure 120 and the metal structure 130. The mesa structure 101 is formed on the inner side 103, As shown in Fig.

A groove 204 is formed on the second substrate 200 to be coupled to the mesa structure 101 so that the first substrate 100 and the second substrate 200 are aligned along the C line .

At this time, the C line may be a part separated into individual packages later.

As described above, sufficient alignment accuracy can be obtained even by using only the mesa structure 101. In this state, when the first substrate 100 and the second substrate 200 are combined to manufacture a light emitting device package, a package having the same shape as in FIG. 9 can be manufactured.

The same elements as those described above can be applied to other unexplained portions.

12 illustrates a third alignment structure 104 formed on the first substrate 100 and a fourth alignment structure 260 formed on the second substrate 200 without using a mesa structure. And the second substrate 200 are aligned and manufactured.

The third alignment structure 104 and the fourth alignment structure 260 allow the substrates 100 and 200 to be located outside the portion D where the substrates 100 and 200 are separated into individual packages.

As such, sufficient alignment accuracy can be achieved with only the alignment structure including the third alignment structure 104 and the fourth alignment structure 260 without a mesa structure.

When the package is manufactured in this state, the package 300 having the flat mounting portion as shown in FIG. 13 can be made.

That is, the metal structure 130 and the semiconductor structure 120, which are coupled to the second bonding metal layer 210, are positioned on the carrier 205 on which the second bonding metal layer 210 is positioned on the flat surface, At least a portion of the side surfaces of the metal structure 130 and the semiconductor structure 120 include a passivation layer 220.

A second electrode 231 extending to the upper side of the passivation layer 220 is positioned on the upper surface of the semiconductor structure 120.

On the other hand, a lens or cap layer 241 having a flat bottom surface is disposed on the semiconductor structure 120, and the wavelength conversion material 250 may be included in the lens or cap layer 241.

In other respects, at least one of the above-described embodiments may be applied to the unexplained portion.

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

100: first substrate 120: semiconductor structure
130: metal structure 200: second substrate
203, 205: carrier 210: second bonding metal layer
220: passivation layer 230: second electrode
240, 241: lens or cap layer 250: wavelength conversion material
300: Package

Claims (15)

A carrier comprising a conductive semiconductor, the carrier including a mounting portion having a second surface recessed inwardly from the first surface;
A first bonding metal layer located inside the second surface of the carrier;
A metal structure located on the first bonding metal layer and including a first electrode;
A semiconductor structure for implementing a light emitting device located on the metal structure;
A passivation layer located on the first side; And
And a second electrode in contact with the semiconductor structure and located on the passivation layer. The light emitting device package according to claim 1, wherein the metal structure further comprises a second bonding metal layer located on the first bonding metal layer. delete The light emitting device package according to claim 2, further comprising a diffusion prevention layer between the second bonding metal layer and the first electrode. The light emitting device package according to claim 1, wherein the second electrode extends on the passivation layer on the semiconductor structure. The light emitting device package according to claim 1, wherein the passivation layer is positioned on the mounting portion. The light emitting device package according to claim 1, further comprising a filling material or a lens located in the mounting portion. 8. The light emitting device package according to claim 7, wherein the filler or the lens includes a phosphor. delete The light emitting device package according to claim 1, wherein the carrier comprises a silicon (Si) semiconductor. Forming a semiconductor structure on a first substrate;
Forming a metal structure including a first electrode on the semiconductor structure;
Forming a first alignment structure on the first substrate;
Forming a first bonding metal layer on a second substrate comprising a conductive semiconductor and forming a second alignment structure to be coupled to the first alignment structure such that the first bonding metal layer is aligned with the metal structure;
Forming a passivation layer on the second substrate;
Coupling the first substrate and the second substrate such that the first alignment structure and the second alignment structure are coupled and the first bonding metal layer is bonded to the metal structure;
Removing the first substrate; And
And forming a second electrode on the semiconductor structure. ≪ Desc / Clms Page number 20 > 12. The method of claim 11,
The first electrode in contact with the semiconductor structure; And
And a second bonding metal layer located on the first electrode and bonded to the first bonding metal layer. 12. The method according to claim 11, wherein the first alignment structure and the second alignment structure are convex-and-concave structures engaged with each other. 12. The method according to claim 11, wherein the second substrate is a silicon (Si) semiconductor substrate. 12. The method of claim 11,
Positioning a filler or lens on the semiconductor structure; And
And cutting the second substrate to separate the first substrate and the second substrate into individual devices.

Images