KR101376221B1 - Nitride Semiconductor and Fabricating Method Thereof - Google Patents

Abstract

The present invention relates to a nitride semiconductor device and a method for manufacturing the device, the nitride semiconductor device according to an embodiment of the present invention between at least two or more nitride-based electrode bonding layer having different electrical characteristics, and between the two electrode bonding layer A semiconductor layer comprising a barrier layer disposed on the semiconductor layer; First and second electrodes respectively contacting the electrode bonding layers having different electrical characteristics; An insulating layer formed in contact with the barrier layer; And a third electrode formed on the insulating layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a nitride semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the device, and more particularly, to improve the characteristics of a device by using electrons in a valence band as a nitride transistor using a tunneling effect, and to leak through a barrier layer. The present invention relates to a nitride semiconductor device capable of reducing off-leakage current and a method of manufacturing the device.

Tunneling field effect transistors (TFETs) were first proposed by Hitachi in Japan and Cambridge University in England, but in the 1990s, conventional MOSFET miniaturization was unreasonable and energy problems were not serious, It was not possible. However, in the 2000s, as the limitations of the miniaturization of MOSFETs became imminent and the energy problem became serious, tunneling transistor research became popular again as a solution to this problem. This is due to the necessity of developing devices that replace or complement the existing MOSFETs, as power consumption is increased as semiconductor devices are reduced in size and performance is improved.

Conventional MOSFETs have a physical limitation that the subthreshold swing (SS) cannot be lowered to 60mV / dec at room temperature, and there is a fundamental problem that a significant performance degradation occurs when the driving voltage is lowered.

However, the tunneling field effect transistor controls the flow of electrons or holes in a tunneling scheme different from that of conventional MOSFETs, so that a small change in driving voltage can lead to a large change in output current. This suggests that the change of ON / OFF state occurs very rapidly according to the change of the gate voltage, and it means that the SS below the low threshold voltage is possible.

Therefore, the tunneling field effect transistor is expected to be able to operate normally even at a very low driving voltage of 1V or less. Therefore, the tunneling transistor can achieve similar performance to that of a conventional MOSFET while consuming less power. It is expected that semiconductor devices can be implemented.

1 is a cross-sectional view showing a structure of a tunneling field effect transistor according to the prior art, and FIG. 2 is an energy band diagram showing generation of a tunneling current in the n-channel TFET structure of FIG. 1.

As shown in FIG. 1, the tunneling field effect transistor according to the related art basically forms a source 120 and a drain 130 with impurities having opposite polarities to both sides of the channel region 110, unlike conventional MOSFETs. It has a structure.

For example, in the case of an n-channel TFET, a source 120 is formed as a P + region and a drain 130 is formed as an N + region on both sides of the channel region 110 on a P-type, N-type or intrinsic SOI substrate on the buried oxide film 100. . Herein, the P + region refers to a high concentration doped layer of P-type impurities, and the N + region refers to a high concentration doped layer of N-type impurities.

In the above structure, when a positive driving voltage is applied to the gate 150 on the gate insulating layer 140 and a reverse bias voltage is applied to the source 120 and the drain 130, respectively, in FIG. As shown in the figure, a junction having an energy band inclination is formed between the channel region 110 and the source 120 so that the driving current Ion due to quantum mechanical tunneling flows.

However, such a conventional tunneling field effect transistor has an inversion layer or an accumulation layer formed in the channel region in contact with the junction plane of the P + or N + region, respectively, as the gate voltage increases. The tunneling junction is formed in such a way that the area of the tunneling junction where the tunneling occurs is narrow, and the thickness of the band-to-band tunneling barrier depends on the gradual change in the depletion region of the pn junction, so that the current value is lower than that of the conventional MOSFET. There is a problem with.

An embodiment of the present invention is to provide a nitride semiconductor device and a method for manufacturing the device that can be usefully used as a high frequency, high temperature, high output power source through the improvement of the structure of the device.

A nitride semiconductor device according to an embodiment of the present invention includes a semiconductor layer including at least two or more nitride-based electrode bonding layers having different electrical characteristics, and a barrier layer disposed between the two electrode bonding layers; First and second electrodes respectively contacting the electrode bonding layers having different electrical characteristics; An insulating layer formed in contact with the barrier layer; And a third electrode formed on the insulating layer.

The barrier layer may include a first barrier layer and a second barrier layer having different band gap energies.

The first barrier layer is formed on the second electrode bonding layer in contact with the second electrode, and characterized in that a bandgap energy is smaller than that of the second barrier layer.

The first barrier layer is formed of indium gallium nitride (InGaN) or a material having a similar bandgap band to the InGaN, and the second barrier layer is formed of aluminum nitride (AlN) or a material having a similar band gap band to the AlN. It is characterized by being formed.

The material having a similar bandgap band to InGaN may be an arsenic (As) or phosphorus (P) -based compound.

The semiconductor layer is divided into a first region in which the first electrode is formed and a second region in which the second electrode is formed, and the first region and the second region form a step having a different height. do.

The third electrode may be formed at a boundary between the first region and the second region forming the step.

The electrode bonding layer contacted with the first electrode is formed of any one of P-type gallium nitride (P-GaN), N-type gallium nitride (N-GaN), and undoped gallium nitride (U-GaN), The electrode bonding layer contacted with the second electrode may be formed of any one of an N-type gallium nitride (N-GaN) and an N (+)-type gallium nitride (N ⁺ -GaN).

The first electrode and the second electrode may be formed of the same metal material, and the third electrode may be formed of a metal material different from the first and second electrodes.

In addition, a method of manufacturing a nitride semiconductor device according to an embodiment of the present invention by placing a barrier layer between the first and second electrode bonding layer of the nitride-based having a different electrical characteristics and the first and second electrode bonding layer Forming a semiconductor layer; Removing a portion of the semiconductor layer to expose the barrier layer; Forming an insulating layer on the semiconductor layer, including the exposed barrier layer, and removing contact portions formed in the first and second electrode bonding layers to form contact holes, respectively; Forming a first electrode and a second electrode contacting the first and second electrode bonding layers through the contact hole; And forming a third electrode on the insulating layer in a portion where the barrier layer is exposed so as to be positioned between the first electrode and the second electrode.

The exposing the barrier layer may expose the barrier layer by etching the second region of the semiconductor layer on which the second electrode bonding layer is formed.

The exposing the barrier layer may further expose the second electrode bonding layer by etching.

The barrier layer is characterized in that it comprises a first barrier layer and a second barrier layer having different band gap energy.

The first barrier layer is formed of indium gallium nitride (InGaN) or a material having a similar bandgap band to InGaN, and the second barrier layer is formed of aluminum nitride (AlN) or a material having a similar band gap band to AlN. It is characterized by forming.

The material having a similar bandgap band to InGaN may be an arsenic (As) or phosphorus (P) -based compound.

According to the embodiment of the present invention, by improving the characteristics of the device through the improvement of the structure of the device may be usefully used in high frequency, high temperature and high output power devices.

1 is a view showing a cross-sectional structure of a tunneling field effect transistor according to the prior art,
FIG. 2 is an energy band diagram showing generation of tunneling current in the n-channel TFET structure of FIG.
3 is a diagram illustrating an epitaxial structure according to an embodiment of the present invention;
4 is a view showing an energy band diagram according to the structure of FIG.
5 illustrates a cross-sectional structure of a nitride semiconductor device according to an embodiment of the present invention;
6 is a view illustrating a manufacturing process of the nitride semiconductor device of FIG. 5.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a diagram illustrating an epitaxial structure according to an embodiment of the present invention, Figure 4 is a diagram showing an energy band diagram according to the structure of FIG.

The epitaxial structure of FIG. 3 can be regarded as substantially representing a semiconductor layer of a semiconductor device such as a field effect transistor (FET) and a bipolar transistor.

As shown in FIG. 3, the semiconductor layer forms a multilayer structure according to an embodiment of the present invention, and each layer may include a nitride-based material. For example, an N (+) type gallium nitride (N ⁺ -GaN) 301 and an indium gallium nitride (In _x Ga _{1 - x} N) 303a on a glass substrate, a quartz substrate, a wafer, or a sapphire substrate. The semiconductor layer may be formed by sequentially stacking the aluminum nitride (AlN) 303b and the P-type gallium nitride (P-GaN) layer 305. Here, the In _x Ga _{1 - x} N layer 303a and the AlN layer 303b may operate as the barrier layer 303, where the barrier layer 303 has a higher bandgap energy than the surrounding layer, and thus, on the energy band diagram It is named in the sense that a barrier can be formed. In addition, P-GaN may be replaced with N-type gallium nitride (N-GaN) or undoped gallium nitride (U-GaN) according to an embodiment of the present invention.

Of course, such a multilayer structure forming the semiconductor layer may be variously modified. In _x Ga _{1 - x} N (hereinafter referred to as InGaN) and AlN layers 303a and 303b constituting the barrier layer 303 without departing from the technical features of the present invention, for example, to form a high band gap energy. Silver may be formed to form one layer, and thus the semiconductor layer may be formed into three stacked structures. In addition, the above structure can be realized by using a thin film having similar bandgap energy instead of the AlN thin film and the InGaN thin film. For example, an arsenic (As) or phosphorus (P) -based compound semiconductor thin film having a similar band gap band may be used instead of the InGaN thin film. Therefore, embodiments of the present invention will not be particularly limited to the stacked structure and the specific material of the semiconductor layer.

Referring to FIGS. 3 and 4 together, the semiconductor layer shows an energy band diagram as shown in FIG. 4 according to the epitaxial structure of FIG. 3. In more detail, as shown in FIG. 4, forbidden band is shown between the two graphs based on the Fermi level, the lower band of the lower graph shows the valence band, and the upper graph of the upper graph shows the conduction band, respectively. .

According to an embodiment of the present invention, the semiconductor device may utilize the tunneling effect by forming a barrier layer by, for example, AlN, In _x Ga _{1 - x} N. In other words, when a bias voltage is applied to the AlN and InGaN thin films of the barrier layer 303, the conduction band of this portion is lowered, and the distance between the valence band and the conduction band of the part ○ indicated by the dotted line as shown in FIG. Many electrons in the valence band are tunneled into the conduction band and supplied.

Accordingly, the semiconductor device according to the embodiment of the present invention enables the device operation by using a very large number of electrons present in the valence band, thereby exhibiting excellent device characteristics, as well as the AlN thin film and InGaN in the absence of voltage. Since the barrier is formed by the thin film, current leakage to the source or drain can be prevented. Furthermore, due to the excellent material properties of the nitride semiconductor having a high bandgap energy and the like, it may be useful for high frequency, high temperature and high output power devices.

5 is a diagram illustrating a cross-sectional structure of a nitride semiconductor device according to an embodiment of the present invention.

As illustrated in FIG. 5, the nitride semiconductor device according to the embodiment of the present invention may include a semiconductor layer 500, an insulating layer 510, first and second electrodes 521 and 523, and a third electrode 525. May include some or all of

As described above, the semiconductor layer 500 includes a nitride-based material such as N ⁺ -GaN, In _x Ga _{1 -x} N, AlN, and P-GaN, and is divided into first and second regions on the substrate. Can be formed. Here, P-GaN may be replaced with N-GaN or U-GaN, and the first and second regions form a step of different heights, that is, a step difference, and a region having a high step may have a plurality of stacked structures. It is desirable to achieve.

As shown in FIG. 5, for example, the first region is formed by sequentially stacking N ⁺ -GaN, In _x Ga _{1 - x} N, AlN, and P-GaN layers, and the second region is formed by only the N ⁺ -GaN layer. Can be formed. At this time, N ⁺ -GaN layer of the first region may be formed a step higher than the N ⁺ -GaN layer of the second region. According to the formation, for example, the semiconductor layer 500 formed on the substrate may have an 'L' shape.

Of course, the structure shown in FIG. 5 illustrates a structure for easily applying a bias voltage to the In _x Ga _{1 - x} N, AlN layer through the boundary portions of the first and second regions of the semiconductor layer 500. Therefore, as long as the bias voltage can be applied to the In _x Ga _{1 - x} N, AlN layer through the third electrode 525, the semiconductor layer 500 may have any structure. For example, it may be possible to form a voltage applying electrode after the groove is formed so that the corresponding region, that is, the In _x Ga _{1 - x} N, AlN layer is exposed to the outside.

In addition, an insulating layer 510 is formed on the semiconductor layer 500. The insulating layer 510 may also be referred to as a gate insulating layer. Contact holes are formed in the insulating layer 510 on the first region and the second region of the semiconductor layer 500, and the contact holes in the first region form the first electrode 521 and the semiconductor layer 500. More precisely for electrical contact with the P-GaN layer, and contact holes in the second region are formed for contacting the second electrode 523 with the semiconductor layer 500, more precisely the N ⁺ -GaN layer. . Accordingly, in the embodiment of the present invention, the P-GaN layer and the N ⁺ -GaN layer may be referred to as an electrode bonding layer.

The first electrode 521 and the second electrode 523 are formed in the contact hole formed on the insulating layer 510, and the insulating layer 510 between the first electrode 521 and the second electrode 523 is formed. On the third electrode 525 is formed. In this case, the third electrode 525 may be formed at a boundary portion where the first region and the second region of the semiconductor layer 500 are stepped with each other. As such, a bias voltage may be applied to the AlN layer and the InGaN layer through the third electrode 525 at the stepped portion.

Here, the first to third electrodes 521, 523, and 525 may refer to source, drain, and gate electrodes, respectively, according to an exemplary embodiment of the present invention. However, since the semiconductor device according to the embodiment of the present invention can be sufficiently applied to a bipolar transistor instead of a field effect transistor (FET), it may mean an emitter, a collector, and a base electrode, respectively. Therefore, in the embodiment of the present invention it will not be specifically limited to what electrode such an electrode means.

6 is a view illustrating a manufacturing process of the nitride semiconductor device of FIG. 5.

Referring to FIG. 6 together with FIG. 5, first, a structure of the semiconductor layer 500 is grown on a substrate (S601). For _{^{example, N + -GaN, In x Ga}} 1 as shown in Fig. ₅ will be sequentially stacked on the N _x, AlN, and P-GaN layers.

Subsequently, a first photolithography process is performed to etch the second region so that the first region and the second region of the semiconductor layer 500 have different steps (S603). Here, the etching of the second region is such that the N ⁺ -GaN layer forming the first layer of the semiconductor layer 500 is exposed to the outside, more precisely the N ⁺ -GaN layer of the first region and the N of the second region ^{The +} -GaN layers are also preferably formed to have steps with each other. This allows the bias voltage to be sufficiently applied through the third electrode 525 in the cross section of In _x Ga _{1 - x} N, AlN exposed through the boundary portion, and may be formed in consideration of the process.

The photolithography process for substantially exposing the N ⁺ -GaN layer in the second region to the outside is applied to the P-GaN layer by applying a photoresist film PR on the P-GaN layer in a state of stacking up to the P-GaN layer in step S601. After exposing the second region to be etched by applying), the second region may be subjected to detailed processes such as development and wet etching.

In addition, an insulating layer is deposited on the first region and the second region of the semiconductor layer 500 having the step difference to form the insulating layer 510 (S605). In this case, the insulating layer may be formed of oxide silicon (SiOx) grown by APCVD, silicon nitride (SiNx) grown by PECVD, aluminum oxide (AlxOy) grown by ALD.

Subsequently, a second photolithography process, and further an etching process, is further performed to form contact holes for forming the first and second electrodes 521 and 523 (S607 and S609). In other words, a contact hole for forming the first electrode 521 is formed in the first region to expose the P-GaN layer of the semiconductor layer 500 to the outside, and the contact hole for the second electrode 523 is formed in the first region. It is formed in two regions to expose the N ⁺ -GaN layer of the semiconductor layer 500 to the outside. Here, the contact hole of the first region may be referred to as a first contact hole, and the contact hole of the second region may be referred to as a second contact hole.

When the formation of the contact hole is completed, the first electrode 521 and the second electrode 523 are formed in the contact hole (S611). To this end, in the exemplary embodiment of the present invention, after the photoresist film is re-coated on the insulating layer 510 including a region where the contact hole is exposed to the outside, the photoresist film is exposed and developed to expose the contact hole, and then the first and Metal materials constituting the second electrodes 521 and 523 are coated. Subsequently, all of the remaining photoresist layers except for the first and second electrodes 521 and 523 formed at the contact hole are removed through a lift off process. As a result, the first electrode 521 is in contact with the P-GaN layer, and the second electrode 523 is in contact with the N ⁺ -GaN layer. Here, since the first electrode 521 and the second electrode 523 may be formed by a printing method, the method of forming the electrode will not be particularly limited in the embodiment of the present invention.

Subsequently, a photolithography process for forming the third electrode 525, for example, the gate electrode, is performed (S613). In other words, after applying the photoresist on the insulating layer 510 on which the first and second electrodes 521 and 523 are formed, the mask is applied to expose and develop the portion where the third electrode 525 is to be formed. Operation S613 thereof may be performed when the third electrode 525 is substantially a different metal material from the first and second electrodes 521 and 523. For example, if the first and second electrodes 521 and 523 are formed of one of Al, Al alloys, chromium (Cr) and titanium (Ti), the third electrode 525 may be made of molybdenum tungsten (MoW), nickel (Ni) and Titanium nitride (TiN) or the like.

Subsequently, the third electrode 525 may be formed by applying a metal material to a region where the photoresist film is removed, that is, a region where the third electrode 525 is to be formed, and removing the photoresist of the peripheral region through a liftoff process. (S615).

Until now, the nitride semiconductor device and the method of manufacturing the device according to the embodiment of the present invention have been described. However, it has been mentioned above that the method of forming the barrier layer of such a device may vary. For example, in order to apply a bias voltage from the gate electrode to the AlN layer and the In _x Ga _{1 - x} N layer, the corresponding region is etched using the center region of the semiconductor layer 500 as the second region to etch the AlN layer and the In _x Ga _{1- . The x} N layer may be exposed to the outside and the insulating layer 510 and the gate electrode may be formed. Alternatively, as shown in FIG. 5, the gate electrode may be formed after the insulating layer 510 is formed outside the 'L' shape. Accordingly, the manufacturing process may vary.

In addition, in the embodiment of the present invention, the manufacturing method was described assuming that the first and second electrodes 521 and 523 of the nitride semiconductor device are made of a metal material different from that of the third electrode 525. However, since the first to third electrodes 521, 523, and 525 may be made of the same material, the metal materials for forming the first to third electrodes 521, 523, and 525 may be formed. It may be formed simultaneously using printing technology. Thus, embodiments of the present invention will not be specifically limited to the structure, material, and fabrication method of such devices.

Meanwhile, the semiconductor devices according to the exemplary embodiment of the present invention are not limited to the FET but may mean one of a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), and a Junction Gate FET (JFET). Therefore, the gate of the FET series element, or the base of the BJT or IGBT series element can be collectively referred to as a drive terminal or a voltage application terminal (or a drive terminal or a voltage application terminal electrode). Also, the drain of the FET-type device, the collector of the BJT, and the IGBT-type device can be referred to as the current input terminal (or the current input terminal electrode) of the semiconductor device, and the source of the FET-type device and the emitter of the BJT and IGBT- May be referred to as a lead-out terminal (or current lead-out terminal).

While the invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

100: investment oxide 110: channel region
120: source 130: drain
140: gate insulating film 150: gate
500: semiconductor layer 510: insulating layer
521: first electrode 523: second electrode
525: third electrode

Claims (15)

A semiconductor layer comprising at least two nitride-based source / drain layers having different conductivity types and a barrier layer disposed between the two source / drain layers;
First and second electrodes respectively contacting the source / drain layers of different conductivity types;
An insulating layer formed in contact with the barrier layer; And
A gate electrode formed on the insulating layer; / RTI >
The barrier layer includes a first barrier layer and a second barrier layer having different band gap energies,
The first barrier layer is formed on the second source / drain layer in contact with the second electrode, and has a lower bandgap energy than the second barrier layer,
The semiconductor layer is divided into a first region in which the first electrode is formed and a second region in which the second electrode is formed, and the first region and the second region form a step having a different height. Nitride semiconductor tunneling field effect transistor. delete delete The method of claim 1,
The first barrier layer is formed of indium gallium nitride (In _x Ga _1-x N), where x is a positive integer,
The second barrier layer is formed of aluminum nitride (AlN) nitride semiconductor tunneling field effect transistor. The method of claim 1,
At least one of the first barrier layer and the second barrier layer is a nitride semiconductor tunneling field effect transistor, characterized in that the arsenic (As) or phosphorus (P) -based compound of the Group 5 series. delete The method of claim 1,
The gate electrode is formed in the boundary portion of the first region and the second region forming the step difference nitride tunneling field effect transistor. The method of claim 1,
The source / drain layer that the first electrode contacts is formed of any one of P-type gallium nitride (P-GaN), N-type gallium nitride (N-GaN), and undoped gallium nitride (U-GaN). ,
The source / drain layer in contact with the second electrode is formed of one of N-type gallium nitride (N-GaN) and N (+) type gallium nitride (N ⁺ -GaN) nitride semiconductor tunneling electric field Effect transistor. The method of claim 1,
The first electrode and the second electrode is formed of the same metal material,
The gate electrode is a nitride semiconductor tunneling field effect transistor, characterized in that the gate electrode is formed of a different metal material than the first and second electrodes. Forming a semiconductor layer by disposing a barrier layer between the first and second source / drain layers of a nitride-based nitride having a different conductivity type and the first and second source / drain layers;
Removing a portion of the semiconductor layer to expose the barrier layer;
Forming an insulating layer on the semiconductor layer, including the exposed barrier layer, and removing contact portions formed in the first and second source / drain layers to form contact holes, respectively;
Forming a first electrode and a second electrode contacting the first and second source / drain layers through the contact hole; And
Forming a gate electrode on the insulating layer in a portion where the barrier layer is exposed so as to be positioned between the first electrode and the second electrode,
The barrier layer includes a first barrier layer and a second barrier layer having different band gap energies,
The first barrier layer is formed on the second source / drain layer in contact with the second electrode, and has a lower bandgap energy than the second barrier layer,
Wherein forming the semiconductor layer comprises:
Nitride semiconductor tunneling, wherein the semiconductor layer is formed to have a step height having a different height between a first region of the semiconductor layer where the first electrode is formed and a second region of the semiconductor layer where the second electrode is formed Method of manufacturing field effect transistor. 11. The method of claim 10,
The exposing of the barrier layer may include etching the second region of the semiconductor layer where the second source / drain layer is formed to expose the barrier layer. 12. The method of claim 11,
The exposing the barrier layer may further expose the second source / drain layer by etching. delete 11. The method of claim 10,
The first barrier layer is formed of indium gallium nitride (In _x Ga _1-x N),
The second barrier layer is formed of aluminum nitride (AlN), characterized in that the nitride semiconductor tunneling field effect transistor manufacturing method. 15. The method of claim 14,
At least one of the first barrier layer and the second barrier layer is a method of manufacturing a nitride semiconductor tunneling field effect transistor, characterized in that the arsenic (As) or phosphorus (P) -based compound of the Group 5 series.

Images