KR101321404B1 - Nitride Semiconductor and Fabricating Method Thereof - Google Patents

Abstract

The present invention relates to a nitride semiconductor device and a method for manufacturing the device, the nitride semiconductor device according to an embodiment of the present invention is to be spaced apart between a plurality of nitride-based electrode bonding layer having different electrical characteristics and the electrode bonding layer A semiconductor layer including a plurality of barrier layers disposed; And a plurality of electrodes contacting the plurality of nitride-based electrode bonding layers and formed separately from each other.

Description

TECHNICAL FIELD [0001] The present invention relates to a nitride semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the device, and more particularly, to a heterojunction bipolar transistor (HBT) using a tunneling effect, for example, by using electrons in a valence band. The present invention relates to a nitride semiconductor device and a method of manufacturing the device capable of improving the characteristics of the semiconductor device and reducing off-leakage current through the barrier layer.

In general, HBT is noticed as a high functional device that can greatly improve the implant efficiency of the emitter and improve the transistor characteristics by changing the composition of the emitter region and the base region so that the band gap of the emitter region becomes larger than the base region. I have received it. The HBT is particularly used as an element in the microwave and millimeter wave band because of its excellent high frequency characteristics. HBT was conventionally manufactured by a combination of GaAs and AlGaAs, which is a group III-V compound semiconductor, but recently, research and development of SiGe HBT using a bandgap of a base layer composed of SiGe layers smaller than Si has been actively conducted.

SiGe HBT utilizes a band gap of Ge (0.66 eV at room temperature) smaller than a band gap of Si (1.12 eV at room temperature) and a smaller band gap of SiGe mixed crystals than Si. The Si layer is used as the emitter region and the SiGe layer is used as the base region, and the band gap of the base layer is reduced with respect to the emitter layer, thereby lowering the voltage lower than the driving voltage (about 0.7 V) in the homo Si bipolar transistor. It becomes possible to drive. Here, the driving voltage refers to a state in which the voltage between the base and emitter in the active region is equal to the diffusion potential between the base and the emitter. In other words, in the NPN bipolar transistor, the energy difference between the emitter layer and the base layer is increased to some extent to suppress the injection of holes from the base layer to the emitter layer, while reducing the energy difference between the conduction band of the emitter layer and the base layer. As a result, the driving voltage can be reduced.

However, such a conventional HBT has a problem that low voltage-oriented devices are mainstream and thus cannot be used properly for high output power devices.

An embodiment of the present invention is to provide a nitride semiconductor device and a method for manufacturing the device that can be usefully used as a high output power device having excellent high current, high voltage and high temperature characteristics through the improvement of the structure of the semiconductor device.

In addition, an embodiment of the present invention to provide a nitride semiconductor device and a method of manufacturing the semiconductor device, for example, to form the base region of the HBT with an N-type semiconductor or to include a barrier layer to improve the characteristics of the semiconductor device There is another purpose.

According to an embodiment of the present invention, a nitride semiconductor device may include a semiconductor layer including a plurality of nitride based electrode bonding layers having different electrical characteristics and a plurality of barrier layers spaced apart from the electrode bonding layer; And a plurality of electrodes contacting the plurality of nitride-based electrode bonding layers and formed separately from each other.

When the plurality of nitride-based electrode bonding layers are formed of three electrode bonding layers, the barrier layer may include a first barrier layer and a second barrier layer respectively disposed between the two electrode bonding layers.

The first barrier layer and the second barrier layer may have different band gap energies.

The first barrier layer includes gallium nitride (GaN) or a material having a band gap band similar to that of the GaN, and the second barrier layer includes aluminum nitride (AlN) or a material having a band gap band similar to the AlN. Characterized in that.

When the plurality of nitride-based electrode bonding layers are formed of three electrode bonding layers, the three electrode bonding layers are in contact with the first electrode, the second electrode, and the third electrode, respectively.

The nitride-based electrode bonding layer in contact with the first electrode includes a P-type gallium nitride (P-GaN) or an N-type gallium nitride (N-GaN) material, and the nitride-based electrode junction in contact with the second electrode. The layer comprises indium gallium nitride (In _x Ga _{1 - x} N) (where x is a positive integer) or a material having a bandgap band similar to the In _x Ga _{1 - x} N and in contact with the third electrode The nitride-based electrode bonding layer is characterized in that it comprises an N-type gallium nitride (N-GaN) or N (+) gallium nitride (N ⁺ -GaN) material.

The material having a similar bandgap band to In _x Ga _{1 - x} N may be an arsenic (As) or phosphorus (P) -based compound.

Each region of the semiconductor layer in which the plurality of electrodes is formed may form a step having a different height.

The plurality of electrodes are each formed in a closed-loop form.

The plurality of electrodes may be formed of the same metal material.

In addition, the method of manufacturing a nitride semiconductor device according to an embodiment of the present invention by arranging a plurality of barrier layers spaced apart between at least three or more nitride-based electrode bonding layer having different electrical characteristics and a plurality of the nitride-based electrode bonding layer Forming a semiconductor layer; Removing a portion of the semiconductor layer to expose the nitride based electrode bonding layer disposed between the two barrier layers; Exposing the nitride-based electrode bonding layer disposed at a lower end of the barrier layer by removing a portion of the region where the nitride-based electrode bonding layer is exposed; And forming a plurality of electrodes in contact with the nitride-based electrode bonding layer disposed on the barrier layer and the two nitride-based electrode bonding layers exposed to each other.

The forming of the semiconductor layer may include forming a first barrier layer and a second barrier layer between the two electrode bonding layers, when the nitride-based electrode bonding layer includes three electrode bonding layers. .

The first barrier layer is formed of gallium nitride (GaN) or a material having a band gap band similar to the GaN, and the second barrier layer is formed of aluminum nitride (AlN) or a material having a band gap band similar to the AlN. Characterized in that it is formed to include.

When the nitride-based electrode bonding layer is composed of three electrode bonding layers, the three electrode bonding layers are in contact with the first electrode, the second electrode, and the third electrode, respectively.

The nitride-based electrode bonding layer in contact with the first electrode is formed of a P-type gallium nitride (P-GaN) or an N-type gallium nitride (N-GaN) material, and the nitride-based electrode in contact with the second electrode The electrode bonding layer is formed of indium gallium nitride (In _x Ga _{1 - x} N) (where x is a positive integer) or a material having a similar bandgap band to the In _x Ga _{1 - x} N. The nitride-based electrode bonding layer in contact with the three electrodes is formed by including an N-type gallium nitride (N-GaN) or an N (+) gallium nitride (N ⁺ -GaN) material.

According to the embodiment of the present invention, through the structural improvement of the semiconductor device it is possible to improve the characteristics of the device by supplying a myriad of electrons present in the valence band to the conduction band.

In addition, the barrier layer formed in the semiconductor device may greatly reduce the off-leakage of the device.

Furthermore, since the base region of the semiconductor device can be formed of a high quality N-type semiconductor, the characteristics of the device can be greatly improved compared to the conventional HBT.

In addition, due to the excellent material properties of the nitride semiconductor will be able to be used for high output power devices that are very excellent in high current, high voltage, high temperature characteristics.

1 is a diagram illustrating an epitaxial structure according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an energy band diagram according to the structure of FIG. 1; FIG.
3A and 3B illustrate a planar and cross-sectional structure of a nitride semiconductor device according to an embodiment of the present invention;
4 is a view illustrating a manufacturing process of the nitride semiconductor device of FIG. 3B.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a diagram illustrating an epitaxial structure according to an embodiment of the present invention, Figure 2 is a diagram showing an energy band diagram according to the structure of FIG.

The epitaxial structure of FIG. 1 substantially represents a semiconductor layer of a semiconductor device, such as a bipolar transistor and a field effect transistor (FET) that includes HBT.

1 and 2 together, according to an embodiment of the present invention, the semiconductor layer forms a multilayer structure, and each layer may include a nitride-based material. For example, an N (+) type gallium nitride (N ⁺ -GaN) 101, gallium nitride (GaN) 103, indium gallium nitride (In) on a glass substrate, a quartz substrate, a wafer, or a sapphire substrate _x Ga _{1 - x} N) 105 (where x is a positive integer), an aluminum nitride (AlN) 107 and a P-type gallium nitride (P-GaN) 109 are sequentially stacked to form a semiconductor layer. Will be able to form.

Here, N ⁺ -GaN (101), In _x Ga _{1 - x} N (105) and P-GaN (109), for example, the electrode bonding layer (101, 105) for contacting the emitter, base and collector electrodes of HBT 109, and GaN 103 and AIN 107 may operate as barrier layers 103, 107. In this case, the barrier layers 103 and 107 have a higher bandgap energy than the peripheral layer, and thus are named in the sense of forming a barrier when viewed on the energy band diagram. Furthermore, according to an embodiment of the present invention, N ⁺ -GaN 101 may be replaced with N-type gallium nitride (N-GaN) or P-type gallium nitride, and P-GaN is N-type gallium nitride (N -GaN) may be replaced. This is due to the fact that the semiconductor elements are formed in the NPN type or the PNP type to the last, and thus, the electrode bonding layer according to the embodiment of the present invention, that is, In _x Ga _{1- x} N 105, is formed on both the N-type semiconductor and the P-type semiconductor. Might apply.

In the above structure, the P-GaN (or N-GaN) 109 of the upper layer is, for example, an emitter electrode of HBT, and the base (In _x Ga _{1 - x} N 105) is located in the center. ) Electrode, and the N ⁺ -GaN 101 of the lower layer can form a collector electrode, respectively. Here, forming the emitter, the base, and the collector electrode may mean forming the electrode bonding layers 101, 105, and 109 of the semiconductor layer and the emitter, base, and collector electrodes of a conductive metal material to contact each other.

Of course, such a multilayer structure forming the semiconductor layer may be variously modified. The barrier layers 103 and 107 may be formed without departing from the technical features of the present invention, for example, to form a high band gap energy or to make the base electrode contact the electrode bonding layer, that is, the In _x Ga _{1 - x} N 105. GaN and AlN 103 and 107 may be formed to form two or more layers, respectively, so that the semiconductor layer may be formed to have various numbers of stacked structures. Of course, the above structure can be realized by using a thin film having similar bandgap energy instead of the AlN thin film and the In _x Ga _{1 - x} N thin film. For example, an arsenic (As) or phosphorus (P) -based compound semiconductor thin film having a similar bandgap band may be used instead of the In _x Ga _{1 - x} N thin film of the electrode bonding layer. Therefore, embodiments of the present invention will not be particularly limited to the stacked structure and the specific material of the semiconductor layer.

The semiconductor layer of the semiconductor device has an energy band diagram as shown in FIG. 2 according to the epitaxial structure of FIG. 1. In more detail, as shown in FIG. 2, forbidden bands are formed between the two graphs based on the Fermi level, a valence band is formed at the bottom of the graph below, and a conduction band is formed at the top of the upper graph. Done.

According to an embodiment of the present invention, a semiconductor device such as HBT may use the tunneling effect by forming In _x Ga _{1 - x} N 105 between two barrier layers 103 and 107, for example. In other words, when a bias voltage is applied to the In _x Ga _{1 -x} N 105 where the base electrode can be formed among the plurality of electrode bonding layers 101, 105, and 109, the conduction band of this portion is lowered. As shown in 2, the distance between the valence band and the conduction band of the part marked with dashed line is getting closer, and many electrons in the valence band are tunneled toward the conduction band and supplied.

Accordingly, the semiconductor device according to the embodiment of the present invention enables the device operation by using a very large number of electrons present in the valence band, and thus exhibits excellent device characteristics, as well as a thin film of GaN and AIN in the absence of voltage. By further including an InGaN thin film forming a well, a barrier can be formed to prevent leakage of current toward an emitter or collector, for example. In addition, since the P-type semiconductor is not required in the base region, contact resistance and series resistance can be reduced, thereby greatly improving device characteristics. Furthermore, due to the excellent material properties of nitride semiconductors having high bandgap energy and the like, they may be useful for high frequency, high temperature and high output power devices.

3A and 3B illustrate planar and cross-sectional structures of a nitride semiconductor device according to an embodiment of the present invention.

As shown in FIGS. 3A and 3B, the nitride semiconductor device according to the embodiment of the present invention may include the semiconductor layers 301, 303, and 305 and the plurality of electrodes 307 as, for example, HBTs.

As described above, the semiconductor layers 301, 303, and 305 include nitride-based materials such as N ⁺ -GaN (or N-GaN), GaN, In _x Ga _{1 - x} N, AlN, and P-GaN. The first and third regions may be divided on the substrate. In this case, the first to third regions form a step difference, that is, a step having different heights, and a stacked structure such that the steps are sequentially lowered from the first region to the third region according to an embodiment of the present invention. It is preferable to form, and vice versa. However, embodiments of the present invention will not be particularly limited to such a step forming structure.

3A and 3B, the first region is, for example, an emitter region of a semiconductor device, in which N ⁺ -GaN, GaN, In _x Ga _{1 - x} N, AlN and P-GaN layers 301, 303, and 305 are formed. A region stacked sequentially, a second region represents a region formed of N ⁺ -GaN, GaN, In _x Ga _{1 - x} N layers 301 and 303 as a base region, and a third region represents N- as a collector region. The region which consists only of GaN layer 301 is shown. Accordingly, as the emitter region is disposed at the center and the collector region is disposed at the outer portion, for example, the semiconductor layers 301, 303, and 305 formed on the substrate have a substantially conical or tower shape.

However, the shape may vary depending on how the first to third regions are arranged. For example, when the leftmost portion is the first region and the rightmost portion is the third region, half of the cone can be cut out. Of course, the structure in FIG. 3 is illustrated to form circular electrodes in the first to third regions of the semiconductor layers 301, 303, and 305, respectively, and is in contact with the In _x Ga _{1 - x} N layer in the second region. If the bias voltage can be applied through the voltage applying electrode, the semiconductor layers 301, 303, and 305 may be formed in any structure. For example the zone, that is, In _x Ga _{1 -} could be any number of voltage application electrode to be formed after forming the groove so as to expose only a portion of the _x N layer to the outside.

In addition, the electrode bonding layers of the semiconductor layers 301, 303, and 305 are in contact with, for example, P-GaN disposed at the top, In _x Ga _{1 - x} N layers disposed in the center region, and N-GaN layers disposed at the bottom, respectively. A plurality of electrodes 307 are separated from each other. In this case, the plurality of electrodes 307 may form a circular electrode according to an embodiment of the present invention. As such, the contact resistance may be reduced by that amount. Here, the plurality of electrodes 307 may mean, for example, emitter, base, and collector electrodes 307a, 307b, and 307c of the bipolar transistor. However, if the semiconductor device is a field effect transistor (FET), the plurality of electrodes 307 may be source, gate, and drain electrodes.

The plurality of electrodes 307 are interposed between the respective layers forming the semiconductor layers 301, 303, and 305 with an insulating layer (not shown), and each electrode bonding layer is formed through a contact hole formed on the insulating layer. It may be possible to make contact. For example, the semiconductor layers 301, 303, and 305 stacked to form the first to third regions are etched by region, more precisely, only the second and third regions, and then an insulating layer is formed thereafter. A contact hole may be formed on the insulating layer. An electrode may be formed after the contact hole is formed. At this time, the plurality of electrodes 307 is preferably formed of the same material according to an embodiment of the present invention, but since the electrode forming the base electrode may be formed of a different material in the embodiment of the present invention the electrode bonding layer and the electrode It will not specifically limit about the structure of this contact and the material of an electrode.

4 is a view illustrating a manufacturing process of the nitride semiconductor device of FIG. 3B.

Referring to FIG. 4 together with FIGS. 3A and 3B, first, a structure of semiconductor layers 301, 303, and 305 is grown on a semiconductor substrate (S401). It will be able to stacking a N _x, AlN, and P-GaN _layer, for example _{^{N + -GaN, GaN, In x}} Ga 1 as shown in Figure 3b.

Subsequently, a first photolithography process and an etching process are performed to expose the electrode bonding layers of the semiconductor layers 301, 303, and 305, that is, the In _x Ga _{1 - x} N layer, to the outside (S403 and S405). More precisely, after the structure is grown as in step S401, the photoresist film PR is applied onto the semiconductor layers 301, 303, and 305 and a mask is applied to the second and the second regions except for the first region. Three areas are exposed and developed. Subsequently, the semiconductor layers 301, 303, and 305 of the developed second and third regions are etched to expose the In _x Ga _{1 - x} N layer to the outside. As a result, the first regions of the semiconductor layers 301, 303, and 305 form a step with the second region. Here, the second and third regions mean that the internal regions of the base electrode 307b and the collector electrode 307c having a closed-loop shape are roughly illustrated in FIG. 3B.

Thereafter, a second photolithography process and an etching process are performed to expose the N ⁺ -GaN layer disposed at the lowermost portion of the semiconductor layers 301, 303, and 305 (or lower portion of the GaN barrier layer) to the outside (S407, S409). In this case, similarly to the steps S403 and S405 above, the photosensitive film is coated on the semiconductor layers 301, 303, and 305 in which the In _x Ga _1-x N layer is exposed to the outside, and a new mask is applied to the first and second layers. The third region except for the second region is exposed and developed. Thereafter, the developed semiconductor layers 301, 303, and 305 are etched to expose the N ⁺ -GaN layer to the outside. As a result, the second region and the third region of the semiconductor layers 301, 303, and 305 form a step with each other.

Thereafter, a process for forming a plurality of electrodes 307 in each layer of the semiconductor layers 301, 303, and 305 is performed (S411 and S413). For this purpose, for example, a third photolithography process is performed on the semiconductor layers 301, 303, and 305 having the first to third regions having the stepped height, thereby exposing a portion where the electrode is to be formed to the outside. Subsequently, by applying a conductive metal for forming an electrode on the photosensitive film, including the portion where the photoresist film has been removed, the metal is buried in a portion exposed to the outside to contact the electrode bonding layer. Thereafter, the photoresist film in the peripheral region except for the contacted portion is removed through a lift off process, thereby finally forming the emitter, the base, and the collector electrodes 307a, 307b, and 307c. The plurality of electrodes 307 are formed of Al, an Al alloy, chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), nickel (Ni), titanium nitride (TiN), etc. in consideration of conductivity and manufacturing cost. Could be.

Such an electrode assumes a case where the plurality of electrodes 307 are made of substantially the same metal material. If the base electrode 307b is made of a different metal material from the emitter and collector electrodes 307a and 307c, a separate photolithography process and a lift-off process for forming the electrode will be performed twice. Since the above process has been described above, further description thereof will be omitted. Furthermore, in the case of forming an electrode by applying a printing technique without separately performing a photolithography process, a plurality of electrodes 307 may be formed directly on the electrode bonding layer without the need for a separate manufacturing process. Therefore, in the embodiment of the present invention, since the manufacturing process may vary depending on how the electrode is formed, the method of forming the electrode will not be particularly limited.

Although the semiconductor device according to the embodiment of the present invention has been described as an example of HBT, it may mean any one of a conventional Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), and a Junction Gate FET (JFET). have. Therefore, the gate of the FET series element, or the base of the BJT or IGBT series element can be collectively referred to as a drive terminal or a voltage application terminal (or a drive terminal or a voltage application terminal electrode). Also, the drain of the FET-type device, the collector of the BJT, and the IGBT-type device can be referred to as the current input terminal (or the current input terminal electrode) of the semiconductor device, and the source of the FET-type device and the emitter of the BJT and IGBT- May be referred to as a lead-out terminal (or current lead-out terminal).

While the invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention.

101, 105, and 109: electrode bonding layers 103 and 107: barrier layers
301, 303, 305: semiconductor layer 307: electrode

Claims (15)

A semiconductor layer including a plurality of nitride-based electrode bonding layers having different electrical characteristics and a plurality of barrier layers spaced apart from each other; And
In contact with the plurality of nitride-based electrode bonding layer, and includes a plurality of electrodes formed to be separated from each other,
The plurality of electrodes are each formed of a closed-loop (closed-loop) form of the nitride semiconductor device. The method of claim 1,
In the case where the plurality of nitride-based electrode bonding layers are composed of three electrode bonding layers, the barrier layer includes a first barrier layer and a second barrier layer respectively disposed between the two electrode bonding layers. device. 3. The method of claim 2,
The first barrier layer and the second barrier layer is a nitride semiconductor device, characterized in that different band gap energy (band gap). 3. The method of claim 2,
The first barrier layer includes gallium nitride (GaN) or a conductive material having a band gap band similar to that of GaN,
And the second barrier layer includes aluminum nitride (AlN) or a conductive material having a band gap band similar to that of AlN. The method of claim 1,
In the case where the plurality of nitride-based electrode bonding layer is composed of three electrode bonding layer, the three electrode bonding layer is in contact with the first electrode, the second electrode and the third electrode, respectively. The method of claim 5,
The nitride-based electrode bonding layer in contact with the first electrode includes a P-type gallium nitride (P-GaN) or an N-type gallium nitride (N-GaN) material,
The nitride-based electrode bonding layer in contact with the second electrode may be formed of indium gallium nitride (In _x Ga _1-x N) (where x is a positive integer) or a band gap band similar to that of In _x Ga _1-x N. A conductive material,
The nitride-based electrode bonding layer in contact with the third electrode is a nitride semiconductor device comprising an N-type gallium nitride (N-GaN) or N (+) gallium nitride (N ⁺ -GaN) material. The method according to claim 6,
The material of the band gap band similar to In _x Ga _{1 - x} N is an arsenic (As) or phosphorus (P) -based compound, characterized in that the nitride semiconductor device. The method of claim 1,
And each region of the semiconductor layer in which the plurality of electrodes is formed to form a step having a different height. delete The method of claim 1,
And the plurality of electrodes are formed of the same metal material. Forming a semiconductor layer by disposing at least three nitride-based electrode bonding layers having different electrical characteristics and a plurality of barrier layers spaced apart from the plurality of nitride-based electrode bonding layers;
Removing a portion of the semiconductor layer to expose the nitride based electrode bonding layer disposed between the two barrier layers;
Exposing the nitride-based electrode bonding layer disposed at a lower end of the barrier layer by removing a portion of the region where the nitride-based electrode bonding layer is exposed; And
And forming a plurality of electrodes in contact with the nitride-based electrode bonding layer disposed above the barrier layer and the two nitride-based electrode bonding layers exposed to each other.
The plurality of electrodes are each formed in a closed-loop (closed-loop) shape manufacturing method of the nitride semiconductor device. 12. The method of claim 11,
Wherein forming the semiconductor layer comprises:
If the nitride-based electrode bonding layer is composed of three electrode bonding layer, the method of manufacturing a nitride semiconductor device, characterized in that each forming a first barrier layer and a second barrier layer between the two electrode bonding layer. The method of claim 12,
The first barrier layer is formed of gallium nitride (GaN) or a conductive material having a band gap band similar to that of GaN,
And the second barrier layer is formed of aluminum nitride (AlN) or a conductive material having a band gap band similar to that of AlN. 12. The method of claim 11,
When the nitride-based electrode bonding layer is composed of three electrode bonding layers, the three electrode bonding layers are in contact with the first electrode, the second electrode and the third electrode, respectively. 15. The method of claim 14,
The nitride-based electrode bonding layer in contact with the first electrode is formed of a P-type gallium nitride (P-GaN) or an N-type gallium nitride (N-GaN) material,
The nitride-based electrode bonding layer in contact with the second electrode may be formed of indium gallium nitride (In _x Ga _1-x N) (where x is a positive integer) or a band gap band similar to that of In _x Ga _1-x N. It is formed including a conductive material,
The nitride-based electrode bonding layer in contact with the third electrode is formed of a nitride semiconductor comprising an N-type gallium nitride (N-GaN) or N (+) gallium nitride (N ⁺ -GaN) material Method of manufacturing the device.

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