KR101371438B1 - Multi-bit resistive switching memory with different electrodes and fabrication method thereof - Google Patents

Abstract

Disclosed is a multi-bit resistive change memory device using different types of electrodes, and the multi-bit resistive change memory device using different types of electrodes is a multi-bit resistive change memory device using different types of electrodes, and includes a first electrode layer. ; A resistance change layer formed on the first electrode layer; A multiple electrode layer formed on the resistance change layer; And a second electrode layer formed on the multi-electrode layer, wherein the multi-electrode layer includes a plurality of electrodes electrically separated from each other, wherein the plurality of electrodes have different operating voltages for the resistance change layers. It may be formed of different materials to have.

Description

MULTI-BIT RESISTIVE SWITCHING MEMORY WITH DIFFERENT ELECTRODES AND FABRICATION METHOD THEREOF}

The present invention relates to a multi-bit resistance change memory device using a different type of electrode and a method of manufacturing the same.

Recently, due to the rapid development of portable electronic products such as smart phones and tablet PCs, the demand for flash memory as a main storage medium of these products is increasing. In order to implement a high-density flash memory, it is the most common method to reduce the size of a memory cell. International technology road-map for semiconductors (ITRS) anticipates that further reductions in the cell size of the current mainstream floating gate flash memory will reach its limits.

Next-generation non-volatile memory devices to replace them are three-dimensional charge trap flash (CTF), ferroelectric random access memory (FRAM) using ferroelectric capacitors, magnetic RAM (MRAM) using tunneling magneto-resistive (TMR) films, and chalcogenite compounds (Phase Change RAM (PRAM) using chalcogenide alloys) and Resistance Switching RAM (ReRAM) using resistance change are attracting attention.

Among them, the ReRAM device has a simple structure of metal-insulator-metal (MIM), which makes the device nano-sized and advantageous for high integration. It is possible to operate multi-bit operation that can operate with more than two bits of one cell as well as single-level operation depending on the voltage applied to the same resistance change material. Ultra high integration is possible.

Many researches have been conducted on the advantages of ReRAM, but the research direction up to now is focused on improving the performance and integration of devices such as speed and power consumption of devices. It is focused on the phenomenon of resistance change due to the change of current and applied voltage.

In particular, in order to implement a multi-bit resistance change memory device, a conventional method that implements multi-bit by applying a change of the limit current or the applied voltage is less reproducible, and there is a slight difference in resistance value between levels and time elapsed. There was a problem causing malfunction due to the change in the resistance value. Therefore, it is time to study the multi-bit operation that can ensure the reproducibility and reliability in the multi-bit resistance memory device.

The present application is to solve the above-mentioned problems of the prior art, a multi-bit resistance change memory device using a different type of electrode that can be manufactured through a highly reproducible, reliable, highly integrated and efficient manufacturing process and a method of manufacturing the same It aims to provide.

As a technical means for achieving the above technical problem, the multi-bit resistance change memory device using different types of electrodes according to the first aspect of the present application is a multi-bit resistance change memory device using different types of electrodes, An electrode layer; A resistance change layer formed on the first electrode layer; A multiple electrode layer formed on the resistance change layer; And a second electrode layer formed on the multi-electrode layer, wherein the multi-electrode layer includes a plurality of electrodes electrically separated from each other, wherein the plurality of electrodes have different operating voltages for the resistance change layers. It may be formed of different materials to have.

In addition, as a technical means for achieving the above technical problem, the multi-bit resistance change memory device manufacturing method using different types of electrodes according to the second aspect of the present application is a multi-bit resistance change memory device using different types of electrodes A manufacturing method, comprising: (a) sequentially stacking a first electrode layer, a resistance change layer, and an insulator on a substrate; (b) patterning the insulator and depositing a material corresponding to one of the plurality of electrodes on the patterned portion to form a plurality of electrodes spaced apart from each other with the insulator interposed therebetween to provide a multi-electrode layer; And (c) stacking a second electrode layer on the multi-electrode layer, wherein the plurality of electrodes may be formed of different materials so that the resistance change layer has different operating voltages for each of them.

According to the above-described problem solving means of the present application, by providing a second electrode layer electrically separating the plurality of electrodes formed of different materials on the resistance change layer and covering all of the plurality of electrodes, the resistance change layer is adjacent Multi-bit operation can be structurally and materially implemented according to material characteristics having different operating voltages depending on the material of the upper electrode, so that reproducibility, reliability, and stability are significantly higher than that of multi-bit operation through electrical control. Can be improved.

In addition, according to the above-described solution to the problem of the present application, the present invention, even if the new multi-bit resistance variable memory device can be used as it is in the existing manufacturing process technology in the manufacture of the efficient manufacturing can be achieved, thereby ensuring high marketability Can be.

1 is a schematic cross-sectional view of a multi-bit resistance variable memory device using different types of electrodes according to an exemplary embodiment of the present disclosure.
2 to 5 are schematic cross-sectional views for explaining a method of manufacturing a multi-bit resistance change memory device using different types of electrodes according to an exemplary embodiment of the present disclosure.
6 is a flowchart illustrating a method of manufacturing a multi-bit resistance variable memory device using different types of electrodes according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. It should be understood, however, that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the same reference numbers are used throughout the specification to refer to the same or like parts.

Throughout this specification, when a part is referred to as being "connected" to another part, it is not limited to a case where it is "directly connected" but also includes the case where it is "electrically connected" do.

Throughout this specification, when a member is located "on" another member, this includes not only when one member is in contact with another member but also when another member exists between the two members.

Throughout this specification, when an element is referred to as "including " an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise. The terms "about "," substantially ", etc. used to the extent that they are used throughout the specification are intended to be taken to mean the approximation of the manufacturing and material tolerances inherent in the stated sense, Accurate or absolute numbers are used to help prevent unauthorized exploitation by unauthorized intruders of the referenced disclosure. The word " step (or step) "or" step "used to the extent that it is used throughout the specification does not mean" step for.

Throughout this specification, the term " combination thereof " included in the expression of the machine form means one or more combinations or combinations selected from the group consisting of the constituents described in the expression of the machine form, And the like.

Hereinafter, a multi-bit resistive change memory device (hereinafter, referred to as 'the present multi-bit resistive change memory device') using different kinds of electrodes according to an exemplary embodiment of the present application will be described.

1 is a schematic cross-sectional view of a multi-bit resistance variable memory device using different types of electrodes according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, the multi-bit resistance change memory device includes a first electrode layer 1.

Referring to FIG. 1, the first electrode layer 1 may be a bottom electrode. In exemplary embodiments, the first electrode layer 1 may be formed of Al, Pt, Ru, Ir, Ni, TiN, Ti, Co, Cr, W, Cu, Hf, or a combination thereof.

In addition, the multi-bit resistive change memory device includes a resistive change layer 3.

Referring to FIG. 1, the resistance change layer 3 is formed on the first electrode layer 1.

The resistive change layer 3 is a layer containing a resistive switching material. When a predetermined bias is applied to the first electrode layer 1 and the second electrode layer 7, the filamentary current path is caused by the vacancy inside the resistance change layer 3 according to the applied bias. ) Or the parasitic filament current path disappears.

By the generation or dissipation of the filament current path, the resistance change layer 3 has two resistance states which are distinguished from each other. That is, the resistance becomes low when the filament current path is generated, and the resistance becomes high when the filament current path is extinguished. At this time, a set voltage is applied to generate a filament current path in the resistance change layer 3 by applying a specific voltage so that the resistance change layer 3 is in a low resistance state. The low state is a set state and the specific voltage is a set voltage. In addition, the reset operation is performed by applying another specific voltage to extinguish the parasitic filament current path so that the resistance change layer is in a high resistance state, and the high resistance of the filament current path disappears is reset. State, and the other specific voltage is a reset voltage.

For example, when the resistance change layer is in a set state, it may be recognized that 1 is stored in the resistance change nonvolatile memory device. When the resistance change layer is in a reset state, the resistance change nonvolatile memory device may be recognized. 0 may be recognized as being stored.

The resistance change layer 3 may be formed of a resistance change material having two or more resistance characteristics according to a bias application. For example, the resistance change layer 3 may be formed of a transition metal oxide (TMO), a perovskite-based material, or a chalcogenide-based material.

The perovskite-based material may be STO (SrTiO), PCMO (PrCaMnO) or GST (GeSbTe), or the like, and the chalcogenide-based material may be GeSe, Ag2S or Cu2S doped with Ag, Cu, or the like. . In addition, the transition metal oxide may be NiO, TiO 2, HfO, Nb 2 O 5, ZnO, ZrO 2, WO 3 or CoO.

The resistance change layer 3 may have different operating voltages (set voltage and reset voltage) for each of the electrodes 51, 52, and 53 having different materials to be described later. This will be described in more detail in connection with the plurality of electrodes 51, 52, and 53 while explaining the configuration of the multi-electrode layer 5.

In addition, the present multi-bit resistive change memory element includes a multi-electrode layer 5.

Referring to FIG. 1, the multi-electrode layer 5 is formed on the resistance change layer 3.

The multi-electrode layer 5 includes a plurality of electrodes 51, 52, 53 electrically separated from each other. Referring to FIG. 1, the plurality of electrodes 51, 52, and 53 are electrically separated from each other so that each of the plurality of electrodes 51, 52, and 53 is separately formed on the resistance change layer 3 and the second electrode layer 7. The plurality of electrodes 51, 52, and 53 may be electrically connected to each other by having an insulator 55 therebetween.

That is, the plurality of electrodes 51, 52, and 53 may be spaced apart from each other to individually contact the resistance change layer 3 and the second electrode layer 7. Referring to FIG. 1, the multi-electrode layer 5 may include an insulator 55 interposed between the plurality of electrodes 51, 52, and 53.

The plurality of electrodes 51, 52, and 53 are formed of different materials so that the resistance change layer 3 has different operating voltages. Here, the operating voltage may be a voltage required for converting the resistance change layer 3 into the salping set state or the reset state. The operating voltage may mean the set voltage and the reset voltage at the same time, but may also mean only the set voltage. For example, the plurality of electrodes 51, 52, and 53 may be formed of different materials so that the resistance change layer 3 has different set voltages with respect to each other.

More specifically, the plurality of electrodes 51, 52, and 53 may be formed of metal having different work functions. In the resistance change memory device, the operating voltage of the resistance change material included in the resistance change layer 3 depends on the work function value of the adjacent upper metal. The present application utilizes such characteristics of the resistance change material, and is isolated between the resistance change layer 3 and the second electrode layer 7 by an insulator 55 or the like, and different kinds of materials (ie, different work). By providing a plurality of electrodes (51, 52, 53) made of a material having a function), the filament current path is set stepwise in the resistance change layer (3) in accordance with the magnitude of the voltage applied to the resistance change memory element Or can be reset.

Thus, according to the material properties (work function) of each of the plurality of electrodes 51, 52, 53, the filament in the portion of the resistance change layer 3 in contact with each of the plurality of electrodes 51, 52, 53 correspondingly Since the operating voltages that cause the current path to be set or reset are different, single cell multi-bit operation can be easily performed by applying different operating voltages.

In particular, by structurally disposing the set voltage values according to the material characteristics of the plurality of electrodes 51, 52, 53 themselves, unstable multi-bits are realized through fine control such as voltage application as before. Rather, multi-bits can be implemented step by step according to the application of the voltage to each of the clearly set set and reset voltages, so that reproducibility and reliability can be greatly improved.

For example, as illustrated in FIG. 1, the plurality of electrodes 51, 52, and 53 have a first electrode 51 having a first set voltage V1, a second set voltage V2, and a first electrode ( And a second electrode 52 spaced apart from the second electrode 51, and a third electrode 53 spaced apart from the second electrode with the third set voltage V3. In addition, as shown in FIG. 1, the multi-electrode layer 5 is an insulating layer interposed between the first electrode 51 and the second electrode 52 and between the second electrode 52 and the third electrode 53. (55).

The multi-bit (2-bit) operation through the three electrodes 51, 52, and 53 having different material properties (work functions) will be described below with reference to FIG. 1.

First, it is assumed that V1, V2, and V3 are in a relationship of V1 < V2 < V3. Here, each of V1, V2, and V3 may be a specific value, or may be a specific numerical range. This is because in the resistance change memory, the set voltage and the reset voltage may be a numerical range having a predetermined distribution rather than a specific value.

First, in the reset state, no filament current path is formed in the resistance change layer 3. Secondly, when the set voltage of V1 is applied to the present multi-bit resistance change memory device, the filament current is applied to the corresponding portion (left side of the resistance change layer 3 as seen in FIG. 1) in contact with the first electrode 51. A path is formed. Third, when the set voltage of V2 is applied to the present multi-bit resistance change memory device, the filament current is applied to the corresponding portion (center portion of the resistance change layer 3 as seen in FIG. 1) in contact with the second electrode 52. A path is formed. Fourth, when the set voltage of V3 is applied to the present multi-bit resistance change memory device, the filament current in the corresponding portion (right side of the resistance change layer 3 as shown in Figure 1) in contact with the third electrode 53 A path is formed. By applying the set voltage, single cell 2-bit operation can be implemented.

In addition, the multi-bit resistance change memory device includes a second electrode layer (7).

Referring to FIG. 1, the second electrode layer 7 is formed on the multi-electrode layer 5.

Referring to FIG. 1, the second electrode layer 7 may be a top electrode. In exemplary embodiments, the second electrode layer 7 may be formed of Al, Pt, Ru, Ir, Ni, TiN, Ti, Co, Cr, W, Cu, Hf, or a combination thereof.

As such, the present application is based on a metal-insulator-metal (MIM) structure, which is a structure of a conventional resistance change memory, and has a set voltage and a reset voltage different according to a metal adjacent to the upper portion of the resistance change material. It is intended to realize multi-bit operation with high reliability and reproducibility by using characteristics.

More specifically, by using a different type of upper material (metal) of the present application to structurally and materially implement a resistance change memory having a different operating voltage in the same cell, thereby implementing a conventional multi-bit resistance change memory device A resistance change memory capable of more reliable and stable multi-bit operation may be provided than a method of changing a current limit or a voltage applied.

Hereinafter, a method of manufacturing a multi-bit resistive change memory device using different types of electrodes according to an exemplary embodiment of the present application will be described as 'a method of manufacturing the multi-bit resistive change memory device'. However, since the present invention relates to a method of manufacturing a multi-bit resistance change memory device using different types of electrodes according to the exemplary embodiment described above, the same reference numerals are used for the same or similar structure as the above-described salpin structure. Duplicate descriptions will be simplified or omitted.

2 to 5 are schematic cross-sectional views for explaining step by step a method of manufacturing a multi-bit resistance change memory device using different types of electrodes according to an embodiment of the present application, Figure 6 is a cross-sectional view according to an embodiment of the present application A flowchart of a method of manufacturing a multibit resistance change memory device using different types of electrodes is shown.

2 and 6, in the method of manufacturing the multi-bit resistive change memory device, the first electrode layer 1, the resistive change layer 3, and the insulator 55 are sequentially formed on a substrate (not shown). The step (S1) of laminating. Such sequential lamination may be performed through deposition by sputtering, an E-beam, an evaporator, CVD, ALD, or the like.

For reference, FIG. 2 illustrates a state in which a passivation layer 91 and a photoresist are formed on the insulator 55, which will be described later.

Also, referring to FIGS. 2, 3A to 5B, and 6, in the method of manufacturing the multi-bit resistance change memory device, the insulator 55 is patterned and one of the plurality of electrodes 51, 52, and 53 is patterned. And forming a plurality of electrodes 51, 52, and 53 spaced apart from each other with an insulator 55 therebetween by repeating the process of depositing a material corresponding to the step S2. .

As described above, the plurality of electrodes 51, 52, and 53 are formed of different materials so that the resistance change layers 3 have different operating voltages. .

More specifically, referring to FIG. 2, the step S2 may include depositing the passivation layer 91 on the insulator 55 and applying the photoresist 93 (the first step of the S2 step). Next, referring to FIGS. 3A, 4A, and 5A, in operation S2, a portion corresponding to one of the plurality of electrodes 51, 52, and 53 of the insulator 55 may be patterned through a photolithography process and an etching process. It may include a step (second step of the step S2). Next, referring to FIGS. 3B, 4B, and 5B, the step S2 may include depositing a material corresponding to one of the plurality of electrodes 51, 52, and 53 on the patterned portion and removing the passivation layer 91. (The third step of the step S2).

The first to third steps included in the step S2 may be repeated until the plurality of electrodes 51, 52, and 53 are all formed as shown in FIG. 5B.

Here, since the deposition process, the photolithography process, the etching process, and the like are obvious to those skilled in the semiconductor art, a detailed description thereof will be omitted. In other words, this multi-bit resistive change memory device is a new invention that approaches the implementation of single-cell multi-bit operation from a material and structural point of view. Therefore, high marketability can be secured.

Also, referring to FIGS. 1 and 6, the method of manufacturing the multi-bit resistance change memory device includes stacking a second electrode layer 7 on the multi-electrode layer 5 (S3). Such lamination may also be accomplished through deposition by sputtering, E-beam, evaporator, CVD, ALD, or the like.

Hereinafter, the method of manufacturing the multi-bit resistance change memory device according to the exemplary embodiment shown in FIGS. 2 and 3A to 5B will be described in more detail.

First, as shown in FIG. 2, the first electrode layer 1, the resistance change layer 3, and the insulator 55 are sequentially deposited on the prepared substrate (not shown) (S1 step).

Next, the passivation layer 91 is deposited on the insulator 55 and the photoresist 93 is applied (first step of step S2). Then, as shown in FIG. 3A, the left portion corresponding to the first electrode 51 of the insulator 55 is patterned through a photolithography process and an etching process (second step in step S2). That is, in the second step of the S2 step, the insulator 55 is patterned to form a space where the first electrode 51 is to be deposited. 3B, a material corresponding to the first electrode 51 is deposited on the patterned portion and the passivation layer 91 is removed (third step S2). This completes the formation of the first electrode 51 of the three electrodes 51, 52, 53.

Next, although not shown in FIG. 2 and FIG. 3B, the passivation layer 91 as shown in FIG. 2 is deposited on the insulator 55 and the first electrode 51 shown in FIG. 3B and a photoresist ( 93) (the first step of step S2). Then, as shown in FIG. 4A, the central portion corresponding to the second electrode 52 of the insulator 55 is patterned through a photolithography process and an etching process (second step in step S2). That is, in the second step of the S2 step, the insulator 55 is patterned so that a space in which the second electrode 52 is to be deposited is formed. Thereafter, as shown in FIG. 4B, a material corresponding to the second electrode 52 is deposited on the patterned portion and the passivation layer 91 is removed (third step in step S2). This completes the formation of the second electrode 52.

Next, although not shown in FIG. 2 and FIG. 4B, the passivation layer 91 shown in FIG. 2 is formed on the insulator 55, the first electrode 51, and the second electrode 52 shown in FIG. 4B. ) Is deposited and the photoresist 93 is applied (first step in step S2). Then, as shown in FIG. 5A, the right portion corresponding to the third electrode 53 of the insulator 55 is patterned through a photolithography process and an etching process (second step in step S2). That is, in the second step of the S2 step, the insulator 55 is patterned to form a space where the third electrode 53 is to be deposited. Thereafter, as shown in FIG. 5B, a material corresponding to the third electrode 53 is deposited on the patterned portion and the passivation layer 91 is removed (third step in step S2). This completes the formation of the third electrode 53.

After the first to third steps of the step S2 are repeated three times, the formation of the first electrode 51, the second electrode 52, and the third electrode 53 is completed, and an insulator is formed between the electrodes. 55 is disposed so that the multi-electrode layer 5 is formed on the resistance change layer 3 (see FIG. 5B).

Next, by depositing the second electrode layer 7 on the multi-electrode layer 5, the fabrication of the present multi-bit resistive change memory device as shown in FIG. 1 is completed (step S3).

It will be understood by those of ordinary skill in the art that the foregoing description of the embodiments is for illustrative purposes and that those skilled in the art can easily modify the invention without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. For example, each component described as a single entity may be distributed and implemented, and components described as being distributed may also be implemented in a combined form.

The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

1: first electrode layer 3: resistance change layer
5: multi-electrode layer 51: first electrode
52: second electrode 53: third electrode
55: insulator 7: second electrode layer
91: passivation layer 93: photoresist

Claims (8)

A multi-bit resistance change memory device using different kinds of electrodes,
A first electrode layer;
A resistance change layer formed on the first electrode layer;
A multiple electrode layer formed on the resistance change layer; And
Including a second electrode layer formed on the multi-electrode layer,
The multi-electrode layer includes a plurality of electrodes that are electrically separated from each other,
And the plurality of electrodes are formed of a material having different work functions so that the resistance change layer has different operating voltages. The method of claim 1,
And the operating voltage is a set voltage and a reset voltage. delete The method of claim 1,
The plurality of electrodes is a multi-bit resistance change memory device using different types of electrodes that are formed spaced apart from each other to be in contact with the resistance change layer and the second electrode layer individually. The method of claim 1,
The multi-electrode layer may further include an insulator interposed between the plurality of electrodes. The method of claim 1,
The plurality of electrodes may include a first electrode having a first set voltage, a second electrode formed with a second set voltage and spaced apart from the first electrode, and a spaced apart from the second electrode with a third set voltage. The third electrode,
The multi-electrode layer further includes an insulating layer interposed between the first electrode and the second electrode and between the second electrode and the third electrode. device. A method for manufacturing a multi-bit resistance change memory device using different kinds of electrodes,
(a) sequentially stacking a first electrode layer, a resistance change layer, and an insulator on the substrate;
(b) patterning the insulator and depositing a material corresponding to one of the plurality of electrodes on the patterned portion to form a plurality of electrodes spaced apart from each other with the insulator interposed therebetween to provide a multi-electrode layer; And
(c) depositing a second electrode layer on the multi-electrode layer,
And the plurality of electrodes are formed of a material having different work functions such that the resistance change layer has different operating voltages for each of the plurality of electrodes. 8. The method of claim 7,
The step (b)
(b1) depositing a passivation layer on the insulator and applying a photoresist;
(b2) patterning a portion corresponding to one of the plurality of electrodes of the insulator through a photolithography process and an etching process; And
(b3) depositing a material corresponding to one of the plurality of electrodes on the patterned portion and removing the passivation layer,
Step (b1) to (b3) is a method of manufacturing a multi-bit resistance change memory device using different types of electrodes that are repeated until all the plurality of electrodes are formed.

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