TWI622128B - Resistive random access memory, manufacturing method thereof, and operation thereof - Google Patents

Abstract

A resistive random access memory includes a first electrode, a second electrode, and a charge trapping layer. The second electrode is located on the first electrode. The charge trapping layer is between the first electrode and the second electrode. The charge trapping layer includes a first region and a second region. The first region has a first dopant and is adjacent to the first electrode. The second region has a second dopant and is adjacent to the second electrode.

Description

Resistive random access memory, manufacturing method thereof and operation thereof

The present invention relates to a memory, a method of fabricating the same, and an operation thereof, and more particularly to a resistive random access memory, a method of fabricating the same, and an operation thereof.

A memristor is a two-terminal element that uses an electric field induced resistance switch to change its resistance state. Since the change in the resistance state is non-volatile, the memristor can be applied to artificial neuromorphic synapse, fuzzy-logic components, and resistive random access memory (resistive random access memory) Access memory, RRAM) and other fields.

RRAM is widely used in the field of non-volatile memory. Because RRAM has a simple interleaved array and can be fabricated at low temperatures, RRAM has the best potential to replace existing flash memory. Although the staggered array of RRAMs can theoretically tolerate a minimum cell size of 4F ² (where F is the minimum feature size), and low temperature processes can allow stacking of memory arrays to achieve an unprecedented bulk density. However, in the 1R structure (that is, having only one resistive element), there is a sneak current passing through adjacent unselected memory cells, which seriously affects the read margin and limits The largest size of the staggered array. This problem can be solved by connecting these resistance conversion elements in series with additional nonlinear selection means. Therefore, a diode with a resistor (1D1R) and a selector with a resistor (1S1R) architecture seems to have become a major competitor in 3D (3D) stacked memory applications.

However, when the above-mentioned 1D1R and 1S1R architectures are applied to a 3D interleaved array, process problems are easily generated and cannot be practically applied to the process of 3D memory. Therefore, how to implement a non-linear resistance conversion element without the need for additional selection elements will become one of the important topics for developing 3D memory with RRAM.

The present invention provides a resistive random access memory, a method of fabricating the same, and an operation thereof, which have a non-linear resistance value and do not require additional selection elements, thereby reducing the area and thereby achieving a high-density three-dimensional stacked RRAM array.

The present invention provides a resistive random access memory, a method of fabricating the same, and an operation thereof, which do not have conventional effects of forming, filament, and ion movement, thereby achieving low power consumption.

The invention provides a resistive random access memory, comprising a first electrode, a second electrode and a charge trapping layer. The second electrode is located on the first electrode. The charge trapping layer is between the first electrode and the second electrode. The charge trapping layer includes a first region and a second region. The first region has a first dopant and is adjacent to the first electrode. The second region has a second dopant and is adjacent to the second electrode.

The present invention provides a method of manufacturing a resistive random access memory, the steps of which are as follows. A first electrode is provided. And forming a charge trapping layer on the first electrode. A second electrode is formed on the charge trap layer.

The present invention provides an operation of a memory element, the steps of which are as follows. The above resistive random access memory is provided. At a set, a positive bias is applied to the second electrode such that a plurality of electrons are injected from the first electrode into the first region of the charge trapping layer and blocked by the second region of the charge trapping layer. At the time of reset, a negative bias is applied to the second electrode such that electrons escape from the first region of the charge trapping layer to the first electrode.

Based on the above, the resistive random access memory of the present invention is only a 1R memory structure, which has a non-linear resistance value and does not require additional selection elements. Therefore, the RRAM of the present invention has a smaller area than conventional RRAMs (e.g., 1D1R and 1S1R architecture). In addition, the RRAM of the present invention can omit the initial forming-free process. Therefore, the initial generated voltage having a large voltage can be eliminated for activation to avoid damage of the RRAM structure, thereby improving reliability. On the other hand, the RRAM of the present invention does not need to form a filament and ion movement, thereby achieving low power consumption.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

10, 20‧‧‧Resistive random access memory

201‧‧‧Base

102, 202‧‧‧ first electrode

203‧‧‧ dielectric layer

104, 204‧‧‧ charge trapping layer

205‧‧‧ memory cells

106, 206‧‧‧ first area

108, 208‧‧‧ second area

110, 210‧‧‧ second electrode

D1‧‧‧ first direction

D2‧‧‧ second direction

D3‧‧‧ third direction

S‧‧‧Stack structure

1 is a cross-sectional view showing a resistive random access memory according to a first embodiment of the present invention.

2A is a perspective view of a resistive random access memory according to a second embodiment of the present invention.

2B is a schematic cross-sectional view of the memory cell of FIG. 2A.

3A to 3D are schematic diagrams showing the operation of the resistive random access memory of FIG. 1.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not be repeated.

1 is a cross-sectional view showing a resistive random access memory according to a first embodiment of the present invention.

Referring to FIG. 1, a resistive random access memory 10 according to a first embodiment of the present invention includes a first electrode 102, a charge trap layer 104, and a second electrode 110. Second electric The pole 110 is located on the first electrode 102. In an embodiment, the material of the first electrode 102 and the material of the second electrode 110 respectively comprise a conductive material, which may be formed by physical vapor deposition. The electrically conductive material can be, for example, a metallic material, a metal nitride or a similar electrically conductive material. The metal material includes at least one selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. The metal nitride includes a metal selected from the group consisting of at least one of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, and Ge. nitride. In an embodiment, the first electrode 102 and the second electrode 110 may be different materials. For example, the first electrode 102 may be a TiN layer, and the second electrode 110 may be a Ta layer. Still alternatively, the first electrode 102 may be a Ta layer, and the second electrode 110 may be an Hf layer. In another embodiment, the first electrode 102 and the second electrode 110 may be the same material. For example, the first electrode 102 and the second electrode 110 are both TiN layers or Ta layers.

The charge trap layer 104 is located between the first electrode 102 and the second electrode 110. The charge trap layer 104 includes a first region 106 and a second region 108. The first region 106 has a first dopant and is adjacent to the first electrode 102. The second region 108 has a second dopant and is adjacent to the second electrode 110.

In one embodiment, the material of the charge trapping layer 104 is an insulating material having an energy gap of less than 5 eV. The insulating material includes at least one selected from the group consisting of TiO ₂ , NiO, HfO, HfO ₂ , ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO, and Nb ₂ O ₅ . For example, the material of charge trapping layer 104 can be TiO ₂ . However, the present invention is not limited thereto. In other embodiments, the energy gap of the material of the charge trap layer 104 can be adjusted according to requirements.

In one embodiment, the first dopant and the second dopant respectively comprise a layer selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf, B, C, Mo, Zn. And at least one of the groups consisting of Mg. In an embodiment, the first dopant and the second dopant may be different. For example, the first dopant can be Al and the second dopant can be Hf. However, the present invention is not limited thereto. In other embodiments, the first dopant and the second dopant are adjusted such that the second region 108 having the second dopant has a larger energy gap than the first dopant. The energy gap of a region 106 is within the scope of the invention. In an embodiment, the energy gap of the second region 108 is at least 1 eV greater than the energy gap of the first region 106. Thus, this embodiment can enhance the electron capture capability of the first region 106 of the charge trapping layer 104 and inhibit the ionic movement in the first region 106 to maintain oxygen vacancies or other ions under application of an electric field. Fixed. On the other hand, the second region 108 of the charge trapping layer 104 can prevent or block electrons from flowing from the first region 106 (or the first electrode 102) to the second electrode 110, thereby further enhancing the electron capture capability of the first region 106. In other words, the second region 108 of the charge trapping layer 104 can control the retention of the non-volatile resistive state, thereby increasing the reliability of the resistive random access memory 10.

In an embodiment, the concentration of the first dopant in the first region 106 is between 1 at% and 50 at%. The concentration of the second dopant in the second region 108 is between 10 at% and 90 at%. In an embodiment, the first region 106 may have a thickness of about 5-15 nm, and the second region 108 may have a thickness of about 5-10 nm. However, the present invention is not limited thereto, and the thickness of the first region 106 and the second region 108 can be adjusted according to user requirements.

In an embodiment, when the first dopant is the same as the second dopant, the concentration of the first dopant in the first region 106 may be less than the concentration of the second dopant in the second region 108. However, the present invention is not limited thereto. In other embodiments, when the first dopant is different from the second dopant, the concentration of the first dopant in the first region 106 may be smaller than the second in the second region 108. The concentration of the dopant.

In another embodiment, when the first dopant is the same as the second dopant, the concentration of the first dopant in the first region 106 and the second region 108 of the charge trapping layer 104 (or the concentration of the second dopant) A gradient may be present such that the concentration of the first dopant adjacent the first electrode 102 is less than the concentration of the second dopant adjacent the second electrode 110.

The resistive random access memory 10 of the first embodiment described above may be, for example, a resistive random access memory of a planar charge trapping layer. However, the present invention is not limited thereto. In other embodiments, it may be a resistive random access memory of a stacked charge trapping layer, which is described in detail below.

2A is a perspective view of a resistive random access memory according to a second embodiment of the present invention. 2B is a schematic cross-sectional view of the memory cell of FIG. 2A.

Referring to FIG. 2A and FIG. 2B, the resistive random access memory 20 of the second embodiment of the present invention includes a substrate 201, a plurality of first electrodes 202, a plurality of dielectric layers 203, a charge trapping layer 204, and a plurality of second Electrode 210. In an embodiment, the substrate 201 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (SOI) on the insulating layer.

The first electrode 202 and the dielectric layer 203 both extend along the first direction D1 and are stacked one on another along the third direction D3 to form a stacked structure S. The material of the first electrode 202 The material and the formation method are similar to those of the first electrode 102 described above, and will not be described herein. The material of the dielectric layer 203 may be, for example, hafnium oxide, tantalum nitride or a combination thereof, and the formation method may be a chemical vapor deposition method, a thermal oxidation method, or the like.

The charge trapping layer 204 conformally and blanketly covers the surface (ie, the top and sidewall) of the stacked structure S (which includes the first electrode 202 and the dielectric layer 203 stacked one on another).

The second electrode 210 extends along the second direction D2 and conformally covers the surface (ie, the top surface and the sidewall) of the stacked structure S (which includes the first electrode 202 and the dielectric layer 203 stacked on each other). A memory cell 205 may be formed at the intersection or overlap of the first electrode 202 and the second electrode 210. The material and formation method of the second electrode 210 are similar to those of the second electrode 110 described above, and will not be described herein. In an embodiment, the first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other.

As shown in FIG. 2B, the memory cell 205 can include a portion of the first electrode 202, a portion of the charge trapping layer 204, and a portion of the second electrode 210. A portion of the charge trapping layer 204 is located on a sidewall of a portion of the first electrode 202 to form a vertical charge trapping layer. A portion of the second electrode 210 is located on the portion of the charge trapping layer 204 such that a portion of the charge trapping layer 204 is between the portion of the first electrode 202 and the portion of the second electrode 210. In detail, the charge trap layer 204 also includes a first region 206 and a second region 208. The first region 206 has a first dopant and is adjacent to the first electrode 202. The second region 208 has a second dopant and is adjacent to the second electrode 210. Due to the material, concentration, and thickness of the charge trap layer 204, the first region 206, and the second region 208 of the second embodiment, The materials, concentrations, and thicknesses of the charge trap layer 104, the first region 106, and the second region 108 of the embodiment are similar, and will not be described herein.

Next, a method of manufacturing the resistive random access memory of the present invention will be described in detail. Hereinafter, the resistive random access memory 10 of the first embodiment will be described as an example.

First, the first electrode 102 is provided. Next, a charge trap layer 104 is formed on the first electrode 102. Thereafter, the second electrode 110 is formed on the charge trap layer 104. Since the materials of the first electrode 102, the charge trap layer 104, and the second electrode 110 have been described in the above paragraphs, they will not be described again.

In an embodiment, the method of forming the charge trap layer 104 may include forming the charge trap layer 104 in situ by an atomic layer deposition process. In one embodiment, the atomic layer deposition process can be, for example, a plasma-enhanced atomic layer deposition (PEALD) process.

Specifically, the atomic layer deposition process includes performing a plurality of first deposition cycles to form a plurality of first material layers having an insulating material. Thereafter, a second deposition cycle is performed a plurality of times to form a plurality of second material layers having the first dopant. The first deposition cycle and the second deposition cycle are then repeated until a first region 106 of the charge trap layer 104 of a desired thickness is formed. In an embodiment, the number of first deposition cycles may be greater than the number of second deposition cycles. For example, 7 first deposition cycles can be performed to form a 7-layer TiO ₂ layer, after which a second deposition cycle is performed to form a 1-layer Al ₂ O ₃ layer. Next, the steps of the first deposition cycle and the 1st second deposition cycle are repeated 7 times until the thickness of the first region 106 of the charge trap layer 104 is about 10 nm. However, the invention is not limited thereto, as long as the number of times of the first deposition cycle is greater than the number of times of the second deposition cycle.

The first region 106 of the charge trapping layer 104 is formed in situ on the first electrode 102 by an atomic layer deposition process, which can adjust the thickness of the first region 106 and the Al doping amount (or doping concentration) so that the resistance The breakdown voltage, operating voltage, and operation-current level of the random access memory can be efficiently adjusted.

Likewise, after the first region 106 of the charge trapping layer 104 is formed, a third deposition cycle can be performed a plurality of times to form a plurality of third material layers having an insulating material. Next, a fourth deposition cycle is performed a plurality of times to form a plurality of fourth material layers having the second dopant. Then, the third deposition cycle and the fourth deposition cycle are repeated until a second region 108 of the charge trap layer 104 of a desired thickness is formed. In an embodiment, the number of fourth deposition cycles may be greater than the number of third deposition cycles. For example, a third deposition cycle can be performed to form a 1-layer TiO ₂ layer, after which a fourth deposition cycle is performed 9 times to form a 9-layer HfO ₂ layer. Next, the steps of the third deposition cycle and the 9th fourth deposition cycle are repeated once until the thickness of the second region 108 of the charge trap layer 104 is about 10 nm. However, the invention is not limited thereto, as long as the number of fourth deposition cycles is greater than the number of third deposition cycles.

The second region 108 of the charge trapping layer 104 is formed in situ on the first electrode 102 by an atomic layer deposition process, which can adjust the thickness of the second region 108 and the Hf doping amount (or doping concentration) so that the resistance The operating current level, resistance state retention, and equilibrium level of the random access memory are effective. The rate is adjusted.

Furthermore, since the present embodiment forms the charge trap layer in situ using an atomic layer deposition process, the formed charge trap layer can be deposited conformally and uniformly on the vertical sidewalls of the first electrode. Therefore, this atomic layer deposition process can be applied to high-density three-dimensional stacked RRAM arrays to meet the current trend of thin and light technology.

In another embodiment, the method for forming the charge trapping layer 104 may further include performing an ion implantation process to form Al to the TiO ₂ layer after forming a material layer (for example, a TiO ₂ layer) by a chemical deposition process. The first region 106 of the charge trapping layer 104 is thereby formed. Alternatively, an ion implantation process may be performed on the first region 106 by forming a material layer (for example, an HfO ₂ layer) by a chemical deposition process to dope the Ti into the HfO ₂ layer, thereby forming The second region 108 of the charge trapping layer 104.

3A to 3D are schematic diagrams showing the operation of the resistive random access memory of FIG. 1.

Hereinafter, the resistive random access memory 10 of the first embodiment will be described as an example. Referring to FIG. 3A, at the time of setting, a positive bias (for example, +4.0 V) is applied to the second electrode 110, so that a plurality of electrons are injected from the first electrode 102 of the ground (GND) into the charge trap layer 104. A region 106 is blocked by the second region 108 of the charge trapping layer 104. At this time, the resistance state of the charge trap layer 104 is changed from a high resistance state (HRS) to a low resistance state (LRS).

Referring to FIG. 3B, when the LRS is read, the second electrode 110 is paired. A read negative bias voltage (e.g., -2V) is applied such that Fowler-Nordheim (FN) electrons are injected from the second electrode 110 into the first region 106 and are supplemented by the first region 106. The sum of the captured electrons and the FN electrons is read as a low resistance state.

Referring to FIG. 3C, a negative bias (eg, -8.0 V) is applied to the second electrode 110 during reset to cause the electrons to escape from the first region 106 of the charge storage layer 104 to ground. The first electrode 102. At this time, the resistance state of the charge trap layer 104 is changed from the low resistance state (LRS) to the high resistance state (HRS).

Referring to FIG. 3D, when the HRS is read, a negative bias voltage (for example, -2 V) is applied to the second electrode 110, so that FN electrons are injected from the second electrode 110 into the first region 106 due to the first region. In Fig. 106, only the FN electrons are left and the electrons are not captured, so that they are interpreted as a high resistance state.

In summary, the resistive random access memory of the present invention is only a 1R memory structure, which has a non-linear resistance value and does not require additional selection elements. Therefore, the RRAM of the present invention has a smaller area than conventional RRAMs (e.g., 1D1R and 1S1R architecture). In addition, the RRAM of the present invention can omit the initial generation step, and therefore, the initial generated voltage having a large voltage can be eliminated for activation to avoid damage of the RRAM structure, thereby improving reliability. On the other hand, the RRAM of the present invention can also omit filament formation and ion mobility, thereby achieving low power consumption.

Further, the present invention forms an electric charge trapping layer in situ using an atomic layer deposition process. Therefore, this atomic layer deposition process can be applied to high-density three-dimensional stacked RRAM arrays to meet the current trend of thin and light technology.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (18)

A resistive random access memory comprising: a first electrode comprising a first conductive material; a second electrode comprising a second conductive material on the first electrode; a charge trapping layer located at the Between the first electrode and the second electrode, wherein the charge trapping layer comprises: a first region having a first dopant adjacent to the first electrode; and a second region having a second dopant and adjacent The second electrode, wherein an energy gap of the second region is greater than an energy gap of the first region. The resistive random access memory according to claim 1, wherein the material of the charge trap layer is an insulating material having an energy gap of less than 5 eV, and the insulating material comprises a material selected from the group consisting of TiO ₂ , NiO, HfO, and HfO _{2 .} At least one of the group consisting of ZrO, ZrO ₂ , Ta ₂ O ₅ , ZnO, WO ₃ , CoO, and Nb ₂ O ₅ . The resistive random access memory of claim 1, wherein the first dopant comprises a layer selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf At least one of the group consisting of B, C, Mo, Zn, and Mg. The resistive random access memory of claim 1, wherein the concentration of the first dopant in the first region is between 1 at% and 50 at%. The resistive random access memory of claim 1, wherein the second dopant comprises a layer selected from the group consisting of Ti, Zr, Fe, Co, Al, S, N, Ca, Cu, Pb, Sr, Hf At least one of the group consisting of B, C, Mo, Zn, and Mg. The resistive random access memory of claim 1, wherein the concentration of the second dopant in the second region is between 10 at% and 90 at%. The resistive random access memory of claim 1, wherein the energy gap of the second region is at least 1 eV greater than the energy gap of the first region. The resistive random access memory of claim 1, wherein the first dopant is different from the second dopant. The resistive random access memory according to claim 1, wherein the first dopant is the same as the second dopant, and the concentration of the first dopant in the first region is different from the second The concentration of the second dopant in the region is in a gradient distribution. The resistive random access memory of claim 1, wherein the first electrode extends along a first direction, and the second electrode extends along a second direction, the first direction and the first The two directions are substantially perpendicular to each other. The resistive random access memory according to claim 10, wherein the number of the first electrodes is plural, and the first electrodes and the plurality of dielectric layers extend along the first direction, and Stacking along a third direction, wherein the charge trapping layer covers at least sidewalls of the first electrodes. The resistive random access memory of claim 11, wherein the charge trapping layer conformally covers the surfaces of the first electrodes and the dielectric layers. The resistive random access memory according to claim 11, wherein at least one memory cell is formed at an overlap of each of the first electrodes and the corresponding second electrode. A method of manufacturing a resistive random access memory, comprising: providing a first electrode; forming a charge trapping layer on the first electrode; Forming a second electrode on the charge trapping layer, wherein the method of forming the charge trapping layer comprises an atomic layer deposition process, the atomic layer deposition process comprising: performing a plurality of first deposition cycles to form a plurality of insulating materials a first material layer; performing a plurality of second deposition cycles to form a plurality of second material layers having a first dopant, wherein the number of the first deposition cycles is greater than the number of the second deposition cycles; The first deposition cycle and the second deposition cycles are repeated until a first region of the charge trap layer of a desired thickness is formed, wherein the first region is adjacent to the first electrode. The method for manufacturing a resistive random access memory according to claim 14, wherein the atomic layer deposition process further comprises: performing a plurality of third deposition cycles to form a plurality of third material layers having the insulating material; Performing a plurality of fourth deposition cycles to form a plurality of fourth material layers having a second dopant, wherein the number of the fourth deposition cycles is greater than the number of the third deposition cycles; and repeating the third The deposition cycle and the fourth deposition cycles are continued until a second region of the charge trap layer of a desired thickness is formed, wherein the second region is adjacent to the second electrode. The operation of the resistive random access memory, comprising: providing the resistive random access memory according to any one of claims 1 to 13; When set, applying a positive bias to the second electrode such that a plurality of electrons are injected from the first electrode into the first region of the charge trapping layer and blocked by the second region of the charge trapping layer; In response, a negative bias is applied to the second electrode such that the electrons escape from the first region of the charge trapping layer to the first electrode. The operation of the resistive random access memory according to claim 16, further comprising applying a read negative bias to the second electrode during reading, so that FN electrons are injected from the second electrode. An area, and the high resistance state or the low resistance state is interpreted by the sum of electrons in the first region. The operation of the resistive random access memory according to claim 16, wherein the generation is not performed until the setting or resetting is performed.