TWI597824B - Resistive random-access memory and operation of resistive random-access memory - Google Patents

Description

Resistive memory device, operation method of resistive memory device

The present disclosure relates to a memory device, and more particularly to a resistive random access memory device.

As the functionality of integrated circuits increases, so does the need for memory. Designers have focused on reducing the size of memory components and stacking more memory components in a unit area to achieve more capacity and lower cost per bit. In recent decades, due to advances in lithography, flash memory has been widely used as a large-capacity and inexpensive non-volatile memory that can store data when the power is turned off. In addition, flash memory can achieve high density by three-dimensional (3D) staggered arrays, such as using vertical NAND memory cell stacking. However, it has been found that the size of the flash memory is limited by the increase in cost.

Designers are looking for next-generation non-volatile memory, such as Magnetoresistive Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), and conductive bridges. Conductive Bridging Random Access Memory (CBRAM) and Resistive Random Access Memory (RRAM) to increase write speed and reduce power consumption. Non-volatile in the above categories In memory, RRAM has a simple structure and a simple interleaved array and can be fabricated at low temperatures, so that RRAM has the best potential to replace existing flash memory.

Although the structure of the RRAM interleaved array is simple, there are still many problems to be solved in manufacturing, especially its 3D interleaved array. If a 3D interleaved array cannot be formed, the high cost of the data storage device may not compete with the 3D NAND memory per bit cost of the RRAM.

In addition, in conventional computing devices, the working memory and the storage memory use different memory devices (for example, the working memory uses random access memory and the storage memory uses flash memory), and the device size cannot be effectively reduced.

The present disclosure provides a resistive memory device comprising: a substrate; a memory cell array comprising a plurality of vertical structures extending in a vertical direction along a surface of the substrate; a plurality of first wires, wherein the two adjacent ones of the first wires An insulating layer is disposed between the wires; a first resistance conversion layer and a second resistance conversion layer are disposed on the sidewall of the vertical structure; and the plurality of second wires extend in a direction perpendicular to the first wire; wherein the memory crystal The cell array includes a plurality of memory cells; wherein the first portion of the memory cell applies a first voltage such that the first portion of the memory cell acts as a working memory, and the second portion of the memory cell applies a second voltage The second part of the memory cell acts as a storage memory.

The present disclosure provides a resistive memory device comprising: a resistive memory device comprising: a 3D memory cell array having a plurality of vertical structures, the memory cell of the 3D memory cell array being located on a sidewall of the vertical structure Applying a first voltage to the first portion of the memory cell array such that the first portion of the memory cell acts as a working memory, and applying a second voltage to the second portion of the memory cell array to make the second portion of the memory cell Store memory.

The present disclosure provides a method for operating a resistive memory device, comprising: providing a 3D memory cell array having a plurality of vertical structures, wherein a memory cell of a 3D memory cell array is located on a sidewall of the vertical structure; and the 3D memory crystal Applying a first voltage to the first portion of the cell array to cause the first portion of the 3D memory cell array to function as a working memory; and applying a second voltage to the second portion of the 3D memory cell array to cause the second portion to be 3D The memory cell array acts as a storage memory.

102‧‧‧ wire

104‧‧‧Wire

106‧‧‧ horizontal axis

108‧‧‧ patterned metal layer

110‧‧‧ Direction

300‧‧‧Base

301‧‧‧Resistive memory device

302‧‧‧Second wire

304‧‧‧First wire

306‧‧‧First insulation

308‧‧‧Second insulation

310‧‧‧ third insulation

312‧‧‧First resistance conversion layer

314‧‧‧Second resistance conversion layer

316‧‧‧ memory cell

316‧‧‧Memory Cell Array

704‧‧‧The first part of the memory cell

706‧‧‧Second part memory cell

708‧‧‧ bit line

710‧‧‧ character line

712‧‧‧First control circuit

714‧‧‧Second control circuit

716‧‧‧ Third control circuit

718‧‧‧fourth control circuit

Figure 1 shows an ideal RRAM 3D staggered array formed from a 1D1R or 1S1R memory cell stack structure.

2A is a perspective view showing the structure of a 3D RRAM memory cell according to an embodiment of the present invention.

Fig. 2B is a cross-sectional view showing the structure of a 3D RRAM memory cell according to an embodiment of the present invention.

Figure 3 is a graph showing the current versus voltage of the RRAM of the disclosed embodiment.

Fig. 4 is a view showing the relationship between the durability and the temperature under different applied voltages of the resistive memory device of the embodiment of the present invention.

Fig. 5 is a view showing the relationship between the different set voltage reliability and the temperature of the resistive memory device of the embodiment of the present invention.

FIG. 6 is a schematic view showing the arrangement of a cell array according to an embodiment of the present invention.

The staggered array of resistive memory devices theoretically allows a minimum cell size of 4F ² (where F is the smallest component size), and the low temperature process allows the stack of memory arrays to achieve an unprecedented bulk density. However, in the 1R structure (having only one resistive element), there is a sneak current passing through adjacent unselected memory cells, which seriously affects the read margin and limits the staggered array. The maximum size is less than 64 bits.

This problem can be solved by adding a nonlinear selection device in series with these resistance conversion elements. For example, a diode has been developed with a resistor (1D1R), a selector with a resistor (1S1R), a bipolar junction transistor with a resistor (1BJT1R), a MOSFET transistor with a resistor (1T1R). Wait for the memory cell structure. In the above memory cell structure, the 1BJT1R structure and the 1T1R structure are too complicated and require a high temperature process, and are not suitable, and the complementary resistance conversion element (CRS) memory cell structure also has a problem of destructive readout. Therefore, the 1D1R structure and the 1S1R structure are more suitable for the application of the 3D interleaved array.

However, 3D interleaved arrays of 1D1R and 1S1R are still not easy to manufacture. The 1D1R and 1S1R memory cell structures are basically formed of a metal-insulator-metal-insulator-metal (MIMIM) structure. Figure 1 shows an ideal RRAM 3D staggered array formed from a 1D1R or 1S1R memory cell stack structure. The MIMIM structure of the 1D1R and 1S1R memory cell structures is formed between the wires 102 and 104 and extends along a horizontal axis 106 that is perpendicular to the sidewalls of the wires 102 and 104. However, RRAM 3D staggered arrays are typically formed in a semiconductor substrate. After the wire 102 is formed, the lithography process can only be performed from the direction 110. From direction 110 The lithography process performed may not form the patterned metal layer 108 as shown in FIG. 1, thus making the 3D interlaced array of the 1D1R and 1S1R memory cell structures unusable.

2A is a perspective view showing the structure of a 3D RRAM memory cell according to an embodiment of the present invention. Fig. 2B is a cross-sectional view showing the structure of a 3D RRAM memory cell according to an embodiment of the present invention. For the purpose of revealing that the memory cell is a 1R structure, an intermediate metal layer is not required, so a RRAM 3D staggered array can be fabricated. Moreover, since the 1R memory cell structure described herein has self-limiting current and self-rectification characteristics, it can also solve the problem of the sneak current of the 1R memory cell of the conventional RRAM 3D staggered array.

Referring to FIGS. 2A and 2B, the RRAM 301 can include a set of first wires 304 that are parallel to each other and a set of second wires 302 that are parallel to each other. The RRAM memory cell 316 structure is formed between the first wires 304 that are parallel to each other and the second wires 302 that are parallel to each other.

In an embodiment, the first wire 304 can be a word line, and the second wire 302 can be a bit line, or vice versa. The metal elements of the first wire 304 and the second wire 302 may be selected from the group consisting of Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge, and the foregoing. alloy. For example, in an embodiment, the first wire 304 can be a Ti layer and the second wire 302 can be a Ta layer. In another embodiment, the first wire 304 can be a Ta layer and the second wire 302 can be a Ti layer.

A first insulating layer 306 may be formed between the substrate 300 and the first conductive line 304, and a second insulating layer 308 is formed between the adjacent first conductive lines 304. A third insulating layer 310 may be formed on the first conductive line 304 of the uppermost layer. In some embodiments, the first insulating layer 306, the second insulating layer 308, and the third insulating layer 310 are hafnium oxide, tantalum nitride, or hafnium oxynitride. In other embodiments, the first insulating layer 306, the second insulating layer 308, and the third insulating layer 310 may be high dielectric constant materials such as Ta ₂ O ₅ , HfO ₂ , HSiO _x , Al ₂ O ₃ , InO. ₂ , La ₂ O ₃ , ZrO ₂ or TaO ₂ . The first insulating layer 306, the second insulating layer 308, and the third insulating layer 310 may be the same material, or may include different materials in other embodiments.

In some embodiments, the first wire 304, the first insulating layer 306, the second insulating layer 308, and the third insulating layer 310 form a vertical structure perpendicular to the surface of the substrate 300. The embodiment of the present invention in Figures 3A and 3B discloses that three layers of wires are included in the vertical structure, but the invention is not limited thereto, and the invention may include more wires (e.g., 4 layers of wires or more) or fewer wires. Vertical structure (for example, 2 layers of wire or less).

The first resistance conversion layer 312 and the second resistance conversion layer 314 may be formed on sidewalls of the first wire 304 and the first, second, and third insulating layers 306, 308, 310. The first resistance conversion layer 312 may be formed of an insulator having a first energy gap. The second resistance conversion layer 314 may be formed of an insulator having a second energy gap, and the second energy gap is larger than the first energy gap. In some embodiments, the first energy gap and the second energy gap can be from about 1 eV to about 9 eV. In some embodiments, the second energy gap can be at least about 0.5 eV greater than the first energy gap.

In some embodiments, the first resistance conversion layer 312 is formed of TiO ₂ and the second resistance conversion layer 314 is formed of Ta ₂ O ₅ . In other embodiments, the first resistance conversion layer 312 is formed of Ta ₂ O ₅ and the second resistance conversion layer 314 is formed of HfO ₂ .

In some embodiments, the first resistance conversion layer 314 can be formed by a deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma Enhanced chemical vapor deposition (PECVD), organometallic chemical vapor deposition (MOCVD), physical vapor deposition (PVD) or other suitable deposition methods. The second resistance conversion layer 316 may be formed by a suitable deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or organometallic chemical vapor deposition (MOCVD). Physical vapor deposition (PVD) or other suitable deposition method. In some embodiments, the first resistance conversion layer 314 can have a thickness of from about 1 nm to about 80 nm. The second resistance conversion layer 316 may have a thickness of about 1 nm to about 80 nm.

Each RRAM memory cell 316 structure is formed where the first resistance conversion layer 312 and the second resistance conversion layer 314 are in direct contact with the first wire 304. That is, as shown in FIGS. 2A and 2B, each RRAM memory cell 316 structure is located on the sidewall of the vertical structure including the first wire 304 and the first, second, and third insulating layers 306, 308, 310. In the resistance conversion layer 312 and the second resistance conversion layer 314. In some embodiments, the first wire 304 is a lower electrode layer of the resistive memory device, and the second wire 302 is an upper electrode layer of the resistive memory device.

In some embodiments, the RRAM 3D staggered array of the present disclosure includes only the 1R memory cell 316 structure. Because the 1R memory cell 316 structure disclosed herein does not require an intermediate metal layer, an RRAM 3D staggered array can be fabricated. Moreover, since the 1R memory cell 316 structure described herein has self-limiting current and self-rectification characteristics, it can also solve the problem of the sneak current of the 1R memory cell 316 of the conventional RRAM 3D staggered array. Therefore, the RRAM 3D staggered array described in the present disclosure can be used for the next generation of non-volatile memory, and has great potential to replace the flash memory device.

Figure 3 shows a current versus voltage diagram for an RRAM in accordance with an embodiment of the present disclosure. In this embodiment, the RRAM is formed by successively stacking a Ti electrode, a TiO ₂ layer, a Ta ₂ O ₅ layer, and a Ta electrode, wherein the TiO ₂ layer has a thickness of 60 nm and the Ta ₂ O ₅ layer The thickness is 20 nm.

As shown in FIG. 3, the RRAM of the disclosed embodiment can be seen to have significant self-rectifying characteristics. In addition, the RRAM is a bipolar RRAM that can be switched to a set state by applying a positive voltage and converted to a reset by applying a negative voltage. status. The RRAM can be switched to a set state by a minimum voltage of about +5V and converted to a reset state by a minimum voltage of about -4V (a voltage of +/-2V is used for reading instead of setting or resetting the device) ). Also, when the negative voltage is increased (even to -4V), the disclosed RRAM can have a current compliance limit level of less than about 10 ^-4 amps.

Fig. 4 is a view showing the relationship between the retention time and the temperature under different applied voltages of the resistive memory device of the embodiment of the present invention. As can be seen from Fig. 4, when the applied voltage is increased, the resistive memory device of the embodiment of the present invention can obtain better durability.

Fig. 5 is a graph showing the relationship between reliability and temperature under different set voltages of the resistive memory device of the embodiment of the present invention. As can be seen from Fig. 5, the resistive memory device of the embodiment of the present invention can obtain relatively good reliability. When the set voltage is 6V~7V, the reliability can reach >10 ¹⁵ cycles at room temperature. Therefore, the resistive memory device of the present invention can be used as a working memory device.

As shown in Fig. 5, when the set voltage is increased, the reliability of the resistive memory device of the embodiment of the present invention becomes poor. However, according to Figure 4, a higher applied voltage results in better durability.

According to the above, the present invention can control the operating voltage at the operating voltage Within a range smaller than the breakdown voltage and greater than the initial voltage, a portion of the memory cell in the memory cell array applies a first operating voltage as a working memory device, and another portion of the memory cell applies a second operating voltage as a Store the memory device.

The following is a schematic diagram of a configuration of a cell array according to an embodiment of the present invention. In this embodiment, the memory cell array 316 of the resistive memory device 301 is divided into a first partial memory cell 704 and a second partial memory cell 706.

In some embodiments, the first portion of the memory cell 704 is between 30% and 70% of the memory cell array 316 and the second portion of the memory cell 706 is between 30% and 70% of the memory cell array 316.

For example, in some embodiments, the first partial memory cell 704 can be 70%, the second partial memory cell 706 can be 30%, or in some embodiments, the first partial memory cell 704 can be 50%. %, the second partial memory cell 706 may be 50%, or the first partial memory cell 704 may be 30%, and the second partial memory cell 706 may be 70%. The ratio of the first portion of the memory cell 704 and the second portion of the memory cell 706 may be adjusted to be more or less depending on the needs of the product, and the present invention is not particularly limited to the first partial memory cell 704 and the second partial memory cell 706. The proportion. In some embodiments, both the first partial memory cell 704 and the second partial memory cell 706 are 3D RRAM memory cells 316 of FIGS. 2A and 2B, such that the memory device of the present invention can achieve high density requirements, and Since the first partial memory cell 704 and the second partial memory cell 706 are all the same memory cell, the switching time is the same.

The first portion of the memory cell 704 is connected to the first via a bit line 708 The control circuit is coupled to the second control circuit 714 by word line 710. The second portion of memory cell 706 is coupled to third control circuit 716 via bit line 708 and to fourth control circuit 718 by word line 710. By the operation of the first control circuit 712, the second control circuit 714, the third control circuit 716, and the fourth control circuit 718, the set voltages of the first partial memory cell 704 and the second partial memory cell 706 are different: The first portion of the memory cell 704 in the memory cell array 316 applies a first operating voltage as a working memory device and the second portion of the memory cell 706 is applied in a region where the voltage is less than the breakdown voltage and greater than the initial voltage. The second operating voltage acts as a storage memory device.

In some embodiments, the first voltage is about 6V~7V, and the second voltage is about 5V~6V. For example, in one example, the first partial memory cell 704 has a set voltage of 8V and the second partial memory cell 706 has a set voltage of 5V. Therefore, the reliability of the first portion of the memory cell 704 at a temperature of 90 ° C to 100 ° C can be greater than 10 ¹⁵ , which can be used as a working memory device, and the second portion of the memory cell 706 has a better durability. It is good enough to be used as a storage memory device.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified, replaced and retouched without departing from the spirit and scope of the invention. . Further, the scope of the present invention is not limited to the processes, machines, manufacture, compositions, devices, methods and steps in the specific embodiments described in the specification, and any one of ordinary skill in the art may disclose the invention. The present disclosure understands the processes, machines, manufacturing, material compositions, devices, methods, and steps that are presently or in the future, as long as they can perform substantially the same function or are obtained in the embodiments described herein. The same general results can be used in the present invention. Therefore, the scope of protection of the present invention should be interpreted in a broad scope or meaning.

301‧‧‧Resistive memory device

316‧‧‧Memory Cell Array

704‧‧‧The first part of the memory cell

706‧‧‧Second part memory cell

708‧‧‧ bit line

710‧‧‧ character line

712‧‧‧First control circuit

714‧‧‧Second control circuit

716‧‧‧ Third control circuit

718‧‧‧fourth control circuit

Claims (13)

A resistive memory device comprising: a substrate; a memory cell array comprising a plurality of vertical structures extending in a direction perpendicular to a surface of the substrate; a plurality of first wires, wherein the first two of the first wires are adjacent to each other An insulating layer is disposed between the wires; a first resistance conversion layer and a second resistance conversion layer are disposed on sidewalls of the vertical structures; and a plurality of second wires extend in a direction perpendicular to the first wires; wherein The memory cell array includes a plurality of memory cells; wherein the first portion of the memory cells is coupled to a first control circuit and a second control circuit, and the first control circuit and the second control circuit are configured And applying a first voltage to the first portion of the memory cells, the memory cell of the first portion is used as a working memory, and the second portion of the memory cells is connected to a third control circuit and a first a fourth control circuit, and the third control circuit and the fourth control circuit are configured to apply a second voltage to the second portion of the memory cells to make the second portion of the memory cell Storage memory, and wherein the first control circuit, second control circuit, the third control circuit and a fourth circuit is configured to simultaneously control the application of the first voltage and the second voltage. The resistive memory device of claim 1, wherein the first voltage is a pulse of 6V to 7V. The resistive memory device of claim 1, wherein the second The voltage is DC (DC) 5V~6V. The resistive memory device of claim 1, wherein the first portion of the memory cell accounts for 30% to 70% of the memory cell array. The resistive memory device of claim 1, wherein the second portion of the memory cell accounts for 30% to 70% of the memory cell array. The resistive memory device of claim 1, wherein the first voltage is smaller than the second voltage. The resistive memory device of claim 1, wherein each of the unit cells is located in the first resistance conversion layer and the second resistance conversion layer on the sidewall of the vertical structure. The resistive memory device of claim 1, wherein the first wires and the second wires comprise Ti, Ta, Ni, Cu, W, Hf, Zr, Nb, Y, Zn, Co, Al, Si, Ge or the aforementioned alloy. A method for operating a resistive memory device includes: providing a 3D memory cell array having a plurality of vertical structures, wherein the memory cells of the 3D memory cell array are located on sidewalls of the vertical structures; and the 3D memory crystals Applying a first voltage to the first portion of the cell to cause the first portion of the 3D memory cell to function as a working memory; and applying a second voltage to the second portion of the 3D memory cell to cause the second portion to be 3D The memory cell acts as a memory, wherein the first voltage and the second voltage are simultaneously applied. The method of operating a resistive memory device according to claim 9, wherein the first voltage is a pulse of 6V to 7V. The operating method of the resistive memory device as described in claim 9 The method, wherein the second voltage is direct current (DC) 5V~6V. The method of operating a resistive memory device according to claim 9, wherein the memory cell of the first portion accounts for 30% to 70% of the memory cell array. The method of operating a resistive memory device according to claim 9, wherein the second portion of the memory cell occupies 30% to 70% of the memory cell array.