KR101347026B1 - Semiconductor package sliming apparatus and method of the same - Google Patents

Semiconductor package sliming apparatus and method of the same Download PDF

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KR101347026B1
KR101347026B1 KR1020120028786A KR20120028786A KR101347026B1 KR 101347026 B1 KR101347026 B1 KR 101347026B1 KR 1020120028786 A KR1020120028786 A KR 1020120028786A KR 20120028786 A KR20120028786 A KR 20120028786A KR 101347026 B1 KR101347026 B1 KR 101347026B1
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semiconductor package
polishing
slimming
seated
vacuum
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KR1020120028786A
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Korean (ko)
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KR20130107023A (en
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배기환
김상근
이우동
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주식회사 케이엔제이
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Priority to JP2013051881A priority patent/JP2013197591A/en
Priority to TW102109771A priority patent/TW201340196A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67092—Apparatus for mechanical treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67721—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

본 발명은 반도체 패키지 슬리밍장치 및 방법에 관한 것으로서, 보다 상세하게는 반도체 패키지의 몰딩면을 연마하여 반도체 패키지의 두께를 감소시키는 반도체 패키지 슬리밍장치 및 방법에 관한 것이다.
본 발명에 의한 반도체 패키지를 슬림화하는 장치는 상기 반도체 패키지가 안착되는 테이블; 및 상기 테이블에 안착된 반도체 패키지를 연마하는 연마수단;을 포함한다. The present invention relates to a semiconductor package slimming apparatus and method, and more particularly, to a semiconductor package slimming apparatus and method for polishing the molding surface of the semiconductor package to reduce the thickness of the semiconductor package.
An apparatus for slimming a semiconductor package according to the present invention includes a table on which the semiconductor package is seated; And polishing means for polishing the semiconductor package seated on the table.

Description

반도체 패키지 슬리밍장치 및 방법{SEMICONDUCTOR PACKAGE SLIMING APPARATUS AND METHOD OF THE SAME}Technical Field [0001] The present invention relates to a semiconductor package slimming apparatus and method,

본 발명은 반도체 패키지 슬리밍장치 및 방법에 관한 것으로서, 보다 상세하게는 반도체 패키지의 몰딩면을 연마하여 반도체 패키지의 두께를 감소시키는 반도체 패키지 슬리밍장치 및 방법에 관한 것이다.
The present invention relates to a semiconductor package slimming apparatus and method, and more particularly, to a semiconductor package slimming apparatus and method for polishing the molding surface of the semiconductor package to reduce the thickness of the semiconductor package.

최근 들어, 반도체 소자 제조 기술의 개발에 따라, 단시간 내에 보다 많은 데이터를 처리하기에 적합한 반도체소자를 갖는 반도체 패키지들이 개발되고 있다.In recent years, with the development of semiconductor device manufacturing technology, semiconductor packages having semiconductor devices suitable for processing more data in a short time have been developed.

반도체 패키지는 리드프레임 또는 인쇄회로기판과 같은 기판자재(Substrate)의 패드 상에 반도체칩을 다이본딩하고 리드프레임의 리드 또는 인쇄회로기판의 단자와 반도체칩을 와이어 본딩한 후, 상기 본딩된 반도체칩 및 와이어의 연결부위를 보호하기 위해 그 주위를 수지(Epoxy Molding Compound ; EMC)로 몰딩한 것을 가리킨다.A semiconductor package is manufactured by die bonding a semiconductor chip on a pad of a substrate material such as a lead frame or a printed circuit board and wire bonding the lead of the lead frame or the terminal of the printed circuit board and the semiconductor chip, And an epoxy molding compound (EMC) around the wire to protect the connection part of the wire.

도 1 및 도 2는 일반적인 반도체 패키지(100)를 도시한 것이다. 도시된 바와 같이, 인쇄회로기판(110)상에 반도체칩(120)이 와이어 본딩되고, 몰딩부(130)가 형성된 것을 알 수 있다. 반도체 칩(120)은 웨이퍼(121)와 와이어본더(122)를 포함한다. Figures 1 and 2 illustrate a typical semiconductor package 100. As shown in the figure, the semiconductor chip 120 is wire-bonded on the printed circuit board 110 and the molding part 130 is formed. The semiconductor chip 120 includes a wafer 121 and a wire bonder 122.

그러나, 적층된 반도체 칩(120)들의 신호전달을 위해 인쇄회로기판(110)이나 리드 프레임을 이용하고, 또한 반도체 칩(120)을 보호하기 위해 수지로 몰딩한 몰딩부(130)의 형성이 불가피해 반도체 패키지(100)의 전체 두께(t0)가 상승하는 문제가 있다.However, the use of the printed circuit board 110 or the lead frame for signal transmission of the stacked semiconductor chips 120 and the formation of the molding part 130 molded by resin for protecting the semiconductor chip 120 are inevitable The total thickness t0 of the semiconductor package 100 is increased.

최근에는 전자기기의 소형화(Minimization) 및 정보통신 기기의 두께 슬림(Slim)화 추세에 대응하기 어려운 문제점이 있다.
In recent years, there has been a problem in that it is difficult to cope with the trend of miniaturization of electronic devices and slimness of information communication devices.

본 발명은 상술한 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 반도체 패키지의 몰딩면을 연마하여 반도체 패키지의 두께를 용이하게 감소시킬 수 있는 반도체 패키지 슬리밍장치 및 방법을 제공함에 있다.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor package slimming apparatus and a method which can easily reduce the thickness of a semiconductor package by polishing a molding surface of the semiconductor package.

위와 같은 기술적 과제를 해결하기 위하여 본 발명에 의한 반도체 패키지를 슬림화하는 장치는 상기 반도체 패키지가 안착되는 테이블; 및 상기 테이블에 안착된 반도체 패키지를 연마하는 연마수단;을 포함한다. In order to solve the above technical problem, an apparatus for slimming a semiconductor package according to the present invention includes a table on which the semiconductor package is seated; And polishing means for polishing the semiconductor package seated on the table.

또한 상기 테이블에는 진공홀이 형성되는 것이 바람직하다. It is also preferable that a vacuum hole is formed in the table.

또한 상기 진공홀을 통해 진공압을 인가하는 진공수단이 더 구비되는 것이 바람직하다. In addition, it is preferable that the vacuum means for applying a vacuum pressure through the vacuum hole is further provided.

또한 상기 테이블 또는 연마지석을 상대적으로 수평운동시키는 이송수단이 더 구비되는 것이 바람직하다. In addition, it is preferable that the transfer means for relatively horizontal movement of the table or abrasive grindstone is further provided.

또한 상기 연마수단은 상기 반도체 패키지를 연마하는 연마지석과, 상기 연마지석을 회전시키는 스핀들을 포함하는 것이 바람직하다. In addition, the polishing means preferably comprises a grinding wheel for polishing the semiconductor package, and a spindle for rotating the grinding wheel.

또한 상기 연마지석은 상기 반도체 패키지의 몰딩면을 연마하는 것이 바람직하다. It is preferable that the abrasive wheel grinds the molding surface of the semiconductor package.

본 발명에 의한 반도체 패키지를 슬림화하는 방법은 1) 상기 반도체 패키지를 테이블에 안착하는 단계; 및 2) 상기 테이블에 안착된 반도체 패키지를 연마하는 단계;를 포함한다. A method of slimming a semiconductor package according to the present invention comprises the steps of: 1) seating the semiconductor package on a table; And 2) polishing the semiconductor package seated on the table.

또한 상기 1)단계는, 상기 반도체 패키지를 상기 테이블에 진공흡착하는 것이 바람직하다. In addition, in the step 1), the semiconductor package may be vacuum-adsorbed to the table.

또한 상기 2)단계는, 상기 반도체 패키지를 연마지석으로 연마하는 것이 바람직하다. In addition, in step 2), it is preferable to polish the semiconductor package with abrasive grindstone.

또한 상기 2)단계는, 상기 반도체 패키지의 몰딩면을 연마하는 것이 바람직하다. In addition, in the step 2), it is preferable to polish the molding surface of the semiconductor package.

또한 상기 2)단계는, 상기 반도체 패키지가 안착된 테이블 또는 연마지석을 수평왕복운동하면서 연마하는 것이 바람직하다. In the step 2), it is preferable to polish the table or the polishing grindstone on which the semiconductor package is seated while performing a horizontal reciprocating motion.

또한 상기 2)단계는, 상기 반도체 패키지가 안착된 테이블 또는 연마지석을 수평왕복운동하면서 최종 목표 연마량을 복수번 나누어 연마하는 것이 바람직하다. In the step 2), the final target polishing amount may be divided and polished a plurality of times while horizontally reciprocating the table or polishing grindstone on which the semiconductor package is mounted.

또한 상기 2)단계는, 상기 연마지석의 폭에 따라 상기 반도체 패키지의 폭방향으로 순차적으로 복수번 나누어 연마하는 것이 바람직하다.
In the step 2), it is preferable to divide and polish a plurality of times sequentially in the width direction of the semiconductor package according to the width of the abrasive grindstone.

본 발명에 따르면, 반도체 패키지의 몰딩면을 연마하여 반도체 패키지의 두께를 용이하게 감소시킬 수 있는 효과가 있다. According to the present invention, the molding surface of the semiconductor package is polished to have an effect of easily reducing the thickness of the semiconductor package.

또한, 몰딩면을 연마하여 두께를 감소시킴으로써, 방열기능이 향상되는 효과도 있다.
In addition, by reducing the thickness by grinding the molding surface, there is also an effect that the heat radiation function is improved.

도 1은 일반적인 반도체 패키지를 나타낸 것이다.
도 2는 도 1의 A-A선 단면도를 나타낸 것이다.
도 3 및 도 4는 본 발명에 의한 슬리밍장치를 나타낸 것이다.
도 5 내지 도 7은 본 발명에 의한 슬리밍방법을 나타낸 것이다. Figure 1 shows a typical semiconductor package.
2 is a sectional view taken along the line AA in Fig.
3 and 4 show a slimming apparatus according to the present invention.
5 to 7 show a slimming method according to the present invention.

이하, 첨부된 도면을 참조하여 본 발명에 의한 슬리밍장치 및 방법을 설명한다. Hereinafter, a slimming apparatus and method according to the present invention will be described with reference to the accompanying drawings.

도 3 및 도 4를 참조하면, 본 발명에 의한 슬리밍장치(1)는 테이블(10)과, 이송수단(30)과 연마수단(20)을 포함한다. 3 and 4, the slimming device 1 according to the present invention includes a table 10, a conveying means 30 and a polishing means 20.

상기 테이블(10)은 반도체 패키지를 진공흡착하는 구성요소로서, 반도체 패키지보다 큰 면적을 갖는 플레이트 형태로서, 복수개의 진공홈(11)이 형성되어 있다. 또한 상기 진공홈(11)에는 복수의 진공홀(12)이 형성되어 있는데, 진공홀(12)은 진공압이 인가되는 진공수단(미도시)에 연결된다. The table 10 is a component for vacuum-adsorbing a semiconductor package, and has a plate shape having a larger area than the semiconductor package, and a plurality of vacuum grooves 11 are formed. A plurality of vacuum holes 12 are formed in the vacuum groove 11. The vacuum hole 12 is connected to a vacuum means (not shown) to which vacuum pressure is applied.

상기 이송수단(30)은 테이블(10)을 수평왕복운동시키는 구성요소이다. 상기 이송수단(30)은 상기 테이블(10)을 지지한 상태에서 구동원(미도시)에 의해 작동되어 안내부를 따라 수평왕복운동한다. The conveying means 30 is a component for horizontally reciprocating the table 10. The conveying means 30 is operated by a driving source (not shown) while supporting the table 10 and horizontally reciprocates along the guide portion.

상기 연마수단(20)은 상기 반도체 패키지를 연마하는 연마지석(21)과, 상기 연마지석(21)을 회전시키는 스핀들(22)을 포함한다. The polishing means 20 includes a polishing stone 21 for polishing the semiconductor package and a spindle 22 for rotating the polishing stone 21.

한편, 본 실시예(1)에서는 이송수단(30)이 테이블(100을 수평왕복운동시키지만, 이와 달리 테이블은 고정되고 연마수단을 수평왕복운동시키는 것도 가능하다. 또한 이송수단은 LM가이드나 에어실린더 등 공지의 수단을 이용할 수 있다. In the present embodiment 1, although the table 100 is horizontally reciprocated by the transfer means 30, the table may be fixed and the polishing means may be reciprocated horizontally. Further, the transfer means may be an LM guide, Or the like can be used.

이하, 슬리밍장치의 작동상태 및 슬리밍 방법을 설명한다. Hereinafter, the operation state of the slimming device and the slimming method will be described.

도 5를 참조하면, 먼저, 반도체 패키지(100)를 테이블(10)에 진공흡착하고, 설정된 연마량에 따라 연마지석(21)을 하강한다. 이 상태에서 연마지석(21)을 회전하면서 테이블(10)을 수평이동시켜 반도체 패키지(100)를 연마하면 반도체 패키지가 슬림화되는 것이다. Referring to FIG. 5, first, the semiconductor package 100 is vacuum-adsorbed to the table 10, and the polishing grindstone 21 is lowered according to the set polishing amount. In this state, if the semiconductor package 100 is polished by horizontally moving the table 10 while rotating the abrasive grind 21, the semiconductor package becomes slim.

또한, 목표 연마량을 한번에 연마하는 것도 가능하지만, 이 경우, 반도체 패키지에 무리를 줄 수 있기 때문에 목표 연마량을 복수번 나누어 연마할 수 있다. 이 경우, 이송수단이 테이블(10)을 수평왕복운동시키면서 연마지석(21)을 단계에 맞춰 조금씩 하강시켜 최종적으로 목표 연마량을 연마한다. In addition, although the target polishing amount can be polished at once, in this case, since the semiconductor package can be overwhelmed, the target polishing amount can be divided and polished a plurality of times. In this case, while the conveying means moves the table 10 in a horizontal reciprocating motion, the grinding grindstone 21 is lowered little by little in step to finally polish the target polishing amount.

도 6을 참조하면, 연마지석(21)의 폭(t1)이 반도체 패키지의 폭(t2)보다 작은 경우, 반도체 패키지(100)를 연마지석(21)의 폭에 따라 복수번 나누어 연마할 수 있다. 이 경우, 테이블(10)을 수평왕복운동시키는 이송수단 이외에 이송수단의 이송방향과 직교되는 방향으로 테이블(10)을 이동시키거나 또는 연마지석(21)을 전후진시키는 제2이송수단(미도시)이 별도로 구비되어야 한다. Referring to FIG. 6, when the width t1 of the abrasive grindstone 21 is smaller than the width t2 of the semiconductor package, the semiconductor package 100 may be divided and polished a plurality of times according to the width of the abrasive grindstone 21. . In this case, in addition to the conveying means for horizontally reciprocating the table 10, a second conveying means (not shown) for moving the table 10 in the direction orthogonal to the conveying direction of the conveying means or advancing the grinding wheel 21 back and forth. ) Shall be provided separately.

도 7을 참조하면, 본 발명은 반도체 패키지(100)의 몰딩면을 연마하여 슬림화한다. 반도체 패키지(100)의 두께 감소량(t3)은 필요에 따라 설정할 수 있는데, 몰딩부(130) 이외에 경우에 따라서는 반도체칩(120)의 웨이퍼(121)의 일부를 연마하는 것도 가능하다. Referring to FIG. 7, the molding surface of the semiconductor package 100 is polished and slimmed. Although the thickness reduction amount t3 of the semiconductor package 100 can be set as needed, it is also possible to grind a part of the wafer 121 of the semiconductor chip 120 in some cases other than the molding part 130.

본 실시예에서는 인쇄회로기판 상에 반도체칩이 실장된 반도체 패키지를 슬리밍하는 장치 및 방법을 설명하였으나, 본 발명에 의한 슬리밍장치 및 방법은 반도체칩이 리드프레임상에 실장된 반도체 패키지의 슬리밍에도 동일하게 적용할 수 있는 것은 당연하다.
In the present embodiment, an apparatus and a method for slimming a semiconductor package mounted with a semiconductor chip on a printed circuit board have been described. However, the slimming apparatus and method according to the present invention are also applicable to slimming of a semiconductor package mounted on a lead frame It is natural that it can be applied to.

1: 슬리밍장치 10: 테이블
11: 진공홈 12: 진공홀
20: 연마수단 21: 연마지석
22: 스핀들 30: 이동수단1: Slimming device 10: Table
11: Vacuum groove 12: Vacuum hole
20: Polishing means 21: Polishing stone
22: spindle 30: moving means

Claims (13)

반도체 패키지를 슬림화하는 장치에 있어서,
상기 반도체 패키지가 안착되는 테이블;
상기 테이블에 안착된 반도체 패키지를 연마하는 연마수단; 및
상기 테이블 또는 연마지석을 상대적으로 수평운동시키는 이송수단;을 포함하며,
상기 연마수단은 상기 반도체 패키지를 연마하는 연마지석과, 상기 연마지석을 회전시키는 스핀들을 포함하고,
상기 연마지석은 상기 반도체 패키지의 몰딩면을 연마하는 것을 특징으로 하는 반도체 패키지 슬리밍장치.
An apparatus for slimming a semiconductor package,
A table on which the semiconductor package is seated;
Polishing means for polishing a semiconductor package seated on the table; And
Includes; conveying means for relatively horizontal movement of the table or grinding wheel,
The polishing means includes a grinding wheel for polishing the semiconductor package, and a spindle for rotating the grinding wheel,
Wherein the abrasive wheel grinds the molding surface of the semiconductor package.
제1항에 있어서,
상기 테이블에는 진공홀이 형성되는 것을 특징으로 하는 반도체 패키지 슬리밍장치.
The method of claim 1,
And a vacuum hole is formed in the table.
제2항에 있어서,
상기 진공홀을 통해 진공압을 인가하는 진공수단이 더 구비되는 것을 특징으로 하는 반도체 패키지 슬리밍장치.


3. The method of claim 2,
And a vacuum means for applying a vacuum pressure through the vacuum hole.


삭제delete 삭제delete 삭제delete 반도체 패키지를 슬림화하는 방법에 있어서,
1) 상기 반도체 패키지를 테이블에 진공흡착하는 단계; 및
2) 상기 테이블에 안착된 반도체 패키지의 몰딩면을 연마지석으로 연마하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지 슬리밍방법.


A method of slimming a semiconductor package,
1) vacuum adsorbing the semiconductor package on a table; And
And 2) polishing the molding surface of the semiconductor package seated on the table with an abrasive grindstone.


삭제delete 삭제delete 삭제delete 제7항에 있어서,
상기 2)단계는,
상기 반도체 패키지가 안착된 테이블 또는 연마지석을 수평왕복운동하면서 연마하는 것을 특징으로 하는 반도체 패키지 슬리밍방법.
The method of claim 7, wherein
Step 2),
A semiconductor package slimming method, characterized in that the polishing while the horizontal reciprocating movement of the table or the abrasive grind on which the semiconductor package is seated.
제11항에 있어서,
상기 2)단계는, 상기 반도체 패키지가 안착된 테이블 또는 연마지석을 수평왕복운동하면서 최종 목표 연마량을 복수번 나누어 연마하는 것을 특징으로 하는 반도체 패키지 슬리밍방법.
12. The method of claim 11,
In the step 2), the semiconductor package slimming method, characterized in that the final target polishing amount is divided and polished a plurality of times while horizontally reciprocating the table or polishing grindstone on which the semiconductor package is seated.
제11항에 있어서,
상기 2)단계는, 상기 연마지석의 폭에 따라 상기 반도체 패키지의 폭방향으로 순차적으로 복수번 나누어 연마하는 것을 특징으로 하는 반도체 패키지 슬리밍방법.
12. The method of claim 11,
In the step 2), the semiconductor package slimming method, characterized in that the polishing is divided into a plurality of times in sequence in the width direction of the semiconductor package according to the width of the abrasive grind.
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KR20050001049A (en) * 2003-06-26 2005-01-06 삼성전자주식회사 Semiconductor device vacuum block for solder ball attaching device

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JPH1142540A (en) * 1997-07-28 1999-02-16 Tokyo Seimitsu Co Ltd Work method for semiconductor wafer and device thereof
KR20050001049A (en) * 2003-06-26 2005-01-06 삼성전자주식회사 Semiconductor device vacuum block for solder ball attaching device

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