TWI730010B - Pre-molded active ic of passive components to miniaturize system in package - Google Patents

Pre-molded active ic of passive components to miniaturize system in package Download PDF

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TWI730010B
TWI730010B TW105135243A TW105135243A TWI730010B TW I730010 B TWI730010 B TW I730010B TW 105135243 A TW105135243 A TW 105135243A TW 105135243 A TW105135243 A TW 105135243A TW I730010 B TWI730010 B TW I730010B
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Taiwan
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integrated circuit
passive devices
die
sealing platform
substrate
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TW105135243A
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Chinese (zh)
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TW201733031A (en
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郭貿
約翰 邁耶斯
佘勇
劉賓
譚凌彥
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美商英特爾公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A system in package and method of making as system in package. The system in package has a substrate with a plurality of passive devices mounted thereon. A molding compound envelopes the plurality of passive devices to define a flat surface substantially parallel to a surface of the substrate. A plurality of integrated circuit dies is coupled successively to the flat surface.

Description

用以微型化系統級封裝的被動組件之預模鑄主動積體電路Pre-molded active integrated circuit for passive components of miniaturized system-in-package

本發明之實施例係有關於系統級封裝(SIP)。更特定地，本發明之實施例係有關於降低的區域SIP。 The embodiments of the present invention are related to system-in-package (SIP). More specifically, the embodiment of the present invention relates to a reduced area SIP.

由於在小型形狀因素中的改進性能，系統級封裝(SIP)係變得越來越受歡迎。SIP將主動積體電路(IC)晶粒與分散組件，亦稱為被動元件或被動裝置，整合於一單一封裝中。SIP的裝配程序係相當複雜，而其複雜性在需要大量被動裝置處更是加劇。在一些情況下，在單一SIP中可能有多達200個被動裝置。被動裝置，本文亦稱為「被動元件」，包括電容器、電感器、電阻器、電壓調整器、變壓器及其類似者。 Due to improved performance in small form factors, system-in-package (SIP) systems are becoming more and more popular. SIP integrates active integrated circuit (IC) dies and discrete components, also known as passive components or passive devices, into a single package. The SIP assembly procedure is quite complicated, and its complexity is exacerbated where a large number of passive devices are required. In some cases, there may be as many as 200 passive devices in a single SIP. Passive devices, also referred to herein as "passive components", include capacitors, inductors, resistors, voltage regulators, transformers, and the like.

歷史上，主動IC係耦接至印刷電路板之表面上並線接合至其上。被動元件係分佈於電路板上之IC周圍。因此，大量被動元件的需求顯著增加SIP在x及y中之維度。逐漸地，SIP被用於更小及更薄的形狀因素，諸如智慧型手機、平板及其他行動裝置。因此，在x及y維度兩者中且亦在z維度中的尺寸變成關鍵因素。 Historically, active ICs have been coupled to the surface of a printed circuit board and wire bonded to it. Passive components are distributed around the IC on the circuit board. Therefore, the demand for a large number of passive components significantly increases the dimensions of SIP in x and y. Gradually, SIP is used for smaller and thinner form factors, such as smartphones, tablets, and other mobile devices. Therefore, the size in both the x and y dimensions and also in the z dimension becomes a key factor.

為了試圖降低尺寸，一些人已嘗試將一百分比之被動元件嵌入印刷電路板(PCB)，以至於更少元件在表面上，藉以降低x及y維度。然而，此種可能的解決方案顯著增加製造基體之成本及複雜度，增加了成本並降低產量。 In an attempt to reduce the size, some people have tried to embed a percentage of passive components on a printed circuit board (PCB) so that fewer components are on the surface, thereby reducing the x and y dimensions. However, this possible solution significantly increases the cost and complexity of manufacturing the substrate, increases the cost and reduces the yield.

另一個建議的解決方案係使用一中介層以安裝被動元件及特定應用積體電路(ASIC)。組合ASIC及被動元件之路由需求通常需要六或更大級別的中介層，其顯著增加z維度。該中介層可接著附接至其他主動IC之堆疊的頂部並線接合至該基體。線接合及信號路徑之長度可負面地影響信號品質。此外，中介層之成本，加上z維度的顯著增加，使得此解決方案不適合於許多應用。 Another proposed solution is to use an interposer to mount passive components and application-specific integrated circuits (ASIC). The routing requirements for combining ASICs and passive components usually require six or more levels of interposer, which significantly increases the z-dimension. The interposer can then be attached to the top of the stack of other active ICs and wire bonded to the substrate. Wire bonding and the length of the signal path can negatively affect signal quality. In addition, the cost of the interposer, coupled with the significant increase in the z-dimension, makes this solution unsuitable for many applications.

另一建議是將IC晶粒直接放置於被動元件上方。為了實現這一點，支撐晶粒的被動元件需要實質上共平面。要確保該等多個被動元件的水平高度係相當困難。線接合程序期間之可能的傾斜引起顯著擔心。此外，初始晶粒及將晶粒之表面附接至該等被動元件的晶粒附接薄膜必須夠厚，以避免使堆疊中之該晶粒或其他晶粒破裂。普遍地，使用此種技術之大量製造尚未找到可行之處。 Another suggestion is to place the IC die directly above the passive component. To achieve this, the passive components supporting the die need to be substantially coplanar. It is quite difficult to ensure the level of these multiple passive components. The possible tilt during the wire bonding procedure raises significant concerns. In addition, the initial die and the die attach film that attaches the surface of the die to the passive components must be thick enough to avoid cracking the die or other die in the stack. Generally, mass manufacturing using this technology has not yet found a feasible place.

依據本發明之一實施例，係特地提出一種系統級封裝，包含：一基體；複數個被動裝置，其安裝於該基體上；一模鑄化合物，其包封該等複數個被動裝置以 界定出實質上平行於該基體之一表面的一平坦表面；以及複數個積體電路晶粒，其相繼耦接至該平坦表面。 According to an embodiment of the present invention, a system-in-package is specifically proposed, including: a substrate; a plurality of passive devices mounted on the substrate; a molding compound that encapsulates the plurality of passive devices to A flat surface substantially parallel to a surface of the substrate is defined; and a plurality of integrated circuit dies are sequentially coupled to the flat surface.

100:系統級封裝(SIP) 100: System in Package (SIP)

102:基體 102: matrix

104:被動裝置 104: Passive device

106:模鑄化合物 106: Molding compound

108-1~108-n:晶粒附接薄膜(DFA) 108-1~108-n: Die Attached Film (DFA)

110、110-1~110-n:積體電路晶粒、晶粒、IC 110, 110-1~110-n: integrated circuit die, die, IC

114:被動裝置 114: Passive device

116:水平表面、平台表面 116: horizontal surface, platform surface

120:接合墊 120: Bonding pad

126:電氣接點、接點 126: Electrical contacts, contacts

202、204、206、208、210、212、214、216:區塊 202, 204, 206, 208, 210, 212, 214, 216: block

300:印刷電路板、PCB 300: Printed circuit board, PCB

302:平台 302: Platform

312、314:鋸線 312, 314: Saw wire

320:接觸點 320: touch point

330:針點模具 330: Needle Point Mould

332:導管 332: Catheter

334:機械臂 334: Robotic Arm

336:基體 336: base

402:被動元件 402: Passive Components

408-1~408-n:晶粒附接薄膜 408-1~408-n: die attach film

410、s410-1~410-n:ASIC 410, s410-1~410-n: ASIC

1000:電腦系統、電子系統 1000: Computer system, electronic system

1010:積體電路 1010: Integrated Circuit

1011:積體電路 1011: Integrated Circuit

1012:處理器 1012: processor

1013:雙處理器 1013: dual processor

1014:通訊電路 1014: communication circuit

1015:雙通訊電路 1015: Dual communication circuit

1016:晶粒上記憶體、嵌入式晶粒上記憶體 1016: On-die memory, embedded on-die memory

1017:雙晶粒上記憶體、嵌入式晶粒上記憶體 1017: Dual on-die memory, embedded on-die memory

1020:系統匯流排 1020: system bus

1030:電壓源 1030: voltage source

1040:外部記憶體 1040: External memory

1042:主記憶體 1042: main memory

1044:硬驅動機 1044: Hard Drive

1046:可移動媒體 1046: Removable media

1048:嵌入式記憶體 1048: Embedded memory

1050:顯示裝置 1050: display device

1060:音訊輸出 1060: Audio output

1070:輸入裝置 1070: input device

本發明之實施例係藉由實例之方式而非藉由限制之方式闡示於隨附圖式之圖中，其中類似的引用指出相似的元件。應注意到對本揭示內容中之「一」或「一個」實施例的不同引用不一定為相同實施例，且該等引用意指至少一個。 The embodiments of the present invention are illustrated in the accompanying drawings by way of example rather than by way of limitation, in which similar references indicate similar elements. It should be noted that different references to "a" or "one" embodiment in this disclosure are not necessarily the same embodiment, and such references mean at least one.

圖1為根據本發明之一個實施例的一系統級封裝之圖表。 FIG. 1 is a diagram of a system-in-package according to an embodiment of the present invention.

圖2為根據本發明之一個實施例的一系統級封裝之產生的流程圖。 FIG. 2 is a flowchart of the generation of a system-in-package according to an embodiment of the present invention.

圖3A顯示出根據本發明之一個實施例的通道模鑄。 Figure 3A shows channel molding according to one embodiment of the present invention.

圖3B顯示出一個別基體及平台被切割成片後的一實例。 Figure 3B shows an example after a separate substrate and platform are cut into pieces.

圖3C顯示出在本發明之一實施例中的接腳模鑄。 Figure 3C shows the pin molding in one embodiment of the present invention.

圖4為本發明之一替代實施例的一圖表。 Figure 4 is a diagram of an alternative embodiment of the present invention.

圖5為根據本發明之一個實施例的一系統之一方塊圖。 Fig. 5 is a block diagram of a system according to an embodiment of the present invention.

圖1為根據本發明之一個實施例的一系統級封裝之圖表。一基體102具有多個耦接至其上的被動裝置 104。可使用慣用表面安裝技術將該等被動裝置104耦接至該基體。一模鑄化合物106包封該等被動裝置104並提供具有一水平(實質上平面)表面116的一平台。額外的被動裝置114，特別是具有z維度比模鑄化合物106之平台的z維度更大的被動裝置，被直接附接至基體102，但未包裝在模鑄化合物106中。 FIG. 1 is a diagram of a system-in-package according to an embodiment of the present invention. A substrate 102 has a plurality of passive devices coupled to it 104. The passive devices 104 can be coupled to the base using conventional surface mounting technology. A molding compound 106 encapsulates the passive devices 104 and provides a platform with a horizontal (substantially planar) surface 116. The additional passive device 114, especially the passive device having a z-dimension larger than the z-dimension of the platform of the molding compound 106, is directly attached to the base 102, but is not packaged in the molding compound 106.

水平表面116容許佔用相同x-y空間做為該等被動元件104的積體電路(IC)晶粒110-1...110-n(一般為110)之安裝，而未有先有技術解決方案所伴隨的問題。第一晶粒110-1與一層晶粒附接薄膜(DAF)108-1一起耦接至平台表面116。後續晶粒，例如晶粒110-2，係與DAF 108-2一起耦接至晶粒110-1的頂面。一任意數目之晶粒110可被附接。在一些實施例中，所有晶粒110為相同尺寸及厚度。例如，晶粒110-1至110-n可全部為記憶體晶粒，例如NAND快閃記憶體。在其他實施例中，不同尺寸之晶粒可出現在晶粒堆疊中。不像先前技術需要更厚的DAF及晶粒，當IC直接覆蓋被動元件時，平台106提供一水平表面以補償該等被動裝置104中的不同高度，並容許均勻厚度DAF被使用在整個裝置中。該等IC 110係在接合墊120處線接合至基體102。一旦所有組件附接至該基體，進一步的模鑄被進行以包裝保護該等晶粒及線接合。可使用任何慣用封裝程序。 The horizontal surface 116 allows the same xy space to be used for the installation of the integrated circuit (IC) dies 110-1...110-n (generally 110) of the passive components 104 without prior technical solutions. Accompanying problems. The first die 110-1 is coupled to the platform surface 116 together with a layer of die attach film (DAF) 108-1. Subsequent die, such as die 110-2, is coupled to the top surface of die 110-1 together with DAF 108-2. An arbitrary number of die 110 can be attached. In some embodiments, all the dies 110 have the same size and thickness. For example, the dies 110-1 to 110-n may all be memory dies, such as NAND flash memory. In other embodiments, dies of different sizes may appear in the die stack. Unlike the prior art, which requires thicker DAF and die, when the IC directly covers the passive components, the platform 106 provides a horizontal surface to compensate for the different heights in the passive devices 104, and allows uniform thickness DAF to be used in the entire device . The ICs 110 are wire-bonded to the base 102 at the bonding pad 120. Once all components are attached to the substrate, further molding is performed to package and protect the die and wire bonds. Any customary packaging program can be used.

基體102提供多個電氣接點126以促進SIP 100與外部裝置之間的信號傳遞。接點126可配置為平面 網格陣列(LGA)、球形網格陣列(BGA)或任何其他慣用配置。 The base 102 provides a plurality of electrical contacts 126 to facilitate signal transmission between the SIP 100 and external devices. Contact 126 can be configured as a plane Grid Array (LGA), Ball Grid Array (BGA) or any other conventional configuration.

圖2為根據本發明之一個實施例的一系統級封裝之產生的流程圖。在區塊202，進行判定一特定應用積體電路(ASIC)是否要被包括在SIP的模鑄化合物內。在區塊204，若該ASIC要被包括，則該ASIC係耦接至基體。在區塊206，被動裝置在該ASIC周圍(若ASIC已被包括)或簡單地在可進行模鑄的群組中被耦接至該基體。該等被動裝置可使用慣用表面安裝技術耦接至該基體。該ASIC可與DAF一起被耦接並線接合至該基體。在一些情況下，超過一個ASIC可堆疊在該基體上，其間具有DAF之層體。聚合的ASIC堆疊之z維度不應超過一所需平台高度所限制的一臨界值。 FIG. 2 is a flowchart of the generation of a system-in-package according to an embodiment of the present invention. In block 202, it is determined whether an application-specific integrated circuit (ASIC) is to be included in the molding compound of the SIP. In block 204, if the ASIC is to be included, the ASIC is coupled to the substrate. At block 206, passive devices are coupled to the substrate around the ASIC (if the ASIC is included) or simply in a group that can be molded. The passive devices can be coupled to the substrate using conventional surface mounting technology. The ASIC can be coupled with the DAF and wire bonded to the base. In some cases, more than one ASIC may be stacked on the substrate with a layer of DAF in between. The z-dimension of the aggregated ASIC stack should not exceed a critical value limited by a required platform height.

在區塊208，一模鑄化合物被引入以包封被動元件及選擇性ASIC以形成具有一實質上平面暴露表面之一平台。此模鑄可使用各種低壓慣用模鑄技術及一環氧樹脂進行。例如，通道流模鑄及針點澆口模鑄兩者都合適。在通道模鑄的情況下，一模具沿著一聚合基體被放置在一「通道」上方，且模鑄化合物係沿著該通道流動，包封其中的該等裝置。該模鑄化合物接著被固化成一固態穩定形式。各別基體可接著從較大的整體被切割成片。關於針點澆口模鑄，一模具被放置在一個基體之一分散區域上方；該模鑄化合物透過一針點澆口被引入，並在該模具內固化。理想上是希望使用不需後續程序以達成平面表面的 模鑄技術。然而，其他模鑄技術係在本發明之實施例的範圍及預期內。 At block 208, a molding compound is introduced to encapsulate passive components and optional ASICs to form a platform with a substantially planar exposed surface. This molding can be performed using various low-pressure conventional molding techniques and an epoxy resin. For example, both channel flow molding and pin point gate molding are suitable. In the case of channel molding, a mold is placed along a polymer matrix above a "channel", and the molding compound flows along the channel to encapsulate the devices. The molding compound is then cured into a solid stable form. The individual substrates can then be cut into pieces from the larger whole. Regarding pin-point gate molding, a mold is placed over a dispersed area of a matrix; the molding compound is introduced through a pin-point gate and solidifies in the mold. Ideally, you want to use those that do not require subsequent procedures to achieve a flat surface Die casting technology. However, other die casting techniques are within the scope and expectations of the embodiments of the present invention.

在該模鑄化合物被引入至該等被動裝置周圍後，當樹脂被固化以形成一穩定平台時，模鑄係在區塊208完成。在決定區塊210，進行判定除了含括在該平台的被動裝置外，是否需要有額外的被動裝置。在區塊214，若需要額外的被動裝置，該等被動裝置被安裝在該基體上。在區塊216，晶粒堆疊係附接至該平台之頂部。在一實施例中，DAF被用來將一第一晶粒附接至該平台之暴露平面表面。後續的DAF之層體被用來將後續IC晶粒附接至一堆疊。一任意數目之晶粒可被如此堆疊、被所需z維度所限制、並與該基體連接。在區塊218，該等晶粒係使用慣用線接合技術予以線接合至該基體。之後，該SIP可使用慣用半導體封裝技術予以密封在一封裝體中。 After the molding compound is introduced around the passive devices, when the resin is cured to form a stable platform, the molding is completed at block 208. In the decision block 210, it is determined whether additional passive devices are required in addition to the passive devices included in the platform. In block 214, if additional passive devices are required, the passive devices are installed on the substrate. At block 216, the die stack is attached to the top of the platform. In one embodiment, DAF is used to attach a first die to the exposed planar surface of the platform. Subsequent layers of DAF are used to attach subsequent IC dies to a stack. An arbitrary number of dies can be stacked in this way, limited by the required z-dimension, and connected to the substrate. In block 218, the dies are wire-bonded to the substrate using conventional wire-bonding techniques. After that, the SIP can be sealed in a package using conventional semiconductor packaging technology.

圖3A顯示出根據本發明之一個實施例的通道模鑄。提供具有多個晶片位置之一印刷電路板300。一通道模具覆蓋於PCB 300上，而模鑄化合物沿著通道向下流動，將裝置包封在該模具內。在所顯示之實例中，模鑄化合物在y方向上流動。在該模鑄化合物固化之後，具有安裝平台之個別基體係沿著鋸線312及314被切割成片。 Figure 3A shows channel molding according to one embodiment of the present invention. A printed circuit board 300 having a plurality of wafer positions is provided. A channel mold covers the PCB 300, and the molding compound flows down the channel, encapsulating the device in the mold. In the example shown, the molding compound flows in the y direction. After the molding compound is cured, the individual base systems with mounting platforms are cut into pieces along the saw lines 312 and 314.

圖3B顯示出一個別基體及平台被切割成片後的一實例。平台302如上所述包裝被動裝置。區域308及306亦如上所述被用以線結合積體電路及安裝額外的被動元件。接觸點320容許基體被耦接至一較大系統中。 Figure 3B shows an example after a separate substrate and platform are cut into pieces. The platform 302 packs passive devices as described above. The areas 308 and 306 are also used to wire-bond integrated circuits and install additional passive components as described above. The contact point 320 allows the substrate to be coupled into a larger system.

圖3C顯示出在本發明之一實施例中的針點澆口模鑄。一機械臂334於一基體336上方移動針點模具330。模鑄化合物流動通過導管332並填充模具，該模具包封含括於其中之被動裝置。針點澆口模鑄需要比上述通道模鑄實例稍大的區域包圍基體336上之模具330。然而，其特別適用於需要在平台的所有側上具有接點及最終晶粒堆疊的情況。 Figure 3C shows a pin point gate die casting in one embodiment of the present invention. A mechanical arm 334 moves the needle point mold 330 above a base 336. The molding compound flows through the conduit 332 and fills the mold, which encloses the passive device contained therein. Pin-point gate molding requires a slightly larger area to surround the mold 330 on the base 336 than in the channel molding example described above. However, it is particularly suitable for situations that require contact points on all sides of the platform and final die stacking.

圖4為本發明之一替代實施例的一圖表。此實施例，在許多方面，係類似於參照圖1所顯示及描述之實施例。然而，一或多個ASIC 410-1至410-n係安裝於基體上以被包封於模鑄化合物中。ASIC 410可被耦接至該基體及使用晶粒附接薄膜408-1至408-n彼此堆疊。被動元件402圍繞ASIC 410被安裝至基體102。被動元件402及ASIC 410被共同地包封於模鑄化合物中，其形成平台供晶粒堆疊110-1至110-n使用。因為ASIC往往較小，已發現將ASIC含括於平台內為增加SIP容量同時降低由SIP 400所佔用之區域的有效方式。 Figure 4 is a diagram of an alternative embodiment of the present invention. This embodiment, in many respects, is similar to the embodiment shown and described with reference to FIG. 1. However, one or more ASICs 410-1 to 410-n are mounted on the substrate to be encapsulated in the molding compound. The ASIC 410 can be coupled to the substrate and stacked on each other using die attach films 408-1 to 408-n. The passive component 402 is mounted to the base 102 around the ASIC 410. The passive component 402 and the ASIC 410 are collectively encapsulated in a molding compound, which forms a platform for the die stacks 110-1 to 110-n. Because ASICs tend to be small, including ASICs in the platform has been found to be an effective way to increase SIP capacity while reducing the area occupied by SIP 400.

圖5為根據本發明之一個實施例的一系統之一方塊圖。所描繪之電腦系統1000(亦稱為電子系統1000)可根據本發明闡述的數個所揭實施例及其相等者而體現一SIP。電腦系統1000可為諸如上網本電腦之行動裝置。電腦系統1000可為諸如無線智慧型手機之行動裝置。電腦系統1000可為桌上型電腦。電腦系統1000可為手持閱讀器。電腦系統1000可為伺服器系統。電腦系統 1000可為超級電腦或高效能計算系統。 Fig. 5 is a block diagram of a system according to an embodiment of the present invention. The depicted computer system 1000 (also referred to as the electronic system 1000) can embody a SIP according to the several disclosed embodiments described in the present invention and their equivalents. The computer system 1000 may be a mobile device such as a netbook computer. The computer system 1000 may be a mobile device such as a wireless smart phone. The computer system 1000 may be a desktop computer. The computer system 1000 may be a handheld reader. The computer system 1000 may be a server system. computer system 1000 can be a supercomputer or a high-performance computing system.

在一實施例中，電子系統1000為一電腦系統，其包括一系統匯流排1020，用以電氣耦接電子系統1000之各種組件。系統匯流排1020為單一匯流排或根據各種實施例之匯流排的任意組合。電子系統1000包括提供電力至積體電路1010之一電壓源1030。在一些實施例中，電壓源1030透過系統匯流排1020供應電流至積體電路1010。 In one embodiment, the electronic system 1000 is a computer system, which includes a system bus 1020 for electrically coupling various components of the electronic system 1000. The system bus 1020 is a single bus or any combination of buses according to various embodiments. The electronic system 1000 includes a voltage source 1030 that provides power to an integrated circuit 1010. In some embodiments, the voltage source 1030 supplies current to the integrated circuit 1010 through the system bus 1020.

積體電路1010電氣耦接至系統匯流排1020且包括根據一實施例之任何電路或電路之組合。在一實施例中，積體電路1010包括可為任何類型之一處理器1012。如本文所使用者，處理器1012可意指任何類型之電路，諸如，但不限於，微處理器、微控制器、圖形處理器、數位信號處理器、或其他處理器。在一實施例中，處理器1012包括本文所揭之SIP或與本文所揭之SIP耦接。在一實施例中，SRAM實施例係體現於該處理器之記憶體快取中。可被包括在積體電路1010中的其他類型之電路為一定制電路或一特定應用積體電路，諸如使用於無線裝置中之通訊電路1014，諸如蜂巢式電話、智慧型手機、呼叫器、可攜式電腦、雙向無線電、及類似電子系統，或用於伺服器之通訊電路。在一實施例中，積體電路1010包括晶粒上記憶體1016，諸如靜態隨機存取記憶體(SRAM)。在一實施例中，積體電路1010包括嵌入式晶粒上記憶體1016，諸如嵌入式動態隨機存取記憶體 (eDRAM)。 The integrated circuit 1010 is electrically coupled to the system bus 1020 and includes any circuit or combination of circuits according to an embodiment. In an embodiment, the integrated circuit 1010 includes a processor 1012 that can be any type. As used herein, the processor 1012 can refer to any type of circuit, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or other processors. In one embodiment, the processor 1012 includes or is coupled to the SIP disclosed herein. In one embodiment, the SRAM embodiment is embodied in the memory cache of the processor. Other types of circuits that can be included in the integrated circuit 1010 are a custom circuit or an application-specific integrated circuit, such as the communication circuit 1014 used in wireless devices, such as cellular phones, smart phones, pagers, and Portable computers, two-way radios, and similar electronic systems, or communication circuits for servers. In one embodiment, the integrated circuit 1010 includes on-die memory 1016, such as static random access memory (SRAM). In one embodiment, the integrated circuit 1010 includes embedded on-die memory 1016, such as embedded dynamic random access memory (eDRAM).

在一實施例中，積體電路1010係與後續積體電路1011相補。有用的實施例包括一雙處理器1013及雙通訊電路1015及諸如SRAM之雙晶粒上記憶體1017。在一實施例中，雙積體電路1010包括諸如eDRAM之嵌入式晶粒上記憶體1017。 In one embodiment, the integrated circuit 1010 complements the subsequent integrated circuit 1011. Useful examples include a dual processor 1013 and dual communication circuits 1015 and dual on-die memory 1017 such as SRAM. In one embodiment, the dual integrated circuit 1010 includes an embedded on-die memory 1017 such as eDRAM.

在一實施例中，電子系統1000亦包括一外部記憶體1040，該外部記憶體1040轉而可包括適用於特定應用之一或多個記憶體元件，諸如以RAM形式之主記憶體1042、一或多個硬驅動機1044、及/或處理可移動媒體1046之一或多個驅動機，可移動媒體1046係諸如磁片、光碟(CD)、數位可變光碟(DVD)、快閃記憶體驅動機、及其他本領域習知的可移動媒體。外部記憶體1040亦可為嵌入式記憶體1048，諸如根據一實施例之於一晶粒堆疊中之第一晶粒。 In one embodiment, the electronic system 1000 also includes an external memory 1040, which in turn may include one or more memory elements suitable for specific applications, such as a main memory 1042 in the form of RAM. One or more hard drives 1044, and/or one or more drives that handle removable media 1046, such as floppy disks, compact discs (CD), digital variable discs (DVD), flash memory Drivers, and other removable media known in the art. The external memory 1040 may also be an embedded memory 1048, such as the first die in a die stack according to an embodiment.

在一實施例中，電子系統1000亦包括一顯示裝置1050、一音訊輸出1060。在一實施例中，電子系統1000包括諸如一控制器之一輸入裝置1070，該輸入裝置1070可為鍵盤、滑鼠、軌跡球、遊戲控制器、麥克風、語音辨識裝置、或任何其他輸入資訊至電子系統1000內的輸入裝置。在一實施例中，輸入裝置1070為一攝影機。在一實施例中，輸入裝置1070為一數位錄音機。在一實施例中，輸入裝置1070為一攝影機及一數位錄音機。在一實施例中，一輸入裝置為一可為顯示裝置 1050之部分的觸控螢幕。 In an embodiment, the electronic system 1000 also includes a display device 1050 and an audio output 1060. In one embodiment, the electronic system 1000 includes an input device 1070 such as a controller. The input device 1070 may be a keyboard, a mouse, a trackball, a game controller, a microphone, a voice recognition device, or any other input information to An input device in the electronic system 1000. In one embodiment, the input device 1070 is a camera. In one embodiment, the input device 1070 is a digital audio recorder. In one embodiment, the input device 1070 is a camera and a digital recorder. In one embodiment, an input device is a display device Part of the 1050 touch screen.

如本文所顯示，積體電路1010可於數個不同實施例中被實現，包括根據若干所揭實施例及其同等者中之任一者的一SIP、電子系統、電腦系統、一或多個製造積體電路之方法、及一或多個製造一電子組件之方法，該電子組件包括根據如本文各種實施例中所闡述之若干所揭實施例中之任一者的一SIP。元件、材料、幾何形狀、尺寸及操作順序可根據若干所揭SIP實施例及其等同者中之任一者而全部被改變，以適應特定I/O耦接需求，包括用於嵌入在處理器中安裝基體之微電子晶粒的陣列接觸計數、陣列接觸組態。可包括一基礎基體，如圖5之虛線所呈現者。亦可包括被動裝置，亦如圖5中所描繪。 As shown herein, the integrated circuit 1010 can be implemented in a number of different embodiments, including a SIP, an electronic system, a computer system, one or more according to any of the disclosed embodiments and their equivalents. A method of manufacturing an integrated circuit, and one or more methods of manufacturing an electronic component, the electronic component including a SIP according to any of the disclosed embodiments as set forth in the various embodiments herein. The components, materials, geometric shapes, dimensions, and operating sequence can all be changed according to any of the disclosed SIP embodiments and their equivalents to meet specific I/O coupling requirements, including for embedding in the processor The array contact count and array contact configuration of the microelectronic die in the mounting substrate. It may include a basic substrate, as shown by the dashed line in FIG. 5. It may also include passive devices, as also depicted in FIG. 5.

下列實例係有關進一步之實施例。不同實施例之各種特徵可與一些所包括之特徵及其他所排除之特徵以各種方式組合，以適應各種不同應用。一些實施例係有關於具有具複數個被動裝置安裝於其上之基體的系統級封裝。模鑄化合物包封該等複數個被動裝置以界定實質上平行於該基體之一表面的一平坦表面。複數個積體電路晶粒係相繼耦接至該平坦表面。 The following examples are related to further embodiments. Various features of different embodiments can be combined with some included features and other excluded features in various ways to adapt to various applications. Some embodiments relate to a system-in-package having a substrate with a plurality of passive devices mounted on it. The molding compound encapsulates the plurality of passive devices to define a flat surface substantially parallel to a surface of the substrate. A plurality of integrated circuit dies are successively coupled to the flat surface.

在進一步的實施例中，該基體為一印刷電路板。 In a further embodiment, the substrate is a printed circuit board.

在進一步的實施例中，至少一特定應用積體電路(ASIC)係耦接至該基體並被包封於該模鑄化合物內。 In a further embodiment, at least one application specific integrated circuit (ASIC) is coupled to the substrate and encapsulated in the molding compound.

在進一步的實施例中，耦接至該平坦表面之各個積體電路晶粒實質上具有相同厚度。 In a further embodiment, each integrated circuit die coupled to the flat surface has substantially the same thickness.

在進一步的實施例中，一第二複數個被動裝置係耦接至該基體並在該模鑄化合物外面。 In a further embodiment, a second plurality of passive devices are coupled to the substrate and outside the molding compound.

在進一步的實施例中，於該模鑄化合物內的該等被動裝置具有不同z維度。 In a further embodiment, the passive devices in the molding compound have different z dimensions.

在進一步的實施例中，一晶粒附接薄膜層將一第一積體電路晶粒耦接至該模鑄化合物之該平坦表面，且相繼的晶粒附接薄膜層將相繼的晶粒耦接在一起以形成一堆疊。 In a further embodiment, a die attach film layer couples a first integrated circuit die to the flat surface of the molding compound, and successive die attach film layers couple successive die Join together to form a stack.

在進一步的實施例中，該等晶粒附接薄膜層實質上各具有相同厚度。 In a further embodiment, each of the die attach film layers has substantially the same thickness.

在進一步的實施例中，該模鑄化合物為一環氧樹脂。 In a further embodiment, the molding compound is an epoxy resin.

一些實施例係關於一種複數個被動裝置被安裝於一基體上之方法。具有平行於該基體之該表面的一實質上平面上表面的一平台被模鑄，包封該等被動裝置。一第一積體電路晶粒係耦接至該平面表面。額外的積體電路晶粒係耦接至第一晶粒並接著相繼地耦接以形成一晶粒堆疊。 Some embodiments relate to a method in which a plurality of passive devices are mounted on a substrate. A platform with a substantially flat upper surface parallel to the surface of the substrate is molded to encapsulate the passive devices. A first integrated circuit die is coupled to the plane surface. Additional integrated circuit dies are coupled to the first die and then sequentially coupled to form a die stack.

在進一步的實施例中，該等積體電路晶粒係線接合至該基體。 In a further embodiment, the integrated circuit dies are wire-bonded to the substrate.

在進一步的實施例中，一特定應用積體電路(ASIC)係於模鑄之前耦接至該基體。 In a further embodiment, an application specific integrated circuit (ASIC) is coupled to the substrate before molding.

在進一步的實施例中，一模具係覆蓋於該等複數個被動裝置上方。模鑄化合物透過一針點澆口而被引入該模具內並於該模具內固化。 In a further embodiment, a mold is covered above the plurality of passive devices. The molding compound is introduced into the mold through a pin point gate and cured in the mold.

在進一步的實施例中，界定出包圍該等被動裝置之一模具通道的一模具被引入。一模鑄化合物係沿著該通道而流動並固化。 In a further embodiment, a mold defining a mold channel surrounding one of the passive devices is introduced. A molding compound flows along the channel and solidifies.

在進一步的實施例中，該等被動裝置及該等積體電路晶粒係封裝於一單一封裝體內。 In a further embodiment, the passive devices and the integrated circuit dies are packaged in a single package.

一些實施例係有關於一種系統，該系統包括具有一基體之一系統級封裝，該基體具複數個安裝於其上之被動裝置。一模鑄化合物包封該等複數個被動裝置以界定出實質上平行於該基體之一表面的一平坦表面。複數個積體電路晶粒係相繼地耦接至該平坦表面。SIP與一顯示器及一麥克風輸入裝置通訊。 Some embodiments relate to a system that includes a system-in-package with a substrate with a plurality of passive devices mounted thereon. A molding compound encapsulates the plurality of passive devices to define a flat surface substantially parallel to a surface of the substrate. A plurality of integrated circuit dies are sequentially coupled to the flat surface. SIP communicates with a display and a microphone input device.

在進一步的實施例中，該顯示器具有一觸控螢幕。在進一步的實施例中，該系統級封裝包括耦接至該基體而於該模鑄化合物外部的複數個被動裝置。在進一步的實施例中，該系統級封裝具有耦接至該基體並被包封在該模鑄化合物內的一特定應用積體電路(ASIC)。 In a further embodiment, the display has a touch screen. In a further embodiment, the system-in-package includes a plurality of passive devices coupled to the substrate and outside the molding compound. In a further embodiment, the system-in-package has an application-specific integrated circuit (ASIC) coupled to the substrate and encapsulated in the molding compound.

一些實施例係有關於一種具有一具複數個被動裝置安裝於其上之基體的系統級封裝。該等複數個被動裝置被包封以界定出實質上平行於該基體之一表面的一平坦表面。複數個積體電路晶粒係相繼地耦接至該平坦表面。 Some embodiments relate to a system-in-package with a substrate on which a plurality of passive devices are mounted. The plurality of passive devices are encapsulated to define a flat surface substantially parallel to a surface of the substrate. A plurality of integrated circuit dies are sequentially coupled to the flat surface.

在進一步的實施例中，至少一特定應用積體電路(ASIC)係耦接至該基體並包封於該表面下面。 In a further embodiment, at least one application specific integrated circuit (ASIC) is coupled to the substrate and encapsulated under the surface.

進一步的實施例包括用以耦接該等積體電路晶粒至該平坦表面上之一堆疊內的構件。 Further embodiments include components for coupling the integrated circuit dies to a stack on the flat surface.

儘管上文以反映特定線性順序之流程圖的上下文討論了本發明的實施例，但這僅是為了方便。在一些情況下，可以不同於所示次序執行各種操作，或各種操作可並行地發生。還應當認識到，關於一個實施例所描述的一些操作可以有利地結合到另一個實施例中。此種併入被明確涵蓋。在前述說明書中，已經參照本發明的具體實施例描述了本發明。然而，將顯而易見的是，在不脫離如所附申請專利範圍中闡述的本發明更廣泛之精神和範圍的情況下，可以對其進行各種修改和改變。因此，說明書和圖式被視為是說明性的而不是限制性的。 Although the embodiments of the present invention are discussed above in the context of a flowchart reflecting a specific linear order, this is for convenience only. In some cases, various operations may be performed in a different order than shown, or various operations may occur in parallel. It should also be recognized that some operations described with respect to one embodiment can be advantageously combined into another embodiment. Such incorporation is explicitly covered. In the foregoing specification, the present invention has been described with reference to specific embodiments of the present invention. However, it will be apparent that various modifications and changes can be made to it without departing from the broader spirit and scope of the present invention as set forth in the scope of the appended patent application. Therefore, the description and drawings are regarded as illustrative rather than restrictive.

100‧‧‧系統級封裝(SIP) 100‧‧‧System in Package (SIP)

102‧‧‧基體 102‧‧‧Matrix

104‧‧‧被動裝置 104‧‧‧Passive device

106‧‧‧模鑄化合物 106‧‧‧Molding compound

108-1~108-n‧‧‧晶粒附接薄膜(DFA) 108-1~108-n‧‧‧Die Attached Film (DFA)

110、110-1~110-n‧‧‧積體電路晶粒、晶粒、IC 110, 110-1~110-n‧‧‧Integrated circuit die, die, IC

114‧‧‧被動裝置 114‧‧‧Passive device

116‧‧‧水平表面、平台表面 116‧‧‧Horizontal surface, platform surface

120‧‧‧接合墊 120‧‧‧Joint pad

126‧‧‧電氣接點、接點 126‧‧‧Electrical contacts, contacts

Claims (19)

一種系統級封裝，包含：一基體；複數個被動裝置，其安裝於該基體上；一模鑄化合物，其包封該等複數個被動裝置以界定出一密封平台，其中該密封平台具有實質上平行於該基體之一表面的一平坦表面，其中該等複數個被動裝置之一或多個被動裝置具有厚度，其係不同於該等複數個被動裝置之其他被動裝置的厚度，且其中該密封平台之該平坦表面佔用一x-y空間；以及複數個積體電路晶粒，其設置在該密封平台之該平坦表面上，其中該等複數個積體電路晶粒之每一者具有一寬度，該寬度係小於該密封平台之寬度，其中該等複數個積體電路晶粒未被包裝在該密封平台之該模鑄化合物內，其中該等複數個積體電路晶粒係相繼地耦接至該密封平台之該平坦表面，其中該等複數個積體電路晶粒包含堆疊成一階梯組態之一第一晶粒、一第二晶粒、及一第三晶粒，且其中該第一晶粒、該第二晶粒、及該第三晶粒之組合具有由該密封平台之該平坦表面所佔用之在該x-y空間內的面積。 A system-in-package includes: a substrate; a plurality of passive devices mounted on the substrate; a molding compound that encapsulates the plurality of passive devices to define a sealing platform, wherein the sealing platform has substantially A flat surface parallel to a surface of the substrate, wherein one or more of the plurality of passive devices has a thickness which is different from the thickness of other passive devices of the plurality of passive devices, and wherein the sealing The flat surface of the platform occupies an xy space; and a plurality of integrated circuit dies are arranged on the flat surface of the sealing platform, wherein each of the plurality of integrated circuit dies has a width, the The width is smaller than the width of the sealing platform, wherein the plurality of integrated circuit dies are not packaged in the molding compound of the sealing platform, and the plurality of integrated circuit dies are sequentially coupled to the The flat surface of the sealing platform, wherein the plurality of integrated circuit dies include a first die, a second die, and a third die stacked in a step configuration, and the first die The combination of the second crystal grain and the third crystal grain has an area in the xy space occupied by the flat surface of the sealing platform. 如請求項1之系統級封裝，其中該基體為一印刷電路板。 Such as the system-in-package of claim 1, wherein the substrate is a printed circuit board. 如請求項1之系統級封裝，其進一步包含： 至少一個特定應用積體電路(ASIC)，其耦接至該基體並且被包封於該密封平台之該模鑄化合物內，其中該至少一個ASIC具有小於該等複數積體電路晶粒之寬度的一寬度。 For example, the system-level package of claim 1, which further includes: At least one application-specific integrated circuit (ASIC) coupled to the substrate and encapsulated in the molding compound of the sealing platform, wherein the at least one ASIC has a width smaller than the width of the plurality of integrated circuit die One width. 如請求項1之系統級封裝，其中該等複數個積體電路晶粒中之各個積體電路晶粒實質上具有相同厚度。 Such as the system-in-package of claim 1, wherein each of the plurality of integrated circuit dies has substantially the same thickness. 如請求項1之系統級封裝，其進一步包含：一第二複數個被動裝置，其耦接至該基體之該表面，其中該等第二複數個被動裝置未被包裝在該密封平台之該模鑄化合物內。 For example, the system-in-package of claim 1, which further comprises: a second plurality of passive devices coupled to the surface of the substrate, wherein the second plurality of passive devices are not packaged in the mold of the sealing platform Casting compound. 如請求項5之系統級封裝，其中該等複數個被動裝置之該一或多個被動裝置之厚度係不同於該等第二複數個被動裝置之厚度。 Such as the system-in-package of claim 5, wherein the thickness of the one or more passive devices of the plurality of passive devices is different from the thickness of the second plurality of passive devices. 如請求項1之系統級封裝，其進一步包含：耦接一第一積體電路晶粒至該密封平台之該平坦表面的一晶粒附接薄膜層，及與該等複數個積體電路晶粒中之相繼晶粒一起耦接的相繼晶粒附接薄膜層。 Such as the system-in-package of claim 1, which further comprises: a die attach film layer coupling a first integrated circuit die to the flat surface of the sealing platform, and the plurality of integrated circuit die Sequential dies in which successive dies in the grain are coupled together are attached to the thin film layer. 如請求項7之系統級封裝，其中該等晶粒附接薄膜層之各層實質上具有相同厚度。 Such as the system-in-package of claim 7, wherein each layer of the die attach film layer has substantially the same thickness. 如請求項1之系統級封裝，其中該模鑄化合物為一環氧樹脂。 Such as the system-in-package of claim 1, wherein the molding compound is an epoxy resin. 一種製造系統級封裝之方法，包含：於一基體上安裝複數個被動裝置；模鑄一密封平台以包封該等複數個被動裝置，該密封平台具有實質上平行於該基體之一表面的一實質上平面表面，其中該等複數個被動裝置之一或多個被動裝置具有厚度，其係不同於該等複數個被動裝置之其他被動裝置的厚度，且其中該密封平台之該實質上平面表面佔用一x-y空間；耦接一第一積體電路晶粒至該密封平台之該實質上平面表面上；以及相繼地耦接複數個積體電路晶粒至該第一積體電路晶粒用以形成一晶粒堆疊，其中該第一積體電路晶粒及該等複數個積體電路晶粒之每一者具有一寬度，該寬度係小於該密封平台之寬度，其中該晶粒堆疊未被包裝在該密封平台內，其中該等複數個積體電路晶粒包含一第二積體電路晶粒、及一第三積體電路晶粒，其中該第一積體電路晶粒、該第二積體電路晶粒、及該第三積體電路晶粒被堆疊成一階梯組態，且其中該第一積體電路晶粒、該第二積體電路晶粒、及該第三積體電路晶粒之組合具有由該密封平台之該實質上平面表面所佔用之在該x-y空間內的面積。 A method of manufacturing a system-in-package includes: installing a plurality of passive devices on a substrate; molding a sealing platform to encapsulate the plurality of passive devices, the sealing platform having a surface substantially parallel to a surface of the substrate A substantially planar surface, wherein one or more of the plurality of passive devices has a thickness that is different from the thickness of other passive devices of the plurality of passive devices, and wherein the substantially planar surface of the sealing platform Occupying an xy space; coupling a first integrated circuit die to the substantially planar surface of the sealing platform; and successively coupling a plurality of integrated circuit die to the first integrated circuit die for A die stack is formed, wherein the first integrated circuit die and each of the plurality of integrated circuit die have a width that is smaller than the width of the sealing platform, and the die stack is not Packaged in the sealed platform, the plurality of integrated circuit dies include a second integrated circuit die and a third integrated circuit die, wherein the first integrated circuit die and the second integrated circuit die The integrated circuit die and the third integrated circuit die are stacked in a step configuration, and the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are stacked The combination of particles has an area in the xy space occupied by the substantially planar surface of the sealing platform. 如請求項10之方法，其進一步包含：線接合該等複數個積體電路晶粒至該基體。 The method of claim 10, further comprising: wire bonding the plurality of integrated circuit dies to the substrate. 如請求項10之方法，其進一步包含：在該模鑄之前耦接一特定應用積體電路(ASIC)至該 基體，其中該ASIC被包封在該密封平台內，且其中該ASIC具有小於該第一積體電路晶粒及該等複數個積體電路晶粒兩者之寬度的一寬度。 Such as the method of claim 10, further comprising: coupling an application-specific integrated circuit (ASIC) to the The base body, wherein the ASIC is enclosed in the sealed platform, and wherein the ASIC has a width smaller than the width of both the first integrated circuit die and the plurality of integrated circuit die. 如請求項10之方法，其中該模鑄包含：於該等複數個被動裝置上方覆蓋一模具；透過一針點澆口將一模鑄化合物引入該模具內；固化該模鑄化合物。 The method of claim 10, wherein the molding comprises: covering a mold on the plurality of passive devices; introducing a molding compound into the mold through a pin point gate; and curing the molding compound. 如請求項10之方法，其中該模鑄包含：引入一模具，其界定出包圍該等被動裝置之一模具通道；以及使一模鑄化合物沿著該通道流動；以及固化該模鑄化合物。 The method of claim 10, wherein the molding comprises: introducing a mold that defines a mold channel surrounding the passive devices; and flowing a molding compound along the channel; and curing the molding compound. 如請求項14之方法，其進一步包含：將該等被動裝置及該ASIC封裝於一單一封裝體內；以及將一第二複數個被動裝置耦接至該基體之該表面，其中該等第二複數個被動裝置未被包裝在該密封平台之該模鑄化合物內，且其中該等複數個被動裝置之該一或多個被動裝置之厚度係不同於該等第二複數個被動裝置之厚度。 For example, the method of claim 14, further comprising: packaging the passive devices and the ASIC in a single package; and coupling a second plurality of passive devices to the surface of the substrate, wherein the second plurality A passive device is not packaged in the molding compound of the sealing platform, and the thickness of the one or more passive devices of the plurality of passive devices is different from the thickness of the second plurality of passive devices. 一種電子系統，包含：一系統級封裝，其包括：一基體；複數個被動裝置，其安裝於該基體上； 一模鑄化合物，其包封該等複數個被動裝置以界定出一密封平台，其中該密封平台具有實質上平行於該基體之一表面的一平坦表面，其中該等複數個被動裝置之一或多個被動裝置具有厚度，其係不同於該等複數個被動裝置之其他被動裝置的厚度，且其中該密封平台之該平坦表面佔用一x-y空間；以及複數個記憶體積體電路晶粒，其設置在該密封平台之該平坦表面上，其中該等複數個記憶體積體電路晶粒之每一者具有一寬度，該寬度係小於該密封平台之寬度，其中該等複數個記憶體積體電路晶粒未被包裝在該密封平台之該模鑄化合物內，其中該等複數個記憶體積體電路晶粒係相繼地耦接至該密封平台之該平坦表面，其中該等複數個記憶體積體電路晶粒包含堆疊成一階梯組態之一第一晶粒、一第二晶粒、及一第三晶粒，且其中該第一晶粒、該第二晶粒、及該第三晶粒之組合具有由該密封平台之該平坦表面所佔用之在該x-y空間內的面積；一顯示器；以及一麥克風輸入裝置。 An electronic system, including: a system-in-package, including: a substrate; a plurality of passive devices installed on the substrate; A molding compound that encapsulates the plurality of passive devices to define a sealing platform, wherein the sealing platform has a flat surface substantially parallel to a surface of the substrate, wherein one of the plurality of passive devices or A plurality of passive devices have a thickness which is different from the thickness of other passive devices of the plurality of passive devices, and the flat surface of the sealing platform occupies an xy space; and a plurality of memory volume circuit dies, which are arranged On the flat surface of the sealing platform, each of the plurality of memory volume circuit dies has a width that is smaller than the width of the sealing platform, wherein the plurality of memory volume circuit dies Not packaged in the molding compound of the sealing platform, wherein the plurality of memory volume circuit dies are sequentially coupled to the flat surface of the sealing platform, wherein the plurality of memory volume circuit dies It includes a first die, a second die, and a third die stacked in a step configuration, and the combination of the first die, the second die, and the third die has The area in the xy space occupied by the flat surface of the sealing platform; a display; and a microphone input device. 如請求項16之電子系統，其中該顯示器包含：一觸控螢幕。 Such as the electronic system of claim 16, wherein the display includes: a touch screen. 如請求項16之電子系統，其中該系統級封裝進一步包含：耦接至該基體之該表面的一第二複數個被動裝置， 其中該等第二複數個被動裝置未被包裝在該密封平台之該模鑄化合物內。 The electronic system of claim 16, wherein the system-in-package further comprises: a second plurality of passive devices coupled to the surface of the substrate, The second plurality of passive devices are not packaged in the molding compound of the sealing platform. 如請求項16之電子系統，其中該系統級封裝進一步包含：耦接至該基體並且被包封於該密封平台之該模鑄化合物內的一特定應用積體電路(ASIC)，其中該ASIC具有小於該等複數個記憶體積體電路晶粒之寬度的一寬度。 The electronic system of claim 16, wherein the system-in-package further comprises: an application-specific integrated circuit (ASIC) coupled to the substrate and encapsulated in the molding compound of the sealing platform, wherein the ASIC has A width smaller than the width of the plurality of memory volume circuit dies.
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