JP2005109419A - Three-dimensional semiconductor integrated circuit device - Google Patents

Three-dimensional semiconductor integrated circuit device Download PDF

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JP2005109419A
JP2005109419A JP2003373420A JP2003373420A JP2005109419A JP 2005109419 A JP2005109419 A JP 2005109419A JP 2003373420 A JP2003373420 A JP 2003373420A JP 2003373420 A JP2003373420 A JP 2003373420A JP 2005109419 A JP2005109419 A JP 2005109419A
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integrated circuit
semiconductor integrated
chip
metal wiring
circuit device
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Taketo Yoshida
健人 吉田
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SYSTEM FABRICATION TECHNOLOGIE
SYSTEM FABRICATION TECHNOLOGIES Inc
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SYSTEM FABRICATION TECHNOLOGIE
SYSTEM FABRICATION TECHNOLOGIES Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Abstract

<P>PROBLEM TO BE SOLVED: To enable high-speed and high-density three-dimensional mounting for a semiconductor integrated circuit device which is constituted of a plurality of chips. <P>SOLUTION: A device is arranged, such that desired functions are realized by forming bumps on a wafer that has been processed through a wiring step and by sticking facedown thereon a plurality of tested non-defective bare chips for a semiconductor integrated circuit, and that high-speed and high-density mounting method can be used, by planarizing the plane where the chips have been stuck and providing thereto a connecting terminal. In the device, these steps are repeated plural number of times, to enable the constitution of the three-dimensional semiconductor integrated circuit device. The wafer is subjected to dicing to obtain chips, which are then tested to provide final products. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、複数の半導体集積回路チップからなる三次元半導体集積回路装置に関し、特に高速且つ高密度実装を実現した半導体集積回路装置の構造及び製造方法に関する。  The present invention relates to a three-dimensional semiconductor integrated circuit device including a plurality of semiconductor integrated circuit chips, and more particularly to a structure and manufacturing method of a semiconductor integrated circuit device that realizes high-speed and high-density mounting.

従来、半導体集積回路はムーアの法則に従い、高集積化による低コスト化・高速化・低消費電力化・高信頼性化の恩恵を享受してきた。しかし設計ルールが、１８０ナノメーターよりさらに微細になってくると、ＳＯＣ（システム・オン・チップ）と呼ばれるように、チップに集積可能なシステムの規模が非常に大きくなり、更なる高集積化のためには、ＤＲＡＭやフラッシュ等の大規模メモリー回路や、ＲＦ等の高速アナログ回路を同時に集積する必要がでてきた。しかしながら、これらを１チップ化するためにはウェハー製造プロセスが非常に複雑になり、搭載されるロジック・メモリー・アナログ等の各機能に対して製造プロセスの最適化が困難になり、リークの増加・基盤ノイズ等の問題が発生する。さらにメモリーセル・ロジックセル等は微細化に対し恩恵を得るが、インターフェース回路・アナログ回路・高耐圧回路等は微細化する事が難しいため、チップ内に占有面積の不均衡が生ずる。さらに、マスク代を含めた開発費用ならびに開発期間が著しく増大する。これは最終製品の市場におけるライフサイクルの短命化から考えても致命的である。  Conventionally, semiconductor integrated circuits have enjoyed the benefits of low cost, high speed, low power consumption, and high reliability through high integration in accordance with Moore's Law. However, when the design rule becomes finer than 180 nanometers, the scale of a system that can be integrated on a chip becomes very large as called SOC (system on chip), and further integration is further increased. For this purpose, it has become necessary to simultaneously integrate large-scale memory circuits such as DRAM and flash and high-speed analog circuits such as RF. However, in order to make these into one chip, the wafer manufacturing process becomes very complicated, making it difficult to optimize the manufacturing process for each function such as logic, memory, analog, etc. Problems such as base noise occur. Furthermore, memory cells, logic cells, etc. benefit from miniaturization, but interface circuits, analog circuits, high voltage circuits, etc. are difficult to miniaturize, resulting in an unbalanced occupation area within the chip. Further, the development cost including the mask cost and the development period are remarkably increased. This is fatal considering the shortening of the life cycle in the final product market.

このように考えていくと、特に９０ナノメーター以降のウェハー製造プロセスで、ＳＯＣ化を必要とするシステムは、非常に高い性能を追求するとともに、大量生産が可能であるシステムに限られていく。このような問題を回避するために、複数の複数の半導体集積回路チップあるいは異種のチップを１つのパッケージに収納することで、上記の問題を回避しようとするＳＩＰ（システム・イン・パッケージ）という手法が広まりつつある。この手法により、他社チップとの混載や、光・機械等の異種チップとの混載等の多機能化を進める事も可能となる。  When thinking in this way, especially in a wafer manufacturing process of 90 nanometers or more, a system that requires SOC is limited to a system that pursues very high performance and can be mass-produced. In order to avoid such a problem, a method called SIP (System in Package) which attempts to avoid the above problem by housing a plurality of semiconductor integrated circuit chips or different types of chips in one package. Is spreading. With this method, it becomes possible to promote multi-functionalization such as mixed mounting with chips from other companies and mixed mounting with different types of chips such as optical and mechanical devices.

従来のＳＩＰの例を図１４に示す。２つの異なる半導体集積回路チップ「２０」・「２１」を重ねてリードフレーム「２２」上にスタック配置し、それぞれのチップのボンディング・パッドから、リードフレーム「２２」へワイヤー「２３」でボンディングされている。これにより高密度な半導体集積回路チップの実装を可能としている。さらに別の従来の実装技術の例として、図１５に示すＣＳＰ（チップ・サイズ・パッケージ）の様に半導体集積回路チップ「２５」上の配線「２６」に、追加配線「２７」を施した後にはんだや金や銅のバンプ「２８」を生成して基盤と圧着する手法がある。  An example of conventional SIP is shown in FIG. Two different semiconductor integrated circuit chips “20” and “21” are stacked on the lead frame “22” and bonded from the bonding pads of each chip to the lead frame “22” with the wire “23”. ing. As a result, high-density semiconductor integrated circuit chips can be mounted. As another example of the conventional mounting technique, after the additional wiring “27” is applied to the wiring “26” on the semiconductor integrated circuit chip “25” like the CSP (chip size package) shown in FIG. There is a technique in which bumps “28” made of solder, gold or copper are generated and pressure-bonded to the substrate.

本発明が解決しようとしている問題は、複数チップからなる半導体集積回路装置の実装を、ＳＩＰの様々な従来手法より、高速・高密度且つ低いコストで実現することである。まず、ワイヤーボンディングのみを使用した場合、他ピンになるとコストが上昇する。さらに外部に接続されない内部バスにも、インダクタンス及び容量の大きいワイヤーが使用されるため、高速用途への適用が非常に難しい。半導体集積回路装置のコスト低減には、バッチ処理の可能なプロセスの導入が有効であるが、従来のＳＩＰの場合では、組立工程に依存している場合が多く、バッチ処理が難しいためコストが高くなる場合が多い。The problem to be solved by the present invention is to realize mounting of a semiconductor integrated circuit device composed of a plurality of chips at higher speed, higher density and lower cost than various conventional SIP methods. First, when only wire bonding is used, the cost increases when other pins are used. Furthermore, since a wire having a large inductance and capacity is used for an internal bus that is not connected to the outside, it is very difficult to apply to high-speed applications. Introducing processes capable of batch processing is effective in reducing the cost of semiconductor integrated circuit devices, but conventional SIP often depends on the assembly process and is expensive because batch processing is difficult. There are many cases.

本発明では、機能を搭載する複数の半導体集積回路チップ（以降ＡＳＣ）群とは別に、配線ベースチップ（以降ＷＢＣ）を使用する。搭載する複数のＡＳＣ群とＷＢＣは、ＷＢＣのパッド上に設けられたバンプを介して、お互いのパッドの存在する面どうしを接合し、その隙間を接着材料で埋めてＡＳＣをＷＢＣに固定した上で、ＡＳＣ側に研削・平坦化処理を行うと共に、ＷＢＣの金属配線で設けられた接続パッドから平坦化処理の行われた面に対し、垂直に形成された金属配線である、スルーホールを形成する。これらの工程により、平坦化された面から、スルーホール並びにＷＢＣ上の金属配線を経由して、ＡＳＣに電気的に接続することが可能になる。この構造を利用することにより、平坦化された面に、ボンディング・パッドや外部接続バンプを形成して外部に接続することや、さらにこれらの工程を繰り返すことにより、三次元の半導体装置を構成することが可能となる。  In the present invention, a wiring base chip (hereinafter referred to as WBC) is used separately from a plurality of semiconductor integrated circuit chips (hereinafter referred to as ASC) groups having functions. A plurality of ASC groups and WBC to be mounted are bonded to each other where the pads exist via bumps provided on the WBC pads, and the gap is filled with an adhesive material to fix the ASC to the WBC. Then, the grinding and flattening process is performed on the ASC side, and a through hole that is a metal wiring formed perpendicular to the surface subjected to the flattening process is formed from the connection pad provided by the WBC metal wiring. To do. By these steps, it is possible to electrically connect to the ASC from the flattened surface via the through hole and the metal wiring on the WBC. By utilizing this structure, a bonding pad and external connection bumps are formed on the flattened surface and connected to the outside, and further, these steps are repeated to form a three-dimensional semiconductor device. It becomes possible.

本発明の半導体集積回路装置の製造工程を、図５から図１１を用いて説明する。まず、ウェハー基板「１５」を構成する配線ベースチップ（ＷＢＣ）「１」に、配線工程「２」を行い、バンプ「３」を形成する（図５）。ＷＢＣは、搭載する各半導体集積回路チップ（ＡＳＣ）と比べると比較的安定した緩いプロセスで製造され、高い歩留まりを実現する。次に、バンプ「３」を介して、ＡＳＣ「５」を電気的に接続する（図６）。次に、接着材料「４」で、ＡＳＣ「５」をＷＢＣ「１」に固定した後に、その裏面を研削する（図７）。その上に、絶縁膜を塗布または成長させ（図８）、さらに研削を行うことにより、面の平坦化を行う（図９）。この時点でのウェハーの状態を図１２に示す。ＡＳＣ「５」に含まれる能動素子は、この時点で自分自身の基板並びにＷＢＣに挿まれて、外部の光の影響を受けない。
ここで、最終的にＡＳＣ「５」の基板を絶縁するための、絶縁膜「１７」を形成するとともに、スルーホール「６」をＷＢＣ「１」のパッド「１９」上に設ける（図１０）。これは、エッチング後に堆積する方法とともに、リフトオフ等の工程で絶縁膜「１６」・「１７」の生成と同時に行うことも可能である。さらに再配線「７」を設けて、外部接続のためのバンプ「８」を形成する（図１１）。この時点でのウェハーの状態を図１３に示す。このように、ＡＳＣ「５」を貼り付けた面に対して外部接続のための端子を設けることが出来る。このウェハーを切断して、側面の処理を行うことにより、図１に示す構造を完成することができる。A manufacturing process of the semiconductor integrated circuit device of the present invention will be described with reference to FIGS. First, the wiring process “2” is performed on the wiring base chip (WBC) “1” constituting the wafer substrate “15” to form the bump “3” (FIG. 5). WBC is manufactured by a relatively stable and loose process as compared with each semiconductor integrated circuit chip (ASC) to be mounted, and realizes a high yield. Next, the ASC “5” is electrically connected through the bump “3” (FIG. 6). Next, after fixing ASC “5” to WBC “1” with the adhesive material “4”, the back surface is ground (FIG. 7). An insulating film is applied or grown thereon (FIG. 8), and further ground to flatten the surface (FIG. 9). The state of the wafer at this time is shown in FIG. The active element included in the ASC “5” is inserted into its own substrate and WBC at this point, and is not affected by external light.
Here, an insulating film “17” for finally insulating the substrate of ASC “5” is formed, and a through hole “6” is provided on the pad “19” of WBC “1” (FIG. 10). . This can be performed simultaneously with the formation of the insulating films “16” and “17” in a process such as lift-off as well as a method of depositing after etching. Further, rewiring “7” is provided to form bumps “8” for external connection (FIG. 11). The state of the wafer at this time is shown in FIG. Thus, a terminal for external connection can be provided on the surface to which ASC “5” is attached. The structure shown in FIG. 1 can be completed by cutting the wafer and processing the side surfaces.

本発明の効果として、以下の６つが上げられる。１：ＳＯＣと同等のバス並びに配線の性能を、チップ間で実現することができる。２：ＳＩＰと同様に、各半導体チップ（ＡＳＣ）に対して、それぞれ最適な製造プロセスを選択することができ、高性能化・少消費電力化が容易である。３：チップをスタックすることにより非常に高密度で実装することが出来る。４：各ＡＳＣの能動素子領域が半導体基板で挿まれているため、特に密封しなくても、外部の光の影響を受けにくい、５：既設計のチップの再利用あるいは流通しているベアチップの購入が可能であり、派生品の展開を考慮した設計プラットフォームの構築が容易。６：ウェハー上へのＡＳＣの貼り付け以外は、ほとんど既存の設計システム及び製造システムが利用可能であり、新規の投資が少ない。  The following six effects can be raised as effects of the present invention. 1: A bus and wiring performance equivalent to SOC can be realized between chips. 2: Like SIP, an optimal manufacturing process can be selected for each semiconductor chip (ASC), and high performance and low power consumption are easy. 3: It can be mounted with very high density by stacking chips. 4: Since the active element region of each ASC is inserted in the semiconductor substrate, it is not easily affected by external light even if it is not sealed. 5: Reuse of already designed chips or the distribution of bare chips It is possible to purchase, and it is easy to build a design platform that takes into account the development of derivative products. 6: Almost existing design systems and manufacturing systems can be used except for attaching the ASC on the wafer, and there is little new investment.

本発明を実施するための最良の形態は、今までＳＩＰでは実現できなかった高速の多ビットのバスを内部に含む画像処理等のアプリケーションを含む場合である。バスの転送速度を上げるため、ＳＯＣでは１０００本以上の高速バスを形成する場合もあり、ＳＩＰ化が困難な理由とされた。本発明では内部信号にバンプを使用するため、通常のワイヤーボンディングに比べ、インダクタンスを１０分の１に抑えることができる。またこのようなアプリケーションでは、熱の発生並びに局部的な温度の上昇等の問題があるが、実施例１で示すように、本発明における構造は冷却に対しても適している。また、複数のプロセスで製造されたチップを集積することが可能になるため、ＳＯＣでは混載が難しかった、アナログチップ・高耐圧チップ・大規模メモリーの高密度実装が容易になる。このように、今までＳＯＣしか考えられなかった高集積で高速なアプリケーションと、ＳＯＣでは困難であった多機能性を必要とするアプリケーションに本発明を実施することが最良形態となる。  The best mode for carrying out the present invention is a case where an application such as an image processing including a high-speed multi-bit bus which cannot be realized by SIP until now is included. In order to increase the bus transfer speed, there are cases where more than 1000 high-speed buses are formed in the SOC, which is the reason why it is difficult to implement SIP. In the present invention, since the bump is used for the internal signal, the inductance can be suppressed to 1/10 compared with the normal wire bonding. Further, in such an application, there are problems such as generation of heat and local temperature rise. However, as shown in Example 1, the structure of the present invention is suitable for cooling. In addition, since chips manufactured by a plurality of processes can be integrated, high-density mounting of an analog chip, a high withstand voltage chip, and a large-scale memory, which is difficult to be mixed with an SOC, is facilitated. As described above, the best mode is to implement the present invention for a high-integrated and high-speed application that has been considered only by SOC until now and an application that requires multi-functionality that has been difficult with SOC.

本発明の実施例１を、図１を用いて説明する。これは、図５から図１１に示す工程で製造されたウェハーを、切断することによって実現した、本発明の半導体集積回路装置である。比較的消費電力が大きい場合を想定しており、ＷＢＣ「１」の裏面にヒートシンク状のエッチングを行い、表面積大きくして熱抵抗を下げている。  A first embodiment of the present invention will be described with reference to FIG. This is a semiconductor integrated circuit device of the present invention realized by cutting a wafer manufactured in the steps shown in FIGS. It is assumed that the power consumption is relatively large, and heat sink-like etching is performed on the back surface of WBC “1” to increase the surface area and reduce the thermal resistance.

本発明の実施例２を、図２を用いて説明する。本実施例では、ＡＳＣ「５」を２段積みにすることにより、さらに単位面積あたりの集積度をあげた、三次元半導体集積回路装置を実現している。製造は図５から図１０に示す工程を２回繰り返したのちに、図１１のバンプの生成工程を行ったウェハーを、切断することによって実現する。  A second embodiment of the present invention will be described with reference to FIG. In this embodiment, a three-dimensional semiconductor integrated circuit device is realized in which the degree of integration per unit area is further increased by stacking ASC “5” in two stages. Manufacture is realized by cutting the wafer subjected to the bump generation process of FIG. 11 after the processes shown in FIGS. 5 to 10 are repeated twice.

本発明の実施例３を、図３を用いて説明する。本実施例では、ＡＳＣ「５」を３段積みにすることにより、さらに単位面積あたりの集積度をあげた、三次元半導体集積回路装置を実現している。製造は図５から図１０に示す工程を３回繰り返したのちに、図１１のバンプの生成工程を行ったウェハーを、切断することによって実現する。  A third embodiment of the present invention will be described with reference to FIG. In this embodiment, a three-dimensional semiconductor integrated circuit device is realized in which the degree of integration per unit area is further increased by stacking ASC “5” in three stages. Manufacture is realized by repeating the steps shown in FIGS. 5 to 10 three times and then cutting the wafer on which the bump generation step of FIG. 11 has been performed.

本発明の実施例４を、図４を用いて説明する。これは、本発明の構造を持つ半導体集積回路チップ「１」と、別の集積回路チップ「９」を組み合わせて、通常のスタック構造のＳＩＰを実現した例である。本発明の半導体集積回路装置は、図１０の工程の跡にパッドを形成する。半導体集積回路チップ「１」は、リードフレーム「１０」にマウントされ、その上に別の集積回路チップ「９」をマウントする。ここで、「１２」はチップ「１」とチップ「９」を接続するボンディングワイヤー、「１３」はチップ「９」とリードフレーム「１０」を接続するボンディングワイヤー、「１４」はチップ「１」とリードフレーム「１０」を接続するボンディングワイヤー、「１１」はモールド封入材である。  A fourth embodiment of the present invention will be described with reference to FIG. This is an example of realizing a normal stack structure SIP by combining the semiconductor integrated circuit chip “1” having the structure of the present invention and another integrated circuit chip “9”. In the semiconductor integrated circuit device of the present invention, a pad is formed at the trace of the process of FIG. The semiconductor integrated circuit chip “1” is mounted on the lead frame “10”, and another integrated circuit chip “9” is mounted thereon. Here, “12” is a bonding wire connecting the chip “1” and the chip “9”, “13” is a bonding wire connecting the chip “9” and the lead frame “10”, and “14” is the chip “1”. The bonding wire connecting the lead frame “10” and “11” is a mold encapsulating material.

本発明により、複数の半導体集積回路チップを高速・高密度に集積することが可能になるため、携帯電話・ＰＤＡ・スチールカメラ・ディジタルビデオカメラ・腕時計型携帯機器等、小容積化・高性能・少消費電力を志向するシステムの実装に有効である。さらに、高速な内部バスを構成できる事よりグラフィックチップ関連、パーソナルコンピュータ等のシステムの小型化・高性能化に有効である。  According to the present invention, since a plurality of semiconductor integrated circuit chips can be integrated at high speed and high density, such as cellular phones, PDAs, still cameras, digital video cameras, wristwatch-type portable devices, etc. It is effective for the implementation of a system that aims at low power consumption. Furthermore, since a high-speed internal bus can be configured, it is effective for downsizing and high performance of graphics chip related systems, personal computers and the like.

本発明の実施例１の説明図である。本構造は、図５から図１１に示す工程で製造されたウェハーを、切断することによって実現する。ＷＢＣ「１」の裏面にヒートシンク状のエッチングを行い、表面積大きくして熱抵抗を下げている。It is explanatory drawing of Example 1 of this invention. This structure is realized by cutting the wafer manufactured in the steps shown in FIGS. A heat sink-like etching is performed on the back surface of WBC “1” to increase the surface area and reduce the thermal resistance. 本発明の実施例２の説明図である。ＡＳＣ「５」を２段積みにすることにより、さらに単位面積あたりの集積度をあげている。図５から図１０に示す工程を２回繰り返した後に、図１１のバンプの生成工程を行ったウェハーを、切断することによって実現する。It is explanatory drawing of Example 2 of this invention. By stacking ASC “5” in two stages, the degree of integration per unit area is further increased. After the process shown in FIGS. 5 to 10 is repeated twice, it is realized by cutting the wafer on which the bump generation process of FIG. 11 has been performed. 本発明の実施例３の説明図である。ＡＳＣ「５」を３段積みにすることにより、さらに単位面積あたりの集積度をあげている。図５から図１０に示す工程を３回繰り返した後に、図１１のバンプの生成工程を行ったウェハーを、切断することによって実現する。It is explanatory drawing of Example 3 of this invention. By integrating ASC “5” in three stages, the degree of integration per unit area is further increased. The process shown in FIGS. 5 to 10 is repeated three times, and then the wafer subjected to the bump generation process of FIG. 11 is cut. 本発明の実施例４の説明図である。本発明の構造の半導体集積回路チップ「１」と、別の集積回路チップ「９」を組み合わせて、通常のスタック構造のＳＩＰを実現した例である。チップ「１」には、図１０の工程の跡にパッドを形成する。半導体集積回路チップ「１」は、リードフレーム「１０」にマウントされ、その上に別の集積回路チップ「９」をマウントされ、ワイヤーボンディングをして、モールド材「１１」で封入されている。It is explanatory drawing of Example 4 of this invention. This is an example of realizing a normal stack structure SIP by combining the semiconductor integrated circuit chip “1” having the structure of the present invention and another integrated circuit chip “9”. On the chip “1”, a pad is formed at the trace of the process of FIG. The semiconductor integrated circuit chip “1” is mounted on the lead frame “10”, and another integrated circuit chip “9” is mounted on the semiconductor integrated circuit chip “1”, wire-bonded, and encapsulated with a molding material “11”. 本発明の製造工程を説明する１番目の図である。ウェハー基板「１５」を構成する配線ベースチップ（ＷＢＣ）「１」に配線工程「２」を行い、バンプ「３」を形成する。It is a 1st figure explaining the manufacturing process of this invention. A wiring process “2” is performed on the wiring base chip (WBC) “1” constituting the wafer substrate “15” to form a bump “3”. 本発明の製造工程を説明する２番目の図である。バンプ「３」を介して、ＡＳＣ「５」を電気的に接続する。It is a 2nd figure explaining the manufacturing process of this invention. The ASC “5” is electrically connected through the bump “3”. 本発明の製造工程を説明する３番目の図である。接着材料「４」で、ＡＳＣ「５」をＷＢＣ「１」に固定した後に、その裏面を研削する。It is a 3rd figure explaining the manufacturing process of this invention. After the ASC “5” is fixed to the WBC “1” with the adhesive material “4”, the back surface thereof is ground. 本発明の製造工程を説明する４番目の図である。平坦化のための絶縁膜を塗布または成長させる。It is a 4th figure explaining the manufacturing process of this invention. An insulating film for planarization is applied or grown. 本発明の製造工程を説明する５番目の図である。研削を行うことにより、ＡＳＣ「５」を貼り付けた面の平坦化を行う。It is a 5th figure explaining the manufacturing process of this invention. By performing grinding, the surface to which ASC “5” is attached is flattened. 本発明の製造工程を説明する６番目の図である。ＡＳＣ「５」の基板を絶縁するための、絶縁膜「１７」を形成するとともに、スルーホール「６」をＷＢＣ「１」のパッド「１９」上に設ける。It is a 6th figure explaining the manufacturing process of this invention. Insulating film “17” for insulating the substrate of ASC “5” is formed, and through hole “6” is provided on pad “19” of WBC “1”. 本発明の製造工程を説明する７番目の図である。再配線「７」を設けて、外部接続のためのバンプ「８」を形成する。It is a 7th figure explaining the manufacturing process of this invention. Rewiring “7” is provided to form bump “8” for external connection. 図９の本発明の製造工程におけるウェハーの状態を説明する図である。It is a figure explaining the state of the wafer in the manufacturing process of this invention of FIG. 図１１の本発明の製造工程におけるウェハーの状態を説明する図である。It is a figure explaining the state of the wafer in the manufacturing process of this invention of FIG. 従来のＳＩＰの例である。半導体チップ「２０」はリードフレーム「２２」にマウントされ、半導体チップ「２１」はチップ「２０」にマウントされる。チップ「２０」及び「２１」上のボンディング・パッドは、ワイヤー「２３」を介してリードフレーム「２２」のリード部と接続される。「２４」はモールド封入材である。It is an example of conventional SIP. The semiconductor chip “20” is mounted on the lead frame “22”, and the semiconductor chip “21” is mounted on the chip “20”. The bonding pads on the chips “20” and “21” are connected to the lead portion of the lead frame “22” via the wire “23”. “24” is a mold encapsulating material. 従来のＣＳＰの例である。半導体集積回路チップ「２５」上の配線「２６」に、追加配線「２７」を施した後にはんだや金や銅のバンプ「２８」を生成して、プリント基板等と圧着する。「２９」は、保護膜である。It is an example of conventional CSP. After the additional wiring “27” is applied to the wiring “26” on the semiconductor integrated circuit chip “25”, a bump “28” of solder, gold, or copper is generated and pressure-bonded to a printed circuit board or the like. “29” is a protective film.

符号の説明Explanation of symbols

１：ベースとなる配線工程を含むチップ（ＷＢＣ）
２：配線チップ「１」の金属配線
３：金属配線「２」と半導体集積回路チップ「５」を電気的に接続するバンプ
４：配線チップ「１」に、半導体集積回路チップ「５」を固定するための接着材料
５：配線チップ「１」に、貼り付けられる半導体集積回路チップ（ＡＳＣ）
６：金属配線「２亅と、半導体集積回路チップ「５」を貼り付けた後平坦化される面を接続するために、垂直に形成された金属配線である、スルーホール
７：スルーホール「６」と、外部接続のためのバンプ「８」を接続する配線
８：外部接続のためのバンプ
９：平坦化された面にフェースアップで貼り付けられた集積回路チップ
１０：配線チップ「１」がマウントされるリードフレーム
１１：モールド封入材
１２：チップ「１」とチップ「９」を接続するボンディングワイヤー
１３：チップ「９」とリードフレーム「１０」を接続するボンディングワイヤー
１４：チップ「１」とリードフレーム「１０」を接続するボンディングワイヤー
１５：チップ「１」を構成するウェハー
１６：平坦化のための絶縁膜
１７：半導体集積回路チップ「５」の基板と、配線「７」を絶縁する層間膜
１８：配線「７」の保護膜
１９：配線チップ「１」に設けられた接続パッド
２０〜２１：半導体集積回路チップ
２２：リードフレーム
２３：ボンディングワイヤー
２４：モールド封入材
２５：半導体基板
２６：金属配線層
２７：再配線層
２８：外部接続のためのバンプ1: Chip (WBC) including wiring process as a base
2: Metal wiring of wiring chip “1” 3: Bump for electrically connecting metal wiring “2” and semiconductor integrated circuit chip “5” 4: Semiconductor integrated circuit chip “5” is fixed to wiring chip “1” 5: A semiconductor integrated circuit chip (ASC) attached to the wiring chip “1”
6: Through hole 7: Through hole “6” which is a metal wiring formed vertically to connect the metal wiring “2 亅 and the surface to be flattened after the semiconductor integrated circuit chip“ 5 ”is attached. ”And wiring for connecting the bump“ 8 ”for external connection 8: bump for external connection 9: integrated circuit chip 10 faced up on the flattened surface: wiring chip“ 1 ” Mounted lead frame 11: Mold encapsulant 12: Bonding wire 13 connecting chip “1” and chip “9” 13: Bonding wire 14 connecting chip “9” and lead frame “10”: Chip “1” Bonding wire 15 for connecting lead frame “10”: Wafer 16 constituting chip “1”: Insulating film 17 for planarization: Semiconductor integrated circuit chip “ ”And the interlayer film 18 that insulates the wiring“ 7 ”: the protective film 19 of the wiring“ 7 ”: the connection pads 20 to 21 provided on the wiring chip“ 1 ”: the semiconductor integrated circuit chip 22: the lead frame 23: Bonding wire 24: Mold encapsulant 25: Semiconductor substrate 26: Metal wiring layer 27: Rewiring layer 28: Bump for external connection

Claims (6)

金属配線工程を終了したウェハー上の各チップに対し、複数の動作の確認された半導体集積回路チップを金属配線にフェースダウンで物理的且つ電気的に接続し、且つ貼り付けた複数の半導体集積回路チップ側の裏面を研削して平坦化の処理が行われ、且つ前述のウェハー上の各チップに金属配線工程で設けられた接続パッドが、接続パッド上に垂直に形成された金属配線を介して平坦化された面に対して電気的に接続されていること特徴とする半導体集積回路装置。  A plurality of semiconductor integrated circuits in which a plurality of semiconductor integrated circuit chips whose operations have been confirmed are physically and electrically connected to the metal wiring face-down and attached to each chip on the wafer after the completion of the metal wiring process. The back surface on the chip side is ground and flattened, and the connection pads provided in the metal wiring process on each chip on the wafer are connected through the metal wiring vertically formed on the connection pads. A semiconductor integrated circuit device characterized by being electrically connected to a planarized surface. 請求項１の半導体集積回路装置において、前述のウェハー上に存在するの各チップに対して貼り付けられた、複数の半導体集積回路チップ同士の隙間に金属配線工程で形成される接続パッドが配置され、且つその接続パッドが接続パッド上に垂直に形成された金属配線を介して平坦化された面と電気的に接続されることを特徴とする半導体集積回路装置。  2. The semiconductor integrated circuit device according to claim 1, wherein a connection pad formed by a metal wiring process is disposed in a gap between a plurality of semiconductor integrated circuit chips attached to each chip existing on the wafer. A semiconductor integrated circuit device characterized in that the connection pad is electrically connected to a planarized surface through a metal wiring formed vertically on the connection pad. 請求項１及び請求項２の半導体集積回路装置において、半導体集積回路チップを貼り付けて平坦化処理が行われ面に、絶縁層を介して外部へ電気的に接続するためのバンプが設けられ、且つ前述の接続パッド上に垂直に形成された金属配線が、新たに設けられた金属配線を介して、前述のバンプと電気的に接続される事を特徴とする半導体集積回路装置。  The semiconductor integrated circuit device according to claim 1 or 2, wherein a planarization process is performed by attaching a semiconductor integrated circuit chip, and bumps for electrically connecting to the outside through an insulating layer are provided on the surface. A semiconductor integrated circuit device characterized in that a metal wiring formed vertically on the connection pad is electrically connected to the bump via a newly provided metal wiring. 半導体集積回路装置において、（１）金属配線工程と、（２）動作の確認された半導体集積回路チップをフェースダウンで電気的・物理的に金属配線に接続する工程と、（３）ウェハーと貼り付けられた半導体集積回路チップの隙間を絶縁物で埋める工程と、（４）貼り付けられた半導体集積回路チップ側の裏面を研削して平坦化し、金属配線工程で設けられた接続パッドより平坦化された面に対して垂直方向の金属配線を形成する工程を有し、これらの工程を１回以上繰り返すことにより製造される事を特徴とする三次元半導体集積回路装置。  In a semiconductor integrated circuit device, (1) a metal wiring step, (2) a step of electrically and physically connecting a semiconductor integrated circuit chip whose operation has been confirmed face down, and (3) bonding a wafer A step of filling the gap between the attached semiconductor integrated circuit chips with an insulator, and (4) grinding and flattening the back surface on the side of the attached semiconductor integrated circuit chip, and flattening from the connection pads provided in the metal wiring step A three-dimensional semiconductor integrated circuit device comprising a step of forming a metal wiring in a direction perpendicular to a formed surface and repeating these steps one or more times. 請求項４の半導体集積回路装置において、前述の平坦化された面に形成された垂直方向の金属配線に電気的に接続された再配線層を形成する工程と、再配線層上に外部へ接続するためのバンプあるいはボンディング・パッドを形成する工程と、ウェハーを各チップに切断する工程により製造される事を特徴とする三次元半導体集積回路装置。  5. The semiconductor integrated circuit device according to claim 4, wherein a step of forming a rewiring layer electrically connected to the vertical metal wiring formed on the flattened surface is connected to the outside on the rewiring layer. A three-dimensional semiconductor integrated circuit device manufactured by a process of forming bumps or bonding pads for performing the process and a process of cutting the wafer into chips. 請求項１及び請求項２の半導体集積回路装置において、半導体集積回路チップを貼り付けて平坦化処理が行われ面に、絶縁層を介して外部へ電気的に接続するためのボンディング・パッドが設けられ、且つ平坦化された面に絶縁層を介して集積回路チップがフェースアップで配置・固定され、且つ前述のボンディング・パッドが、配置された集積回路チップ上の接続パッドと電気的に接続されている事を特徴とする半導体集積回路装置。  3. The semiconductor integrated circuit device according to claim 1, wherein a planarization process is performed by attaching a semiconductor integrated circuit chip, and a bonding pad is provided on the surface for electrical connection to the outside through an insulating layer. The integrated circuit chip is arranged and fixed face-up through an insulating layer on the planarized surface, and the above-described bonding pads are electrically connected to the connection pads on the arranged integrated circuit chip. A semiconductor integrated circuit device characterized by that.
JP2003373420A 2003-09-29 2003-09-29 Three-dimensional semiconductor integrated circuit device Pending JP2005109419A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741723B2 (en) 2006-06-30 2010-06-22 Fujitsu Semiconductor Limited Semiconductor device comprising chip on chip structure
US8367468B2 (en) 2006-07-11 2013-02-05 National Institute Of Advanced Industrial Science And Technology Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741723B2 (en) 2006-06-30 2010-06-22 Fujitsu Semiconductor Limited Semiconductor device comprising chip on chip structure
EP2634804A1 (en) 2006-06-30 2013-09-04 Fujitsu Semiconductor Limited Semiconductor device
EP2637205A1 (en) 2006-06-30 2013-09-11 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of same
US8367468B2 (en) 2006-07-11 2013-02-05 National Institute Of Advanced Industrial Science And Technology Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same
US8399979B2 (en) 2006-07-11 2013-03-19 National Institute Of Advanced Industrial Science And Technology Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same

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