KR101971059B1 - Semiconductor package sliming apparatus and method of the same - Google Patents

Semiconductor package sliming apparatus and method of the same Download PDF

Info

Publication number
KR101971059B1
KR101971059B1 KR1020160064862A KR20160064862A KR101971059B1 KR 101971059 B1 KR101971059 B1 KR 101971059B1 KR 1020160064862 A KR1020160064862 A KR 1020160064862A KR 20160064862 A KR20160064862 A KR 20160064862A KR 101971059 B1 KR101971059 B1 KR 101971059B1
Authority
KR
South Korea
Prior art keywords
semiconductor package
package
unit
polishing
spindle
Prior art date
Application number
KR1020160064862A
Other languages
Korean (ko)
Other versions
KR20170133722A (en
Inventor
박종현
박기삼
손희진
오현우
Original Assignee
주식회사 케이엔제이
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 케이엔제이 filed Critical 주식회사 케이엔제이
Priority to KR1020160064862A priority Critical patent/KR101971059B1/en
Publication of KR20170133722A publication Critical patent/KR20170133722A/en
Application granted granted Critical
Publication of KR101971059B1 publication Critical patent/KR101971059B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection

Abstract

The present invention relates to an apparatus and method for reducing the thickness of a semiconductor package, and more particularly, to an apparatus and a method for reducing the thickness of a semiconductor package, in which even if warpage is severe in a strip state, And more particularly, to a semiconductor package slimming device and method.
A semiconductor package slimming apparatus according to the present invention comprises: a table for sucking unit packages cut in chip units in a strip-shaped semiconductor package; A spindle disposed above the table; Polishing means for polishing the molding surface of the unit package, which is rotated by the spindle and is seated on the table, to reduce the thickness of the unit package; And conveying means for relatively moving the table or the spindle horizontally.

Description

Technical Field [0001] The present invention relates to a semiconductor package slimming apparatus and method,

The present invention relates to an apparatus and method for reducing the thickness of a semiconductor package, and more particularly, to an apparatus and a method for reducing the thickness of a semiconductor package, in which even if warpage is severe in a strip state, And more particularly, to a semiconductor package slimming device and method.

In recent years, with the development of semiconductor device manufacturing technology, semiconductor packages having semiconductor devices suitable for processing more data in a short time have been developed.

A semiconductor package is manufactured by die bonding a semiconductor chip on a pad of a substrate material such as a lead frame or a printed circuit board and wire bonding the lead of the lead frame or the terminal of the printed circuit board and the semiconductor chip, And an epoxy molding compound (EMC) around the wire to protect the connection part of the wire.

Figures 1 and 2 illustrate a typical semiconductor package 100. As shown in the figure, the semiconductor chip 120 is wire-bonded on the printed circuit board 110 and the molding part 130 is formed. The semiconductor chip 120 includes a wafer 121 and a wire bonder 122.

However, the use of the printed circuit board 110 or the lead frame for signal transmission of the stacked semiconductor chips 120 and the formation of the molding part 130 molded by resin for protecting the semiconductor chip 120 are inevitable The total thickness t0 of the semiconductor package 100 is increased.

In recent years, there has been a problem in that it is difficult to cope with the trend of miniaturization of electronic devices and slimness of information communication devices.

In order to solve such a problem, the present applicant has filed a patent application No. 1347026. [

3 and 4, a conventional slimming apparatus 1 includes a table 10, a conveying means 30, and a polishing means 20. As shown in FIG.

The table 10 is a component for vacuum-adsorbing the semiconductor package 100 in a strip state, and therefore, a vacuum hole 12 is formed. The conveying means 30 is a component for horizontally reciprocating the table 10. The conveying means 30 is operated by a driving source (not shown) while supporting the table 10 and horizontally reciprocates along the guide portion.

The polishing means 20 includes a polishing stone 21 for polishing the semiconductor package and a spindle 22 for rotating the polishing stone 21. The polishing grindstone is formed in a cylindrical shape and the package is polished and slipped by using the circumferential surface of the grinding stone in a state where the direction of the rotation axis of the grinding stone 21 is parallel to the semiconductor package 100.

5 and 6 show another conventional slimming apparatus 200, which was filed by the present applicant as a patent application No. 2016-63061.

A spindle 220 disposed above the table with the semiconductor package mounted horizontally on the table, a rotary disk 210 and a polishing tip 211.

The rotation axis of the spindle 220 is arranged to be orthogonal to the semiconductor package.

And a rotating disk 210 connected to the rotating shaft of the spindle 220 and rotating. The rotating disc 210 is formed in a disc shape as a whole, and its central portion is cut for coupling with the spindle 220.

Further, the polishing tip 211 protrudes downward along the circumference of the rotary disk 210. The polishing tip 211 is formed in a ring shape as a whole, and the direction of the axis of rotation is orthogonal to the substrate 10. The polishing tip 211 is provided with a slit 212 for supplying or discharging polishing water.

Further, a transfer means (not shown) for relatively moving the spindle 220 and the table to polish the molding surface of the semiconductor package is provided. Relative movement is to horizontally move the spindle 220 while the table is stopped or horizontally to move the table while the spindle 220 is stopped. It also includes transferring the spindle 220 and the table simultaneously in opposite directions.

On the other hand, the semiconductor package may be deformed during the manufacturing process. Warpage occurs as shown in Fig. 7 or 8 (a).

In this case, even if the semiconductor package 100 in a strip state is vacuum-adsorbed to the table 10, it is adsorbed in a deformed shape without being flatly adsorbed (refer to FIG. 7). Or if the semiconductor package 100 is bent in the strip state and does not come into close contact with the table 10, airtightness may not be maintained and the semiconductor package 100 may not be adsorbed. Therefore, there is a problem that the semiconductor package 100 is not firmly fixed (refer to FIG. 7) and the thickness after polishing is uneven (see FIG. 8 (b)).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor package which can be flatly and firmly adsorbed even when a warpage phenomenon is severe in a strip state, And a package slimming apparatus and method.

According to an aspect of the present invention, there is provided a semiconductor package slimming apparatus comprising: a table for sucking unit packages cut in chip units in a strip-shaped semiconductor package; A spindle disposed above the table; Polishing means for polishing the molding surface of the unit package, which is rotated by the spindle and is seated on the table, to reduce the thickness of the unit package; And conveying means for relatively moving the table or the spindle horizontally.

In addition, it is preferable that a plurality of seating grooves on which the unit packages are seated are formed on the table.

Preferably, the polishing means is formed in a cylindrical shape, and the direction of the rotation axis is parallel to the unit package.

It is preferable that the polishing means is formed in a ring shape, and the direction of the rotation axis is perpendicular to the unit package.

A semiconductor package slimming method according to the present invention comprises the steps of: 1) cutting a semiconductor package in a strip state into chips; 2) adsorbing each of the unit packages cut in a chip unit to a table; And 3) reducing the thickness by polishing the molding surface of the unit package while moving the table or the polishing means relative to each other.

Particularly, the semiconductor package in the strip state is preferably a semiconductor package having a warpage phenomenon.

Preferably, the polishing means is formed in a cylindrical shape having a rotation axis direction parallel to the unit package, and the molding surface of the unit package is polished using a circumferential surface.

It is preferable that the polishing means is formed in a ring shape in which the direction of the axis of rotation is orthogonal to the unit package.

According to the present invention, even when the semiconductor package has a severe warpage phenomenon in a strip state, the semiconductor package can be flatly and strongly adsorbed.

Accordingly, the thickness of the semiconductor package can be uniformly slimmed.

1 shows a semiconductor package in a strip state.
2 shows a cross-sectional view of a semiconductor package.
3 and 4 show a conventional slimming apparatus.
5 and 6 show other conventional slimming apparatuses.
FIGS. 7 and 8 show a slimming method of a semiconductor package in a strip state in which a conventional warpage is severe.
9 to 11 show the configuration of a slimming apparatus according to the present invention.
12 and 13 show a slimming method according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a configuration and an operation of an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

A semiconductor slimming apparatus according to the present invention includes a table, a spindle, a polishing means, and a transfer means.

Referring to FIG. 9, the table 400 includes a plurality of seating grooves 411, and vacuum holes 412 are formed in the seating grooves 411, respectively. The seating groove 411 is a structure for individually mounting the unit package ('101' in FIG. 11).

In the meantime, the unit packages separated in units of chips are seated in the seating grooves 411 of the table 400, and the unit packages are separated into chip units in the strip-shaped semiconductor package shown in FIG.

10 shows a cutting apparatus 300 for forming a unit package. A unit package (101 'in FIG. 11) is formed by cutting the package 130 from the molding part 130 to the printed circuit board 110 by a cutting device (saw) 300 provided on a semiconductor package 100 in a strip state . The cutting apparatus 300 is a known means for cutting a semiconductor package using a cutter or a laser, and thus a detailed description thereof will be omitted.

11 shows a state in which the unit packages 101 are vacuum-adsorbed in a state where the unit packages 101 are placed in the seating grooves 411 of the table 400. FIG. In particular, in the case where the semiconductor package in the strip state is a semiconductor package having a warpage phenomenon, the unit package is cut into unit packages by the cutting device 300, The semiconductor package can be flatly adsorbed because there is no warping phenomenon. In addition, since the unit package is flatly adsorbed, the vacuum pressure is not leaked, and stable and stable adsorption can be performed.

Hereinafter, an operation state of the semiconductor package slimming apparatus according to the present invention and a slimming method using the same will be described.

12 shows an embodiment of a slimming method according to the present invention. As shown in the figure, the table 400 vacuum-adsorbs the unit packages 101 cut in chip units using the pneumatic pressure applied through the vacuum holes 412 in a state in which the unit packages 101 are seated in the seating grooves 411, respectively. Even if a semiconductor package having a warpage is cut, the unit package is firmly adsorbed flatly without warpage.

On the other hand, on the upper part of the table 400, a polishing grindstone 21 of cylindrical shape is provided as the polishing means 20. The polishing grindstone 21 is rotated by a spindle provided with a rotating shaft in a horizontal direction (see "20" in FIG. 3). That is, the cylindrical surface of the polishing means 20 is polished by using the circumferential surface in a state where the rotation axis is arranged parallel to the unit package 101.

Fig. 13 shows another embodiment of the slimming method according to the present invention. As in the previous embodiment, the table 400 vacuum-adsorbs the unit packages 101, which are cut in chip units, by using air pressure applied through the vacuum holes 412 in a state where the unit packages 101 are seated in the respective seating grooves.

On the other hand, a polishing tip 211 in the form of a ring is provided as an abrasive means 200 on the table 400. The polishing tip 211 is rotated by a spindle 220 whose rotation axis is installed in a direction orthogonal to the unit package 101. In other words, the ring-shaped polishing tip 211 is polished on the molding surface in a state where the rotation axis is perpendicular to the unit package 101.

In the present embodiment, an apparatus and a method for slimming a semiconductor package mounted with a semiconductor chip on a printed circuit board have been described. However, the slimming apparatus and method according to the present invention are also applicable to slimming of a semiconductor package mounted on a lead frame It is natural that it can be applied to. It is of course also possible to apply not only to semiconductor packages but also to reduce the thickness of various substrates.

10: Polishing means
21: abrasive wheel
200: polishing means
211: Abrasive tip
220: spindle
400: Table
411: seat groove
412: Vacuum hole

Claims (8)

A table for individually adsorbing unit packages cut in a chip unit in a semiconductor package in a strip state;
A spindle disposed above the table;
Polishing means for polishing the molding surface of the unit package, which is rotated by the spindle and is seated on the table, to reduce the thickness of the unit package; And
And conveying means for relatively moving the table or the spindle horizontally,
Wherein the table has a plurality of seating grooves on which the unit packages are seated, a vacuum hole is formed in each of the seating grooves,
Wherein the polishing means is formed in a ring shape and the direction of rotation axis is orthogonal to the unit package.
delete delete delete delete delete delete delete
KR1020160064862A 2016-05-26 2016-05-26 Semiconductor package sliming apparatus and method of the same KR101971059B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020160064862A KR101971059B1 (en) 2016-05-26 2016-05-26 Semiconductor package sliming apparatus and method of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020160064862A KR101971059B1 (en) 2016-05-26 2016-05-26 Semiconductor package sliming apparatus and method of the same

Publications (2)

Publication Number Publication Date
KR20170133722A KR20170133722A (en) 2017-12-06
KR101971059B1 true KR101971059B1 (en) 2019-04-23

Family

ID=60922246

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160064862A KR101971059B1 (en) 2016-05-26 2016-05-26 Semiconductor package sliming apparatus and method of the same

Country Status (1)

Country Link
KR (1) KR101971059B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114291571B (en) * 2022-01-11 2023-09-22 业成科技（成都）有限公司 Adsorption device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003236735A (en) 2002-02-20 2003-08-26 Sumitomo Electric Ind Ltd Wafer grinding method
JP2007005366A (en) * 2005-06-21 2007-01-11 Toshiba Corp Method of manufacturing semiconductor device
JP2011258789A (en) * 2010-06-10 2011-12-22 Lapis Semiconductor Co Ltd Grinding method and grinder
JP2014024136A (en) * 2012-07-25 2014-02-06 Disco Abrasive Syst Ltd Method of processing package substrate

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2789166B2 (en) * 1994-05-11 1998-08-20 畑村 洋太郎 Grinding method
JPH09174398A (en) * 1995-12-26 1997-07-08 Toshiba Corp Grinding device and grinding wheel
JP3472784B2 (en) * 1997-05-16 2003-12-02 株式会社岡本工作機械製作所 Grinding and polishing equipment
JP2015223667A (en) * 2014-05-28 2015-12-14 株式会社ディスコ Griding device and grinding method for rectangular substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003236735A (en) 2002-02-20 2003-08-26 Sumitomo Electric Ind Ltd Wafer grinding method
JP2007005366A (en) * 2005-06-21 2007-01-11 Toshiba Corp Method of manufacturing semiconductor device
JP2011258789A (en) * 2010-06-10 2011-12-22 Lapis Semiconductor Co Ltd Grinding method and grinder
JP2014024136A (en) * 2012-07-25 2014-02-06 Disco Abrasive Syst Ltd Method of processing package substrate

Also Published As

Publication number Publication date
KR20170133722A (en) 2017-12-06

Similar Documents

Publication Publication Date Title
US6337258B1 (en) Method of dividing a wafer
KR102185238B1 (en) Grinding apparatus and method for grinding rectangular substrate
TWI824024B (en) Grinding method of rectangular substrate
JP2015223667A (en) Griding device and grinding method for rectangular substrate
KR101971059B1 (en) Semiconductor package sliming apparatus and method of the same
KR20190024698A (en) Multiblade and method for processing a workpiece
KR101347026B1 (en) Semiconductor package sliming apparatus and method of the same
JP2015199153A (en) Holding table, and grinding method and cutting method using the same
KR101749482B1 (en) Semiconductor package sliming apparatus and method of the same
KR101464130B1 (en) Semiconductor package sliming apparatus and method of the same
KR101347027B1 (en) Semiconductor package sliming apparatus and method of the same
JP7152882B2 (en) How to hold the workpiece unit
KR101759125B1 (en) Semiconductor package sliming apparatus and method of the same
JP3696900B2 (en) Surface grinding machine for grinding resin for sealing electronic parts
KR101347029B1 (en) Semiconductor package sliming apparatus and method of the same
KR101448502B1 (en) Semiconductor package sliming apparatus and method of the same
KR101347028B1 (en) Semiconductor package sliming apparatus and method of the same
JP3751631B2 (en) Electronic component sealing method
KR20080113682A (en) Grinding wheel for wafer and wafer back grinding apparatus having the same
KR101762192B1 (en) Semiconductor package sliming apparatus and method of the same
KR101362243B1 (en) Semiconductor package sliming apparatus
KR20170132051A (en) Semiconductor package sliming apparatus and method of the same
KR101327527B1 (en) Semiconductor package sliming apparatus and method of the same
KR101347030B1 (en) Semiconductor package sliming apparatus and method of the same
JP2023058925A (en) Method for manufacturing wafer, and chuck table

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
J201 Request for trial against refusal decision
J301 Trial decision

Free format text: TRIAL NUMBER: 2017101004367; TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20170913

Effective date: 20190318

S901 Examination by remand of revocation
GRNO Decision to grant (after opposition)
GRNT Written decision to grant