KR101318217B1 - Liquid crystal Display device and method for fabricating of the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of improving signal transmission efficiency of a link line and a method of manufacturing the same, including: a liquid crystal panel having an image display unit; A first pad connected to an integrated circuit, a second pad formed on the liquid crystal panel to input an external signal, and first and second lines overlapping each other with an insulating layer interposed therebetween to electrically connect the first and second pads. It characterized in that it comprises a link line connecting to.

Link part, link line, pad part,

Description

Liquid crystal display device and method for fabricating of the same

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a link unit and a pad unit illustrated in FIG. 1.

3 is a cross-sectional view showing a III-III 'section of FIG. 2 in accordance with an embodiment of the present invention.

4 is a cross-sectional view illustrating III-III ′ of FIG. 2 according to another embodiment of the present invention.

5A through 5C are cross-sectional views illustrating a method of manufacturing the link line and the pad unit illustrated in FIG. 4 in stages.

6 is a cross-sectional view illustrating III-III ′ of FIG. 2 according to another embodiment of the present invention.

＊ Description of symbols for main parts of the drawings ＊

2: liquid crystal panel 4: driving integrated circuit

6: circuit film 8: link part

P: pixel area LkL: link line

L1: first line L2a: semiconductor layer

L2b: source / drain layer L3: third line

GL1 to GLn: first to nth gate lines

DL1 to DLm: first to mth data lines

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same that can improve signal transmission efficiency of a link line.

Recently, liquid crystal displays, field emission displays, plasma display panels, and light emitting displays are emerging as flat panel displays.

Among the flat panel displays, liquid crystal displays are actively applied to notebooks, desktop monitors, and mobile terminals due to their excellent resolution, color display, and image quality.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a liquid crystal cell, a backlight unit for applying light to the liquid crystal panel, and a driving circuit for driving the liquid crystal cell.

Here, the driving circuit includes a drive integrated circuit for driving the liquid crystal cell, and according to a method of connecting the driving integrated circuit to the liquid crystal panel, a tape carrier package and a chip on film Film) and chip on glass (hereinafter referred to as 'COG').

A conventional liquid crystal display (COG) using a COG method includes a liquid crystal panel in which pixel cells are formed in each region defined by a plurality of data and gate lines, a driving integrated circuit driving data and a gate line, and generating a control signal for driving integration. And a link unit for electrically connecting the circuit film and the driving integrated circuit to supply a control signal from the control unit to the driving integrated circuit.

The circuit film supplies control signals, driving power, and the like from the controller to the driving integrated circuit. In this case, the circuit film is a flexible printed circuit film and is electrically connected to a pad part provided at one end of the link part by an anisotropic conductive film.

The link unit is formed of a plurality of link lines, and pads are formed on one side and the other side of the link line. One end of the link line is electrically connected to the conductive material through a contact hole formed in the pad, and the conductive material of the pad is connected to the anisotropic conductive film to be electrically connected to the circuit film. Meanwhile, pads are formed at the other end of the link line to electrically connect with the driving integrated circuit. Here, the link line is formed of a metal material such as data and gate line on the semiconductor substrate.

However, a plurality of link lines formed in the link portion are formed in a single line within a limited area and have a width of several micrometers (µm). Specifically, each link line has a large resistance in transmitting electrical signals because its cross section is very small. Accordingly, there is a problem that the signal transmission efficiency of the link lines are inferior.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a liquid crystal display and a method of manufacturing the same, which can improve signal transmission efficiency of a link line.

The liquid crystal display according to the embodiment of the present invention for achieving the above object is a liquid crystal panel having an image display unit, a drive integrated circuit mounted on the liquid crystal panel to drive the image display unit, and the first and second connection to the drive integrated circuit; A first pad, a second pad formed on the liquid crystal panel to input an external signal, and a link line formed to overlap the first and second lines with an insulating layer interposed therebetween to electrically connect the first and second pads. It is characterized by including.

Each of the first and second pads exposes a first conductive layer extending from the first line, a second conductive layer extending from the second line, a protective film formed on the second conductive layer, and the first conductive layer. And a third contact layer electrically connecting the first and second lines through the first contact hole, the second contact hole to expose the second conductive layer, and the first and second contact holes. It is done.

The link line further includes a third line extending from the third conductive layer and overlapping the second line with the passivation layer therebetween.

In addition, the manufacturing method of the liquid crystal display device according to an embodiment of the present invention for achieving the above object comprises the steps of forming a link line having a first line and a second line overlapped with an insulating film therebetween, And forming first and second pads connected at both ends, respectively.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to an embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 1 drives a liquid crystal panel 2 having an image display unit IP for displaying an image, and drives data lines DL1 to DLm and gate lines GL1 to GLn of the image display unit IP. Supplying the integrated circuit 4 to the integrated circuit 4, a circuit film 6 on which a control unit for generating a control signal for controlling the integrated integrated circuit 4 is mounted, and a control signal from the controller to the driving integrated circuit 4. And a link unit 8 electrically connecting the circuit film 6 and the driving integrated circuit 4 to one side and the other side of the link unit 8 so as to provide a circuit film 6 and the driving integrated circuit 4. And a pad portion (not shown) for electrically connecting with the link portion 8.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region P defined by a plurality of gate lines GL1 through GLn and a plurality of data lines DL1 through DLm, a TFT, A connected liquid crystal capacitor is provided. The liquid crystal capacitor is composed of a pixel electrode connected to a TFT and a common electrode facing each other with the pixel electrode and the liquid crystal interposed therebetween. The TFT supplies the data signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor charges the difference voltage between the data signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. Storage capacitors are connected to the liquid crystal capacitors in parallel so that the voltage charged in the liquid crystal capacitor is maintained until the next data signal is supplied. The storage capacitor is formed by overlapping pixel electrodes with a previous gate line and an insulating layer interposed therebetween. In contrast, the storage capacitor may be formed by overlapping pixel electrodes with a storage line and an insulating layer therebetween.

In the mobile and portable liquid crystal display devices, a plurality of gate lines GL1 to GLn may be alternately disposed on one side and the other side of the liquid crystal panel 2.

The driving integrated circuit 4 includes a gate driver and a data driver, and is formed as a single chip. Accordingly, the driving integrated circuit 4 drives the data lines DL1 to DLm and the gate lines GL1 to GLn in accordance with data and gate control signals from a controller (not shown). Specifically, the driving integrated circuit 4 sequentially generates scan pulses, that is, gate high pulses, in response to the gate control signal, and supplies them to the gate lines GL1 to GLn. The controller converts the digital image data from the controller into analog image data and supplies one horizontal line of analog image data to the data lines DL1 through DLm every horizontal period in which scan pulses are supplied to the gate lines GL1 through GLn. . That is, a gamma voltage having a predetermined level is selected according to the gray value of the analog image data, and the selected gamma voltage is supplied to the data lines DL1 to DLm.

As described above, in a liquid crystal display device such as a portable and mobile device, the gate driver and the data driver may be formed in one driving integrated circuit 4, but the gate and data driver may be formed of different integrated circuits.

Although not shown in the circuit film 6, a control unit for supplying gate and data control signals, image data, and driving power to the driving integrated circuit 4 is mounted. Accordingly, the circuit film 6 supplies the gate and data control signals, the image data, the driving power, and the like from the controller to the driving integrated circuit 4. Here, the circuit film 6 is a flexible printed circuit film and is connected to a pad portion provided on one side of the link portion 8 by an anisotropic conductive film.

 The link portion 8 is formed of a plurality of link lines, and each link line is formed of a double layer or a triple layer such that a gate material, a source / drain forming material, a transparent conductive material, and the like overlap each other with an insulating film interposed therebetween. Pad portions are formed at one side and the other side of the link unit 8, respectively. The link part 8 electrically connects the circuit film 6 and the driving integrated circuit 4 through the pad part and the anisotropic conductive film formed at both ends.

The pad part electrically connects the lines of the double layer and the triple layer by forming a plurality of contact holes at both ends of each link line and forming a conductive material to cover the plurality of contact holes.

The link line and the pad portion of the present invention as described above are integrally formed on the lower substrate of the liquid crystal panel 2 during the TFT array process.

FIG. 2 is a diagram illustrating a link unit and a pad unit illustrated in FIG. 1.

The link portion 8 and the first and second pad portions PD1 and PD2 shown in FIG. 2 are collectively disposed under the liquid crystal panel 2 in order to minimize the formation area thereof. The link unit 8 may include a plurality of link lines LkL, and the plurality of link lines LkL may be formed in a shape having at least one bend. The first and second pad portions PD1 and PD2 are formed at one side and the other side of the plurality of link lines LkL, respectively. Here, at least one contact hole CT1 to CT4 is formed in the first and second pad parts PD1 and PD2 to electrically connect each layer of the link line LkL formed of a double layer or a triple layer.

3 is a cross-sectional view illustrating a III-III ′ section of FIG. 2 according to an embodiment of the present invention.

The link line LkL illustrated in FIG. 3 includes a semiconductor layer such that the first line L1 formed of a gate material on the substrate 20 and the first line L1 overlap with each other with the insulating layer 21 interposed therebetween. A second line L2 formed of L2a and a source / drain material L2b, and a passivation layer 23 formed on the entire surface of the substrate 20 including the second line L2 are included. Here, an ohmic contact layer is further formed between the semiconductor layer L2a of the second line L2 and the source / drain material L2b so as to overlap the first line L1 although not shown in the drawing.

The first pad PD1 penetrates the second line L2 to contact the first line L1, and penetrates the passivation layer 23 to contact the second line L2. A first conductive material 24, that is, a transparent conductive layer, electrically connecting the first and second lines L1 and L2 through the second contact hole CT2 and the first and second contact holes CT1 and CT2. It includes. The second pad PD2 penetrates through the passivation layer 23 and penetrates through the third contact hole CT3 and the second line L2a and L2b that are in contact with the second line L2a and L2b. ) And a second conductive material 25 electrically connecting the first and second lines L1 and L2 through the fourth contact hole CT4 and the third and fourth contact holes CT3 and CT4. That is, it contains a transparent conductive layer.

As described above, the link line LkL is composed of the first line L1 and the second line L2, and even if the width thereof is formed to several micrometers (μm), the cross-sectional area increases to reduce the resistance. In addition, since the contact surfaces of the first to fourth contact holes CT1 to CT4, the first line L1, and the second line L2 are wide, the decrease in resistance caused by the contact holes CT1 to CT4 may be minimized.

4 is a cross-sectional view illustrating III-III ′ of FIG. 2 according to another embodiment of the present invention.

The link line LkL illustrated in FIG. 4 and the first and second pad portions PD1 and PD2 have the same configuration except for the first and second conductive materials 24 and 25 illustrated in FIG. 3. In detail, the third line L3 illustrated in FIG. 4 is formed to overlap the first and second lines L1 and L2 with the passivation layer 23 therebetween. That is, the first and second conductive materials 24 and 25 electrically connect the first and second lines L1 and L2 through the first to fourth contact holes CT1 to CT4, as well as the first and second conductive materials 24 and 25. It is formed to cover all of the second lines L1 and L2. Accordingly, the link line LkL according to another embodiment of the present invention includes the first and second lines L1 and L2 and the third line L3 made of a conductive material.

As described above, the link line LkL according to another embodiment of the present invention is composed of first to third lines L3. Accordingly, even if the width is formed to a few micrometers (µm), the cross-sectional area is increased than the link line (LkL) consisting of a double layer can significantly reduce the resistance. In addition, since the contact surfaces of the first to fourth contact holes CT1 to CT4, the first line L1, and the second line L2 are wide, the decrease in resistance caused by the contact holes CT1 to CT4 may be minimized.

5A through 5C are cross-sectional views illustrating a method of manufacturing the link line and the pad unit illustrated in FIG. 4 step by step.

First, as shown in FIG. 5A, the gate metal layer is deposited on the substrate 20 through a deposition method such as a sputtering method. The first line L1 is formed by a photolithography process and an etching process using a mask. Here, chromium (Cr), molybdenum (Mo), aluminum-based metal, or the like is used as the gate metal for forming the gate line and the first line L1 in a single layer or a double layer structure.

Subsequently, the insulating film 21, the amorphous silicon layer L2a, the n + amorphous silicon layer and the source / drain metal layer L2b are sequentially formed through a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or sputtering. Is formed. A photoresist pattern (not shown) is formed on the source / drain metal layer L2b by performing a photolithography process using a mask. Next, the n + amorphous silicon layer, the amorphous silicon layer L2a and the source / drain metal layer L2b are simultaneously patterned by a dry etching process using a photoresist pattern. As a result, the semiconductor layer L2a and the source / drain metal layer L2b constituting the second line L2 are formed. Here, the second line L2 is formed in the same manner when the data line is formed.

As the material of the insulating film 21, an inorganic insulating material or an organic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the source / drain metal layer L2b, chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), or the like is used.

Thereafter, the protective film 25 is formed on the entire surface of the insulating film 21 on which the semiconductor layer L2a and the source / drain layer L2b are formed by a deposition method such as PECVD or a coating method such as spinless. As the material of the protective film 25, an inorganic insulating material such as the insulating film 21 or an organic insulating material such as an acrylic organic compound having a low dielectric constant, silicon oxide (SiOx), silicon nitride (SiNx), BCB, or PFCB may be used. Is used.

Next, as shown in FIG. 5B, the first to fourth contact holes exposing a portion of the first line L1 and the second line L2 by patterning the passivation layer 25 by a photolithography process and an etching process. (CT1 to CT4) are formed. Here, the first and fourth contact holes CT1 and CT4 pass through the passivation layer 25 and the insulating layer 21 to expose a part of the first line L1, but the second and third contact holes CT2 and Since CT3 penetrates only the protective film 25, a part of the second line L2, that is, a part of the source / drain metal layer L2b is exposed.

Thereafter, as illustrated in FIG. 5C, a conductive material layer for electrically connecting the first line L1 and the second line L2, that is, a conductive material for forming the third line L3 may be sputtered or the like. It is formed by the deposition method of. In this case, the conductive material, that is, the third line L3 electrically connects the first line L1 and the second line L2 and, through the photolithography and etching process, the first and second lines L1, It is formed to overlap with L2).

A conductive material, that is, a transparent conductive layer, which is a material for forming the third line L3, is used in the same manner when forming a pixel electrode, and indium-tin-oxide (ITO), IZO, ITZO, TO, and the like are used. On the other hand, in the case of a semi-transmissive liquid crystal display device, instead of a conductive material such as ITO, it may be formed of the same reflective metal layer as the reflective electrode of the image display area.

6 is a cross-sectional view illustrating III-III ′ of FIG. 2 according to another embodiment of the present invention.

The link line LkL illustrated in FIG. 6 has a first line L1 formed of a gate metal and a second line L2 formed of a conductive material so as to overlap the first line L1 with an insulating film 21 therebetween. Is done. In addition, one contact hole CT1 and CT2 is formed in the first and second pad parts PD1 and PD2 to electrically connect the first line L1 and the second line L2.

A method of manufacturing the link line LkL and the first and second pad parts PD1 and PD2 according to another embodiment of the present invention is as follows.

First, chromium (Cr), molybdenum (Mo), aluminum-based metal, etc. are deposited in a single layer or double layer structure, and then patterned to form a first line L1.

Subsequently, an inorganic insulating material or an organic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface of the substrate 20 including the first line L1.

Next, amorphous silicon, n + amorphous silicon, source / drain metal, and the like are deposited, which are removed by both photolithography and etching processes.

Subsequently, a protective film is formed on the entire surface of the insulating film 21 by a deposition method such as PECVD or a coating method such as spinless. The photolithography process and the etching process are performed to form first and second contact holes CT1 and CT2 to expose a portion of the first line L1. The protective layer may be removed by an etching process when the first and second contact holes CT1 and CT2 are formed as shown in FIG. 6, or may not be removed as shown in FIG. 5C.

Subsequently, the substrate 20 including the first and second contact holes CT1 and CT2 may be formed of a conductive material such as ITO (ITO), IZO, ITZO, TO, etc. to form the second line L2. Form on the front of the. The second line L2 is formed to overlap the first line L1 by performing a photolithography process and an etching process.

As described above, the link line LkL according to another embodiment of the present invention allows the second line L2 to be formed with the first line L1 formed of the gate metal and the insulating layer 21 interposed therebetween. In the second line L2, a transparent conductive material ITO (Imdium-Tin-Oxide), IZO, ITZO, TO, or the like is used. Accordingly, the resistance can be reduced by increasing the cross-sectional area of the link line LkL. In addition, unlike the link line LkL of the triple layer formed by the first to third lines L1 to L3, the conductive material is formed as the second line L2, so that the plurality of link lines LkL and the pad portions PD1, It is also possible to overcome the step difference in the region where the PD2) is formed.

As described above, the link line LkL according to the embodiment of the present invention is first, second and third lines (L1, L2, L3) are electrically connected to form a double layer or triple layer structure. Accordingly, it is possible to increase the signal transmission efficiency of the link line LkL and to prevent a failure due to disconnection of the link line LkL.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the liquid crystal display and the manufacturing method thereof according to the present invention have the following effects.

In the present invention, the first, second and third lines are electrically connected to form a link line of a double layer or triple layer structure. Accordingly, the liquid crystal display and the method of manufacturing the same according to the present invention can increase the signal transmission efficiency of the link line and can prevent a defect due to the disconnection of the link line.

Claims (13)

A liquid crystal panel having an image display unit; A driving integrated circuit mounted on the liquid crystal panel to drive an image display unit; A first pad connected with the driving integrated circuit; A second pad formed on the liquid crystal panel to input an external signal; A link line formed to overlap the first and second lines with the insulating layer interposed therebetween to electrically connect the first and second pads; Each of the first and second pads exposes a first conductive layer extending from the first line, a second conductive layer extending from the second line, a protective film formed on the second conductive layer, and the first conductive layer. And a third contact layer electrically connecting the first and second lines through the first contact hole, the second contact hole exposing the second conductive layer, and the first and second contact holes. The link line And a third line extending from the third conductive layer and overlapping the second line with the passivation layer therebetween. delete delete The method of claim 1, The first line is formed on the same layer of the same metal layer as the gate line when forming the gate line of the image display unit, The second line is formed on the same layer as the same metal layer as the data line when the data line of the image display unit is formed. And the third line is formed on the same layer as a transparent conductive layer such as a pixel electrode of the image display unit. The method of claim 1 Each of the first and second pads A first conductive layer extending from the first line, An insulating film formed on the first conductive layer, A plurality of contact holes exposing the first conductive layer, And a second conductive layer electrically connected to the first line through the plurality of contact holes. 6. The method of claim 5, The first line is formed on the same layer of the same metal layer as the gate line when forming the gate line of the image display unit, And the second line extends from the second conductive layer and is formed on the same layer as a transparent conductive layer such as a pixel electrode of the image display unit. Forming a link line having first and second lines superposed therebetween with an insulating film interposed therebetween; Forming first and second pads connected to both ends of the link line, respectively; Forming each of the first and second pads includes forming a first conductive layer extending from the first line, forming a second conductive layer extending from the second line, and forming the second conductive layer. Forming a protective film on the substrate; forming first and second contact holes to expose the first and second conductive layers; and forming the first and second contact holes through the first and second contact holes. Forming a third conductive layer to be electrically connected; Forming the link line Forming a protective film on the substrate to cover the second line; And And forming a third line extending from the third conductive layer to overlap the second line on the passivation layer. The method of claim 7, wherein Forming the link line Forming the first line on a substrate, Forming the insulating film on the substrate to cover the first line; And forming a second line on the insulating film to overlap the first line. delete delete 9. The method of claim 8, The first line is formed on the same layer of the same metal layer as the gate line when forming the gate line of the image display unit, The second line is formed on the same layer as the same metal layer as the data line when the data line of the image display unit is formed. And the third line is formed on the same layer as a transparent conductive layer such as a pixel electrode of the image display unit. The method of claim 7, Forming each of the first and second pads may be Forming a first conductive layer extending from the first line, Forming an insulating film on the first conductive layer, Forming a first contact hole to expose the first conductive layer, Forming a second conductive layer to be electrically connected to the first line through the first contact hole. 13. The method of claim 12, The first line is formed on the same layer of the same metal layer as the gate line when forming the gate line of the image display unit, And the second line extends from the second conductive layer and is formed on the same layer as a transparent conductive layer such as a pixel electrode of the image display unit.

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