KR102141553B1 - Array Substrate For Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to an array substrate for a liquid crystal display device, comprising: a substrate; A plurality of gate lines and a plurality of data lines formed on the substrate to cross each other to define a plurality of pixel regions; A thin film transistor formed in each of the plurality of pixel regions; A pixel electrode connected to the thin film transistor; A common electrode having at least one opening corresponding to the pixel electrode; A driving integrated circuit for generating gate signals and data signals respectively supplied to the plurality of gate lines and the plurality of data lines; A plurality of first link wirings that transmit the gate signals to the plurality of gate wirings and are formed of the same layer and material as the plurality of gate wirings; A plurality of second link wires positioned between the first link wires and formed on a layer different from the first link wires to transmit the data signal to the plurality of data wires; A plurality of third link wires, which are located between the first link wire and the second link wire, and comprise a first layer made of the same material on the same layer as the common electrode, and a second layer above the first layer. Include.

Description

Array Substrate For Liquid Crystal Display Device

The present invention relates to an array substrate for a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device in which one driving integrated circuit supplies both a gate signal for gate wiring and a data signal for data wiring.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal displays (LCDs), plasma display panels (PDPs), organic electric fields Various flat panel displays (FPDs) such as light emitting devices (OLED: organic light emitting diodes) are being used.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the electrodes face each other, injects liquid crystal between the two substrates, and then moves the liquid crystal molecules by an electric field generated by applying a voltage to the electrodes. , It is a device that expresses an image by the transmittance of light that varies accordingly.

Such a liquid crystal display device includes a liquid crystal panel comprising two bonded substrates and a liquid crystal layer therebetween, a backlight unit disposed under the liquid crystal panel to supply light, and a plurality of signals for driving the liquid crystal panel disposed outside the liquid crystal panel, and It consists of a drive unit that supplies power.

Typically, the driver is implemented on a printed circuit board (PCB), and is divided into a gate driver connected to the gate wiring of a liquid crystal panel and a data driver connected to the data wiring. It may be implemented as a printed circuit board (data PCB), and these printed circuit boards for gates and printed circuit boards for data are formed on one side of a liquid crystal panel and have a gate pad connected to the gate wiring, and the gate pad is formed. It is formed on the other side orthogonal to the side and can be mounted in the form of a tape carrier package (TCP) on each data pad connected to the data line.

On the other hand, for example, in the case of a small model, since the number of gate wiring and data wiring is relatively small, a driving integrated circuit (D-IC) for gate wiring and a driving integrated circuit for data wiring are not separately configured, A liquid crystal display device in which a circuit supplies both a gate signal for gate wiring and a data signal for data wiring has been developed.

Hereinafter, an array substrate for a liquid crystal display device of this type according to the prior art will be described with reference to the schematic circuit diagram of FIG. 1.

As shown in FIG. 1, a plurality of gate wirings GL1 to GLm receiving a scan signal in one direction and a plurality of pixel regions perpendicular to the plurality of gate wirings GL1 to GLm are vertically intersected on the substrate 20. And a plurality of data lines DL1 to DLn to which a data voltage is applied are arranged in a matrix form.

A plurality of thin film transistors Tr serving as switching are located at the intersection of the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn, and the thin film transistor Tr is a pixel configured to correspond to the pixel region. It is in contact with an electrode (not shown).

In addition, a liquid crystal capacitor (C _lc ) and a storage capacitor (C _st ) connected to the thin film transistor (Tr) are formed in each pixel region, and the liquid crystal capacitor (C _lc ) and the storage capacitor (C _st ) have a plurality of common wirings ( CL1 to CLm) respectively.

At one edge of the substrate 20, a driving integrated circuit 70 for supplying a gate signal and a data signal to the gate wiring and the data wiring, respectively, is formed, and connected to the driving integrated circuit 70 outside the driving integrated circuit 70. As a result, an input pad 72 receiving a plurality of driving signals and power from an external driving unit is formed.

Here, the driving integrated circuit 70 is connected to a plurality of gate wires (GL1 to GLm) through a plurality of gate link wires (GLL1 to GLLm), and a plurality of common wires through a plurality of common link wires (CLL1 to CLLm). It is connected to (CL1 to CLm), and is connected to a plurality of data wirings (DL1 to DLn) through a plurality of data link wirings (DLL1 to DLLn).

The driving integrated circuit 70 generates a gate signal and a data signal by using a plurality of driving signals supplied from an external driving unit, and the gate signal is generated by the thin film transistor Tr in each pixel region through the gate link wiring and the gate wiring. The thin film transistor (Tr) is switched by being applied to the gate electrode, and the data signal is supplied to the source electrode of the thin film transistor (Tr) in each pixel region through the data link wiring and the data wiring, and through the thin film transistor (Tr), a liquid crystal capacitor ( It is applied to C _lc ) and storage capacitor (C _st ).

Here, a plurality of gate link wires (GLL1 to GLLm) and a plurality of data link wires (DLL1 to DLLn) are separated into an even-numbered first link wire and an odd-numbered second link wire to be connected to the driving integrated circuit (70). do.

Further, each of the plurality of gate link wires GLL1 to GLLm and the plurality of data link wires DLL1 to DLLn may be formed with the same line width and line spacing.

Here, the even-numbered first link wiring and the odd-numbered second link wiring of the conventional liquid crystal display are designed to cross each other by being formed of different materials in different layers.

This will be described in more detail with reference to FIG. 2.

2 is a schematic cross-sectional view of a conventional array substrate for a liquid crystal display device.

As shown in FIG. 2, a plurality of gate wirings GL1 to GLm crossing each other to define a pixel region and a plurality of data wirings DL1 to DLn are formed on the upper surface of the array substrate, and gate wirings are formed in each pixel region. And a thin film transistor Tr connected to the data line.

The thin film transistor Tr includes a gate electrode 40 formed on the substrate 20, a gate insulating film 45 formed on the gate electrode 40, a semiconductor layer 50 formed on the gate insulating film 45, The semiconductor layer 50 includes a source electrode 55 and a drain electrode 60 formed to be spaced apart from each other, and a protective layer 65 is formed on the thin film transistor Tr.

In addition, a pixel electrode 62 connected to the thin film transistor Tr is formed between the gate insulating layer 45 and the protective layer 65 of each pixel area, and the substrate 20 and the gate insulating layer 45 of each pixel area A common electrode 56 spaced apart from the pixel electrode 62 is formed therebetween.

At this time, a plurality of gate wirings (GL1 to GLm) are connected to a plurality of gate link wirings (GLL1 to GLLm), a plurality of data wirings (DL1 to DLn) are connected to a plurality of data link wirings (DLL1 to DLLn), A plurality of common wirings CL1 to CLm are connected to a plurality of common link wirings CLL1 to CLLm. A plurality of gate link wires, a plurality of data link wires, and a plurality of common link wires are separated into a first link wire 42 that is an odd-numbered link wire and a second link wire 57 that is an even-numbered link wire to form a gate insulating film. The first link wiring is formed of the same material on the same layer as the gate electrode, and the second link wiring is formed of the same material on the same layer as the source electrode and the drain electrode.

However, since the first link wiring and the second link wiring are formed of different materials in different layers, the specific resistance value varies according to the material formed in each layer, and accordingly, a specific resistance difference occurs. There is a problem in that a dim phenomenon in which an image is expressed brightly or blurred in a display area of the substrate is generated in the display area of the substrate and the image quality of the display area of the substrate is deteriorated according to the delay time difference of the data voltage.

In addition, as the liquid crystal display device is configured with a high resolution, the number of link wirings increases in proportion to the number of pixels that increase, so that a wiring area is required and the size of the bezel increases.

An object of the present invention is to solve the above-described problem, and an object thereof is to provide an array substrate for a liquid crystal display device capable of preventing deterioration of image quality due to a difference in resistivity of each wiring and reducing the size of a bezel.

In order to achieve the above object, the array substrate for a liquid crystal display device of the present invention comprises: a substrate; A plurality of gate lines and a plurality of data lines formed on the substrate to cross each other to define a plurality of pixel regions; A thin film transistor formed in each of the plurality of pixel regions; A pixel electrode connected to the thin film transistor; A common electrode having at least one opening corresponding to the pixel electrode; A driving integrated circuit for generating gate signals and data signals respectively supplied to the plurality of gate lines and the plurality of data lines; A plurality of first link wirings that transmit the gate signals to the plurality of gate wirings and are formed of the same layer and material as the plurality of gate wirings; A plurality of second link wires positioned between the first link wires and formed on a layer different from the first link wires to transmit the data signal to the plurality of data wires; A plurality of third link wires, which are located between the first link wire and the second link wire, and comprise a first layer made of the same material on the same layer as the common electrode, and a second layer above the first layer. Include.

The first link wiring, the second link wiring, and the second layer of the third link wiring are formed on different layers.

The second link wiring is formed of the same layer and the same material as the plurality of data wirings.

The third link wiring is formed in a double layer on the same layer as the common electrode using a half tone mask.

The third link wiring is formed by a single mask process with the common electrode using a half tone mask.

The array substrate for a liquid crystal display device according to the present invention can prevent a delay difference in data voltage by reducing a specific resistance difference by applying a metal having the same specific resistance characteristics to the first link wiring, the second link wiring, and the third link wiring. .

In addition, according to the present invention, since the first link wiring, the second link wiring, and the third link wiring are located on different layers, the size of the bezel can be reduced by reducing the wiring area.

1 is a schematic circuit diagram of a conventional array substrate for a liquid crystal display device.
2 is a schematic cross-sectional view of a conventional array substrate for a liquid crystal display device.
3 is a schematic circuit diagram showing an array substrate for a liquid crystal display device according to an embodiment of the present invention.
FIG. 4 is a plan view illustrating an array substrate for a liquid crystal display device corresponding to part A of FIG. 3.
5 is a cross-sectional view of an array substrate for a liquid crystal display device taken along line V-V of FIG. 4.
6A to 6C are cross-sectional views sequentially illustrating a manufacturing process of an array substrate for a liquid crystal display according to the cut line V-V of FIG. 4.

Hereinafter, preferred embodiments of an array substrate for a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic circuit diagram showing an array substrate for a liquid crystal display device according to an embodiment of the present invention. For convenience of explanation, reference is made to FIG. 5 which is a cross-sectional view of an array substrate for a liquid crystal display device.

As shown in FIG. 3, a plurality of gate wirings GL1 to GLm to which a scan signal is applied in one direction on the substrate 120 of the array substrate for a liquid crystal display according to an embodiment of the present invention, and a plurality of A plurality of pixel regions are defined by vertically crossing the gate lines GL1 to GLm, and a plurality of data lines DL1 to DLn to which a data voltage is applied are arranged in a matrix form.

A plurality of thin film transistors Tr serving as switching are formed at the intersection of the plurality of gate lines GL1 to GLm and the plurality of data lines DL1 to DLn, and the thin film transistors Tr are configured corresponding to the pixel region. It is in contact with the pixel electrode (see 162 in FIG. 5).

In addition, a liquid crystal capacitor (C _lc ) and a storage capacitor (C _st ) connected to the thin film transistor (Tr) are formed in each pixel region, and the liquid crystal capacitor (C _lc ) and the storage capacitor (C _st ) have a plurality of common wirings ( CL1 to CLm) respectively.

At one edge of the substrate 120, a driving integrated circuit 170 for supplying a gate signal and a data signal to the gate wiring and the data wiring, respectively, is formed, and connected to the driving integrated circuit 170 outside the driving integrated circuit 170. As a result, an input pad 172 receiving a plurality of driving signals and power from an external driving unit is formed.

Here, the driving integrated circuit 170 is connected to a plurality of gate wirings (GL1 to GLm) through a plurality of gate link wirings (GLL1 to GLLm), and a plurality of common wirings through a plurality of common link wirings (CLL1 to CLLm). It is connected to (CL1 to CLm), and is connected to a plurality of data wirings (DL1 to DLn) through a plurality of data link wirings (DLL1 to DLLn). In this case, an area where the driving direct circuit 170 and the input pad 172 are located corresponds to a bezel area.

The driving integrated circuit 170 generates a gate signal and a data signal by using a plurality of driving signals supplied from an external driving unit, and the gate signal is generated by the thin film transistor Tr in each pixel region through the gate link wiring and the gate wiring. It is applied to the gate electrode 140 to switch the thin film transistor Tr, and the data signal is supplied to the source electrode 155 of the thin film transistor Tr in each pixel region through the data link wiring and the data wiring, and the thin film transistor Tr ) Through the liquid crystal capacitor (C _lc ) and the storage capacitor (C _st ).

In the embodiment of the present invention, a plurality of gate link wirings (GLL1 to GLLm), a plurality of data link wirings (DLL1 to DLLn), and a plurality of common link wirings (CLL1 to CLLm) are designed to be located on different layers. Since it can be arranged closely by reducing the line width of the bezel, the area of the bezel area can be reduced.

Here, for convenience of explanation, a plurality of gate link wires (GLL1 to GLLm) are connected to a first link wire (see 142 in FIG. 5), and a plurality of data link wires (DLL1 to DLLn) are connected to a second link wire (fig. 157), a plurality of common link wirings (CLL1 to CLLm) are referred to as a third link wiring (see 167 in FIG. 5).

An array substrate for a liquid crystal display device on which the first link wiring 142, the second link wiring 157, and the third link wiring 167 are positioned will be described in more detail with reference to FIGS. 4 and 5.

4 is a plan view illustrating an array substrate corresponding to portion A of FIG. 3, and FIG. 5 is a cross-sectional view of the array substrate taken along line V-V of FIG. 4.

4 and 5, a plurality of gate wirings GL1 to GLm and a plurality of data wirings DL1 to DLn crossing each other to define a pixel area are formed on the substrate 120, and each pixel In the region, a thin film transistor Tr connected to the gate line and the data line is formed. The thin film transistor Tr includes a gate electrode 140 formed on the substrate 120, a gate insulating layer 145 formed on the gate electrode 140, a semiconductor layer 150 formed on the gate insulating layer 145, A source electrode 155 and a drain electrode 160 are formed on the semiconductor layer 150 to be spaced apart from each other, and a protective layer 165 is formed on the thin film transistor Tr.

Here, the gate electrode 140 is a single layer of a conductive material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), molybdenum (Mo), and molybdenum alloy (MoTi), or It can be made of multiple layers, and metals such as aluminum (Al), copper (Cu), silver (Ag), and titanium (Ti) include calcium (Ca), Mg (magnesium), zinc (Zn), titanium (Ti), Molybdenum (Mo), nickel (Ni), zirconium (Zr), cadmium (Cd), gold (Au), silver (Ag), cobalt (Co), phosphorus (In), tantalum (Ta), hafnium (Hf), It may be made of a single layer or multiple layers of an alloy containing at least one of tungsten (W) and chromium (Cr).

In this case, the plurality of first link wirings 142 connecting the plurality of gate wirings GL1 to GLm and the driving integrated circuit 170 are formed of the same layer and the same material as the plurality of gate electrodes 140.

In addition, the gate insulating layer 145 may be made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx), or may be made of aluminum (Al) oxide or hafnium (Hf) oxide.

The semiconductor layer 150 may be made of indium tin oxide (ITO) or indium zinc oxide (IZO), and the source electrode 155 and the drain electrode 160 are relatively low. It may be made of copper (Cu) or a copper alloy having specific resistance.

At this time, the plurality of second link wirings 157 connecting the plurality of data wirings DL1 to DLn and the driving integrated circuit 170 are made of the same layer and the same material as the source electrode 155 and the drain electrode 160. .

In addition, the protective layer 165 is silicon oxide (SiO ₂ ) coated with an organic insulating material such as benzocyclobutene (BCB) or photo-acryl, or through a chemical vapor deposition (CVD) method. ) Or by depositing an inorganic insulating material such as silicon nitride (SiNx).

In addition, a pixel electrode 162 connected to the thin film transistor Tr is formed between the gate insulating layer 145 and the protective layer 165 of each pixel region, and the pixel electrode 162 is under the drain electrode 160. And is electrically connected to the drain electrode 160.

In addition, a common electrode 156 is formed on the entire surface of the substrate 120 on the protective layer 165, and a plurality of openings 154 spaced a predetermined distance from the adjacent common electrode 156 corresponding to the pixel electrode 162 Have. At this time, the common electrode 156 completely covers the upper portion of the thin film transistor.

The pixel electrode 162 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the common electrode 156 is indium-tin-oxide. A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) may be formed over the entire surface of the substrate 120.

The common electrode 156 is connected to a plurality of common wirings CL1 to CLm to receive a common voltage. Here, the plurality of third link wirings 167 are formed of the same layer as the common electrode 156, a first layer made of the same material, and a second layer above the first layer by using a halftone mask 173. , A common voltage is supplied to the common electrode 156.

The pixel electrodes 162 and the common electrodes 156 are alternately disposed in the pixel region, each receiving a data signal and a common voltage to generate a horizontal electric field, and liquid crystal molecules of the liquid crystal layer (not shown) are generated by a horizontal electric field. It is rearranged and displays the image with the change in transmittance.

In particular, the common electrode 156 and the third link wiring 167 formed using the halftone mask 173 will be described in detail with reference to FIGS. 6A to 6C.

6A to 6C are cross-sectional views sequentially illustrating a manufacturing process of the third link wiring 167 using the half-tone mask 173 in the array substrate for a liquid crystal display according to the cut line V-V of FIG. 4.

As shown in FIG. 6A, a first layer 151 made of the same material as a common electrode is deposited on the substrate 120 on which the protective layer 165 is formed on the entire area of the substrate 120, and the first layer (151) A second layer 152 made of a metal such as aluminum (Al) or copper (Cu) is deposited on the top to form a double metal film.

Thereafter, a photosensitive layer 174 is formed on the second layer 152 by using the half tone mask 173. Here, the halftone mask 173 is provided with a region through which the irradiated light is transmitted, a region through which only part of the light is transmitted, and a region in which light is blocked, and only the light passing through the halftone mask 173 is provided on the photosensitive layer 174. It is irradiated to form a photosensitive layer pattern. Accordingly, the photosensitive layer 174 is formed in a halftone pattern on the region where the common electrode 156 is formed.

Thereafter, as shown in FIG. 6B, etching is performed using the halftone pattern photosensitive layer 174 as a mask, and as shown in FIG. 6C, a common electrode made of the first layer 151 of a transparent conductive material. A third link wiring 167 composed of a double layer of 156 and a first layer 151 made of a transparent conductive material and a second layer 152 made of a metal is formed.

The first link wiring 142, the second link wiring 157, and the third link wiring 167 described above are in different layers with the gate insulating layer 145 and the protective layer 160 interposed therebetween. It is formed such that the second link wiring 157 and the third link wiring 167 are positioned between 142. In such a configuration, even if the first to third link wirings 142, 157, and 167 are designed to overlap each other in a plane, there is no fear of a short-circuit failure, and thus can be closely designed without being limited to the minimum line width. Therefore, it is possible to reduce the bezel area.

In addition, since the first to third link wirings 142, 157, and 167 are formed of metals having the same resistivity characteristics, it is possible to prevent delay deviation of the data voltage.

The embodiment of the present invention described above is an example of the present invention, and can be freely modified within the scope of the spirit of the present invention. Accordingly, the present invention includes modifications of the present invention within the scope of the appended claims and equivalents thereto.

110: liquid crystal display device 120: first substrate
130: second substrate 140: gate electrode
142: first link wiring 145: gate insulating film
150: semiconductor layer 151: first layer
152: second layer 154: opening
155: source electrode 156: common electrode
157: second link wiring 160: drain electrode
162: pixel electrode 165: protective layer
167: third link wiring 170: driving integrated circuit
172: input pad 173: halftone mask
174: photosensitive layer

Claims (11)

A substrate including a first region and a second region outside the first region;
A plurality of gate wires and a plurality of data wires formed to cross each other over the first region of the substrate to define a plurality of pixel regions;
A thin film transistor formed in each of the plurality of pixel regions;
A pixel electrode connected to the thin film transistor;
A common electrode having at least one opening corresponding to the pixel electrode;
A driving integrated circuit disposed in the second region of the substrate and generating gate signals and data signals respectively supplied to the plurality of gate lines and the plurality of data lines;
A plurality of first link wirings disposed between the gate wiring and the driving integrated circuit to electrically connect the gate wiring and the driving integrated circuit and transferring the gate signals to the plurality of gate wirings;
A plurality of devices disposed between the data line and the driving integrated circuit to electrically connect the data line and the driving integrated circuit, transferring the data signal to the plurality of data lines, and positioned between the first link lines A second link wiring of;
It is located between the first link wiring and the second link wiring, and is composed of a plurality of third link wirings comprising a first layer and a second layer above the first layer,
The first link wiring, the second link wiring, and the third link wiring are arranged to be spaced apart from each other on different layers of the second area, and the first link wiring is made of the same material on the same layer as the gate wiring, and the The second link wiring is formed of the same material on the same layer as the data wiring, and the third link wiring is formed on the same layer as the common electrode.
delete delete The method of claim 1,
An array substrate for a liquid crystal display device, wherein the third link wiring is formed using a half tone mask.
The method of claim 1.
The third link wiring is formed by a single mask process with the common electrode using a half tone mask. The method of claim 1, wherein the third link wiring,
A first layer made of the same material as the common electrode; And
An array substrate for a liquid crystal display device, comprising a second layer disposed on the first layer and made of metal.
The array substrate of claim 1, wherein the pixel electrode is connected to the thin film transistor by contacting a lower surface of the drain electrode of the thin film transistor.
The array substrate of claim 1, wherein the common electrode covers the entire thin film transistor.

The liquid crystal display device according to claim 1, further comprising an input pad disposed outside the driving integrated circuit in the second area to receive a plurality of driving signals and power to the outside and applied to the driving integrated circuit. For array substrate.
The array substrate of claim 1, wherein the second link wiring and the third link wiring are disposed between the first link wirings.
The array substrate of claim 1, wherein at least two of the first link wiring, the second link wiring, and the third link wiring have the same resistivity.

Images