KR101278396B1

KR101278396B1 - Substrate fixing jigs for packaging and fabrication methods for semiconductor chip packages

Info

Publication number: KR101278396B1
Application number: KR1020110036271A
Authority: KR
Inventors: 충-딩 왕; 윌리엄 쳉; 보-이 리; 첸-후아 유; 치엔-시운 리
Original assignee: 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
Priority date: 2010-04-20
Filing date: 2011-04-19
Publication date: 2013-06-24
Also published as: TWI443771B; TW201138010A; KR20110117018A

Abstract

A substrate holding jig for packaging is disclosed. The substrate holding jig for packaging includes a base plate, a laminated substrate having a plurality of semiconductor chip attachment regions for bonding at least one semiconductor chip therein, and a top fixing cover for flattening the laminated substrate. And mechanically and magnetically fixing the laminated substrate between and the top fixing cover. The upper fixing cover has a plurality of openings corresponding to the plurality of semiconductor chip attachment regions. The present invention also discloses a manufacturing method for a semiconductor chip package.

Description

Substrate fixing jig for packaging and manufacturing method of semiconductor chip package {SUBSTRATE FIXING JIGS FOR PACKAGING AND FABRICATION METHODS FOR SEMICONDUCTOR CHIP PACKAGES}

The present invention relates to a substrate fixing jig for packaging, and more particularly, to a substrate fixing jig for flip chip chip scale packaging (fcCSP) and a manufacturing method of fcCSP.

fcCSP technology is widely used in high performance, high speed, and high density, compact size packages. For conventional fcCSP technology, the semiconductor chip is flipped downward and the metal conductor on the semiconductor chip is then bonded onto the underlying laminated substrate.

As the dimensions of the semiconductor device decrease, the bump pitch also decreases. If the semiconductor chip is flipped and bonded onto the laminated substrate by the conventional fcCSP method, a bridge may occur between neighboring bumps when the laminated substrate is bent by external force, or a very brittle cold joint ) May be formed. The laminated substrate is not fixed by the fixer in the step of placing the semiconductor chip on the laminated substrate, and the edge portion of the laminated substrate is fixed by the fixer after the reflow process followed by the flux cleaning process. However, in the step of placing the semiconductor chip on the laminated substrate, the laminated substrate is easily broken, causing the formation of bump bridges or cold joints.

Therefore, there is a need to develop a substrate holding jig for packaging and a manufacturing method for a semiconductor chip package, which can prevent the formation of bump bridges or cold joints while removing flux forming residues from the flux cleaning process.

One exemplary embodiment of a substrate holding jig for packaging includes a base plate, a laminated substrate having a plurality of semiconductor chip attachment regions for bonding at least one semiconductor chip therein, and a top fixing cover for planarizing the laminated substrate. The top anchoring cover includes mechanically and magnetically anchoring the laminated substrate between the base plate and the top anchoring cover. The upper fixing cover has a plurality of openings corresponding to the plurality of semiconductor chip attachment regions. The present invention also discloses a manufacturing method for a semiconductor chip package.

One exemplary embodiment of a method of manufacturing a semiconductor clip package includes providing a substrate holding jig for packaging, wherein the substrate holding jig for packaging includes a base plate, a plurality of bonding chips for bonding at least one semiconductor chip therein. A laminated substrate having a semiconductor chip attachment region, and a top fixed cover for planarizing the laminated substrate, wherein the top fixed cover mechanically and magnetically holds the laminated substrate between the base plate and the top fixed cover; The top fixing cover has a plurality of openings corresponding to the plurality of semiconductor chip attachment regions. The semiconductor chip is located on one of the plurality of semiconductor chip attachment regions. A reflow process is performed on a substrate holding jig for packaging with a semiconductor chip. The substrate holding jig for packaging with the semiconductor chip is cleaned by a solution containing deionized water (DIW) and a solvent to remove residual flux.

According to the present invention, since the laminated substrate is flattened by the top fixing cover, the problem of bump bridge or cold joint formation induced by substrate bending can be prevented during the semiconductor chip flipping step. In addition, during flux removal, the formation of residual flux and residual solution can be prevented. In addition, it is possible to reduce the occurrence of lamination delamination of the ultra low dielectric caused by the external force caused by stopping the process.

The invention can be more fully understood by reading the detailed description and the embodiments which follow with reference to the accompanying drawings.
1A shows a perspective view of one exemplary embodiment of a substrate holding jig for packaging according to the present invention.
FIG. 1B shows a cross-sectional view of the substrate holding jig for packaging shown in FIG. 1A.
2A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging according to the present invention.
FIG. 2B shows a cross-sectional view of the substrate holding jig for packaging shown in FIG. 2A.
3A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging according to the present invention.
FIG. 3B shows an exploded view of the substrate holding jig for packaging shown in FIG. 3A.
4A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging according to the present invention.
FIG. 4B shows an enlarged view of the peripheral region 4B of the packaging substrate holding jig shown in FIG. 4A.
4C is a plan view of the substrate holding jig 400 for packaging shown in FIG. 4A.
4D shows a cross-sectional view of the substrate holding jig 400 for packaging shown in FIG. 4C.
5A shows a top view of another exemplary embodiment of a substrate holding jig 500 for packaging according to the present invention.
FIG. 5B shows a cross-sectional view of the substrate holding jig 500 for packaging shown in FIG. 5A.
FIG. 5C shows an enlarged view of the peripheral region 5C of the packaging substrate fixing jig shown in FIG. 5A.
6A shows a top view of another exemplary embodiment of a substrate holding jig 600 for packaging according to the present invention.
FIG. 6B shows a cross-sectional view of the substrate holding jig 600 for packaging shown in FIG. 6A.
FIG. 6C shows an enlarged view of the peripheral region 6C of the packaging substrate holding jig shown in FIG. 6A.

The following description entails the manufacture and purpose of the present invention. It is to be understood that this description is provided for the purpose of illustrating the manufacture and use of the invention and is not to be taken in a limiting sense. Within the drawings or the description, the same or similar elements are denoted or indicated by the same or similar reference numerals. In addition, the shape or thickness of the elements shown in the drawings may be enlarged for simplicity or convenience. In addition, elements not shown or described in the figures or descriptions are generic elements well known in the art.

1A shows a perspective view of one exemplary embodiment of a substrate holding jig for packaging according to the present invention, and FIG. 1B shows a cross-sectional view of the packaging substrate holding jig shown in FIG. 1A. 1A and 1B, the packaging substrate fixing jig 100 has a base plate 150 and a plurality of semiconductor chip attachment regions 135 for bonding at least one semiconductor chip 160 therein. And a top fixing cover 110 having a plurality of openings 125 corresponding to the laminated substrate 130 and the plurality of semiconductor chip attachment regions 135. It can be appreciated that the top fixing cover 110 is designed to have a thickness T less than or equal to the thickness of the semiconductor chip 160 in order to easily remove the solution including the solvent and DIW during the removal of the flux. The plurality of pin holes 115 are formed in the peripheral area 126 of the upper fixing cover 110. A plurality of pinholes 115 are employed to couple with the guide pins of the base plate 150, thereby fixing the top fixing cover 110, the laminated substrate 130, and the base plate 150 to the pinholes. The plurality of openings 125 of the top stationary cover 110 includes a slender belt 122 configured as a grid, thereby separating each chip in the chip array.

FIG. 2A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging according to the present invention, and FIG. 2B shows a cross-sectional view of the packaging substrate holding jig shown in FIG. 2A. 2A and 2B, the substrate holding jig 200 for packaging is laminated with a base plate 250 and a plurality of semiconductor chip attachment regions 235 for bonding at least one semiconductor chip 260. And a top fixing cover 210 having a plurality of openings 225 corresponding to the substrate 230 and the plurality of semiconductor chip attachment regions 235. In this embodiment, each chip attach region 23 5 can be used to attach a chip array. The plurality of pin holes 215 are formed in the peripheral area 226 of the upper fixing cover 210. A plurality of pinholes 215 are employed to engage with the guide pins of the base plate 250, thereby fixing the top fixing cover 210, the laminated substrate 230, and the base plate 250 to the pinholes. The belt region 228 is between adjacent openings 225 in the top stationary cover 210, where the belt region 228 is greater than the width of the scribe slot in the laminated substrate 230 and has two widths. It has a width D smaller than the width of the gap D 'between adjacent sets of chip arrays. In addition, it is to be understood that the top fixing cover 210 is designed to have a thickness T less than or equal to the thickness of the semiconductor chip 260 to easily and easily remove the solution including the solvent and DIW when the flux is removed. have.

3A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging according to the present invention, and FIG. 3B shows an exploded view of the packaging substrate holding jig shown in FIG. 3A. Referring to FIGS. 3A and 3B, the top plate cover 310 includes a first fastening component 310a and a second fastening component 310b. The first fastening component 310a is a top cover ring, which is attached to the edge of the second fastening component 310b, wherein the fringe of the top cover ring 310a is the top plate, the laminated substrate and the top fastening cover. A plurality of clamp rings 318 are fixed to the cover ring 310a.

The second fastening component 310b is similar to the top fastening cover 110 shown in FIG. 1A and has a plurality of openings 325 corresponding to the chip attachment region. The plurality of pin holes 315 are formed in the peripheral area of the upper fixing cover 310. A plurality of pin holes 315 are employed to secure the top fixation cover 310, the laminated substrate and the base plate. The plurality of openings 325 of the second fastening component 310b include a slender belt 322 configured as a grid, thereby separating each chip in the chip array.

4A shows a perspective view of another exemplary embodiment of a substrate holding jig for packaging a semiconductor chip package according to the present invention, and FIG. 4B shows an enlarged view of the peripheral region 4B of the substrate holding jig for packaging shown in FIG. 4A. Indicates. Referring to FIGS. 4A and 4B, the substrate holding jig 400 for packaging includes a laminated substrate 430 having a base plate 450 and a plurality of semiconductor chip attachment regions for bonding at least one semiconductor chip. And a top fixing cover 410 having a plurality of openings 425 corresponding to the plurality of semiconductor chip attachment regions. In one embodiment, a plurality of magnets 458 is installed on the base plate 450 to planarize the laminated substrate 430 such that the laminated substrate 430 is fixed to the base plate 450 and the top fixed cover. 410 is fixed between. The upper fixing cover 410 has a plurality of pinholes 415 which are adapted to engage with the guide pins 416 of the base plate 450, whereby the upper fixing cover 410 and the laminated substrate 430 in the pinholes. ) And the base plate 450. In another embodiment, the top stationary cover 410 has a plurality of vacuum holes 455 to adsorb the laminated substrate 430.

In addition, a plurality of pin holes 415 are formed in the peripheral area 426 of the top fixing cover 410. The peripheral area 426 of the upper fixing cover 410 has a plurality of grooves 428 that connect the plurality of openings 425 to the outside of the packaging substrate fixing jig 400.

FIG. 4C shows a plan view of the packaging substrate holding jig 400 shown in FIG. 4A, and FIG. 4D shows a cross-sectional view of the packaging substrate fixing jig 400 shown in FIG. 4C. Referring to FIG. 4D, the laminated substrate 430 is flattened and fixed on the base plate 450 by the top fixing cover 410, thereby preventing the laminated substrate 430 from bending. When the flux is removed, the top fixing cover 410 is larger than the thickness of the semiconductor chip in order to easily remove the solution containing the DIW and the solvent, with respect to the outside of the packaging substrate holding jig 400 through the groove 428. It can be appreciated that it is designed to be large and have a thickness T higher than the height T1 of the groove 428.

5A shows a top view of another exemplary embodiment of a substrate holding jig 500 for packaging according to the present invention, and FIG. 5B shows a cross-sectional view of the packaging substrate holding jig 500 shown in FIG. 5A, and FIG. An enlarged view of the peripheral region 5C of the packaging substrate fixing jig shown in 5a is shown. Referring to FIGS. 5A and 5B, the substrate holding jig 500 for packaging is laminated with a base plate 550 and a plurality of semiconductor chip attachment regions 535 for bonding at least one semiconductor chip 560. Top fixing cover 510 including a slender belt 522 configured as a grid to separate the substrate 530 and each chip in the chip array. In one embodiment, the peripheral area of the top stationary cover 510 has a plurality of grooves 528. When the flux is removed, a plurality of openings 525 are provided for the substrate holding jig 500 for packaging to easily remove the solution including the DIW and the solvent from the substrate holding jig 500 for the packaging through the groove 528. It can be understood that it is connected to the outside of the. The peripheral region of the top fixed cover 510 is shaped in a step shape with respect to the laminated substrate 530 and has a protrusion 526, where the height of the bottom of the groove 528 is the height of the laminated substrate 530. Substantially equal to height.

6A shows a top view of another exemplary embodiment of a substrate holding jig 600 for packaging according to the present invention, and FIG. 6B shows a cross-sectional view of the packaging substrate holding jig 600 shown in FIG. 6A, and FIG. An enlarged view of the peripheral region 6C of the packaging substrate fixing jig shown in 6a is shown. 6A to 6C, the packaging substrate fixing jig 600 is substantially similar to that of the packaging substrate fixing jig 500 shown in FIGS. 5A to 5C and will not be described again for the sake of simplicity. The difference is that the peripheral area of the top fixing cover 610 is shaped in a step shape and lies on the edge of the laminated substrate 630 and has a protrusion 626, where the bottom of the groove 628 is for packaging The outside of the substrate holding jig 600 should be substantially higher than the top surface of the laminated substrate 630 to help remove the cleaning solution used in the flux.

According to the above-described embodiment, flip chip chip scale packaging (fcCSP) may be manufactured using the substrate fixing jig 100 to 600 for packaging. For example, a substrate holding jig for packaging is provided, and the chip is flipped to position on one of the plurality of semiconductor chip attachment regions. Next, a reflow process is performed on the substrate holding jig for packaging with the semiconductor chip. The substrate holding jig for packaging with a semiconductor chip is cleaned by a solution containing a DIW and a solvent to remove residual flux, wherein the semiconductor chip is flipped and positioned, a reflow process is performed, and Removing the flux is performed by an inline process apparatus. Since the laminated substrate is planarized by the top fixing cover, the problem of bump bridge or cold joint formation induced by substrate bending can be prevented during the semiconductor chip flipping step. In addition, during flux removal, the solution removing the flux can be completely removed to the outside of the substrate holding jig for packaging by forming a groove in the peripheral area of the top fixing cover, thereby preventing the formation of residual flux and residual solution. You can prevent it. In addition, the substrate holding jig for packaging according to the above-described embodiments can fix the base plate, the laminated substrate and the top fixing cover and thus can be applied to the inline fcCSP process, thereby causing the external force caused by stopping the process. This can reduce the occurrence of extreme low-k (ELK) lamination de-lamination.

While the invention has been described, for example, in the preferred embodiments, it is to be understood that the invention is not limited to these embodiments. On the contrary, it is intended to include various modifications and similar arrangements (as will be apparent to those skilled in the art). Accordingly, the scope of the appended claims should be understood in the broadest sense so as to encompass all such modifications and similar arrangements.

100: substrate fixing jig for packaging
110: top fixed cover
130: laminated substrate
135: semiconductor chip attachment region
150: base plate

Claims

In the substrate fixing jig for packaging,
A base plate,
A lysed substrate having a plurality of semiconductor chip attachment regions for bonding at least one semiconductor chip therein,
The top anchoring cover to planarize the laminated substrate and to mechanically and magnetically fix the laminated substrate between the base plate and the top anchoring cover
Including;
And said upper fixing cover has a plurality of openings corresponding to said plurality of semiconductor chip attachment regions.

The jig for packaging of claim 1, wherein the top fixing cover has a thickness less than or equal to the thickness of the semiconductor chip.

3. The belt area of claim 2 wherein a belt region between adjacent openings in the top fixing cover is greater than the width of the scribe slots in the laminated substrate and less than the width of the gap between the two chip array sets. The substrate holding jig for packaging having.

According to claim 1, further comprising a top cover ring attached to the edge portion of the top fixing cover,
The fringe of the top cover ring has a plurality of clamp rings for securing the base plate, the laminated substrate and the top fixing cover to the top cover ring.

The packaging substrate holding jig according to claim 1, wherein the peripheral area of the upper fixing cover has a plurality of grooves, each groove connecting the plurality of openings to the outside of the packaging substrate fixing jig.

According to claim 1, wherein the upper fixing cover has a thickness less than or equal to the thickness of the semiconductor chip, the peripheral region of the upper fixing cover is shaped in a step shape, the plurality of the outer of the packaging substrate fixing jig for packaging Substrate fixing jig for packaging having a plurality of grooves for connecting the opening of the.

In the method of manufacturing a semiconductor chip package,
Providing a substrate holding jig for packaging;
Flipping and positioning the semiconductor chip on one of the plurality of semiconductor chip attachment regions;
Performing a reflow process on the packaging substrate holding jig having the semiconductor chip;
Cleaning the substrate holding jig for packaging with the semiconductor chip by a solution containing deionized water (DIW) and a solvent to remove residual flux
Including;
The packaging substrate fixing jig for
A base plate,
A laminated substrate having said plurality of semiconductor chip attachment regions for bonding at least one semiconductor chip therein,
And a top fixing cover for planarizing the laminated substrate and for mechanically and magnetically fixing the laminated substrate between the base plate and the top fixing cover, wherein the top fixing cover comprises the plurality of semiconductor chip attachment regions. A plurality of openings corresponding to
Method of producing a semiconductor chip package.

8. The method of claim 7, wherein flipping and positioning the semiconductor chip, performing the reflow process, and removing the residual flux are performed by in-line process equipment. The manufacturing method of a semiconductor chip package.

The method of claim 7, wherein the top fixing cover has a thickness less than or equal to the thickness of the semiconductor chip.

8. The belt area of claim 7 wherein a belt region between adjacent openings in the top fixing cover is greater than the width of the scribe slots in the laminated substrate and less than the width of the gap between the two chip array sets. Method of producing a semiconductor chip package.

The method of claim 7, further comprising a top cover ring attached to the edge portion of the top fixing cover,
Wherein the fringe of the top cover ring has a plurality of clamp rings for securing the base plate, the laminated substrate and the top fixing cover to the top cover ring.

The method of claim 7, wherein the peripheral area of the upper fixing cover has a plurality of grooves, and each groove connects the plurality of openings to the outside of the packaging substrate fixing jig.

The method of claim 7, wherein the upper fixing cover has a thickness less than or equal to the thickness of the semiconductor chip, the peripheral region of the upper fixing cover is shaped in a step shape, the plurality of outer surfaces of the packaging substrate fixing jig The manufacturing method of the semiconductor chip package which has a some groove which connects the opening part of.