KR101234589B1 - Copper plated layer for forming pattern of printed circuit board and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a copper plating layer that can be used for a copper foil for a printed circuit board or a copper plating layer coated on the surface of the copper foil, in the etching process for forming a pattern is possible to etch with a high anisotropy in the thickness direction compared to the prior art to form a fine pattern An object of the present invention is to provide an advantageous copper plating layer and a method of manufacturing the same.
Copper plating layer according to the invention is characterized in that the absolute value of the residual stress is 8 MPa or less.

Description

Copper plating layer for forming PCB pattern and manufacturing method thereof {COPPER PLATED LAYER FOR FORMING PATTERN OF PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a copper plating layer used for pattern formation of a printed circuit board (PCB) and a manufacturing method thereof, and more particularly, copper plating layer that can be used for copper foil for a printed circuit board or a copper plating layer coated on the surface of the copper foil. The present invention relates to a copper plating layer capable of etching with a high anisotropy in the thickness direction in the etching process for pattern formation and advantageous in forming a fine pattern, and a method of manufacturing the same.

Printed Circuit Board (hereinafter referred to as 'PCB') is a high growth rate among the demand industries and is mainly applied to mobile electronics and information devices that have high product competitiveness in Korea, HDI (High Density Interconnects), MLB (Multi-Layer Board) and FPC ( In the manufacture of high value-added PCBs such as flexible printed circuit boards, one of the core technologies is a technique for implementing fine patterns and micro vias.

Conventional exposure techniques that use films with printed circuit patterns as exposure masks have circuit line widths of 30 μm or less due to printer resolution limitations, film shrinkage control limitations, and copper (Cu) layer etching mechanism limitations. There are many difficulties to implement.

As a technique to overcome this problem, a semi-additive method or a maskless laser, which forms a necessary conductor circuit through an electroless plating method, an electroplating method and an etching on an insulating plate, is directly applied to a dry film. Exposure technology is being developed and partly employed in the PCB process to produce semiconductor substrates.

Meanwhile, the subtractive method, which is widely used for circuit pattern formation in PCB manufacturing, forms a circuit pattern by removing copper or metal of unnecessary parts except for circuit parts of conductors required from a dynamic laminated plate or a metal laminated plate, which is a raw material. In the etching process for removing the copper or metal, reducing side etching as much as possible is the key to realizing fine patterns.

Since etching increases the closer the surface is to the etching, the cross section in the thickness direction after the conventional etching has a shape as shown in Fig. 1A. Therefore, the circuit line width A must be large. In order to reduce the influence of the etching process, the thickness of the copper plated layer or copper foil, which is the target of etching, may be reduced, but the thickness of the copper foil may not be infinitely thin. Impedances to implementation

Accordingly, a technique capable of minimizing the circuit line width in the copper plating layer or the copper foil of a given thickness is required. To this end, as shown in FIG. 1B, the etching anisotropy is reduced, so that the side etching can be reduced and the circuit line width B can be reduced. Etching process technology is required.

The present invention is to provide a copper plating layer for PCB pattern formation that can greatly reduce the side etching when etching through the control of the surface state and physical properties of the copper plating layer for PCB pattern formation compared to the conventional copper foil or copper plating layer. Let's solve the problem.

In addition, another object of the present invention is to provide a method of manufacturing a copper plating layer for forming a PCB pattern that can be performed at a low cost and greatly reduce side etching by minimizing changes in the circuit forming process by the current etching method.

The inventors of the present invention found that the smaller the residual stress or grain size of the copper plating layer formed for copper foil for pattern formation of a printed circuit board or for copper plating plated on the surface of the copper foil, the smaller the side etching during etching of the copper plating layer. The present invention has been completed after confirming that a circuit can be implemented.

As a means for solving the above problems, the present invention provides a copper plating layer for forming a printed circuit board pattern, characterized in that the absolute value of the residual stress is 8 MPa or less (that is, -8 MPa to 8 MPa).

In this invention, a "copper plating layer" includes what is itself used for copper foil, and what is plated on the surface of copper foil.

When the absolute value of the residual stress exceeds 8 MPa, the isotropic etching property of the copper plating layer is enhanced during etching, which is preferably 8 MPa or less, and the absolute value of the residual stress is 5 MPa. It is more preferable to keep it below.

In the copper plating layer according to the present invention, the average grain size of the copper plating layer is preferably maintained at 1 µm or less to keep the residual stress low, and more preferably at 0.7 µm or less.

In addition, the present invention as a means for solving the other problems, a method for producing a copper plating layer for pattern formation of a printed circuit board by an electroplating method using an electrolytic plating solution, the electrolytic plating solution has a molecular weight of 1 ~ 50ppm concentration Provided is a method of manufacturing a copper plating layer for forming a printed circuit board pattern comprising 5,000 to 20,000 gelatin-based materials.

When the gelatinous material is added to less than 1 ppm in the electrolytic plating solution, it is difficult to control the internal defects such as the surface shape of the plating layer or the micro-pinhole, and when it exceeds 50 ppm, the residual stress of the copper plating layer formed is exceeded. Since it is difficult to keep the absolute value below 8 MPa, it is preferable to add in 1-50 ppm. In addition, since the residual stress and grain size of the copper plating layer formed even when the molecular weight of the gelatinous material is less than 5,000 or exceeds 20,000, it is preferable to maintain the range of 5,000 to 20,000.

In addition, the electrolytic plating solution is characterized in that it contains CuSO ₄ 5H ₂ O (Cu based): 20 ~ 80g / l, H ₂ SO ₄ : 120 ~ 140g / l, Cl: 10 ~ 30 ppm.

This is because CuSO ₄ 5H ₂ O is less than 20 g / ℓ (based on Cu), there is a problem such as a decrease in the plating rate, if it exceeds 80 g / ℓ because it is difficult to manage the solution, such as precipitation due to temperature changes 20 ~ 80 g / l is preferred, and 120 to 140 g / l is preferred since H ₂ SO ₄ causes uneven growth of the plating layer when it is less than 120 g / l and more than 140 g / l, and Cl is 10 This is because 10 to 30 mg / l is preferable because less than mg / l and more than 30 mg / l inhibit the uniformity of peaks and valleys on the surface of the coating layer.

According to the copper plating layer for a fine pattern according to the present invention and a method for manufacturing the same, it is possible to form a circuit pattern having a high anisotropy in the thickness direction at the time of etching and a large aspect ratio, thereby forming a finer pattern as compared with the prior art.

1A and 1B are schematic views showing differences in circuit line widths according to differences in side etching amounts.
Figure 2 shows the change in the surface shape of the copper (Cu) plating layer according to the type and concentration change of the organic additive.
3 is a circuit pattern photograph formed using a copper plating layer according to an embodiment of the present invention.
Figure 4 shows the calculation process of the etching index measured in the embodiment of the present invention.
FIG. 5 shows the photograph of the cross-sectional shape of the microcircuit formed by the subtractive method using the copper plating layer prepared in the embodiment of the present invention, and the etching index obtained for the plating layer for each additive type and concentration.
6 is a graph showing the correlation between the residual stress and the circuit etching value of the copper plating layer prepared in the embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to exemplary embodiments of the present invention. However, the technical idea of the present invention is not limited or limited thereto, and may be variously modified and implemented by those skilled in the art.

PCB Manufacture of Copper Foil

In an embodiment of the present invention, a copper foil for use as a pattern forming copper foil for use in a substractive method for implementing a circuit by attaching a copper foil to a disc insulating layer and then removing unnecessary portions by etching. The plated layer was prepared by electroplating.

The plating solution for electroplating synthesizes a high concentration of copper plating solution capable of high-speed plating, and then purifies the plating solution sufficiently by using an active carbon filter and a cartridge filter having a size of 0.5 μm to remove impurities in the plating solution. Various kinds of copper plating solutions were prepared by mixing organic additives.

Specifically, the plating solution synthesizes a reagent grade (EP grade) sulfuric acid (H ₂ SO ₄ , 120 ~ 140g / L) and copper sulfate (CuSO ₄ 5H ₂ O, 80g / L based on Cu), as shown in Table 1, 20 ppm of HCl was added for uniform growth of the copper plating layer formed by electroplating, and six kinds of organic additives were added to 50 ppm or less.

ingredient Concentration (g / ℓ) CuSO ₄ 5H ₂ O 80 (Cu standard) H ₂ SO ₄ 120 to 140 Cl 20 ppm Additives A, B, C, D, E, F 0 to 50 ppm

In electroplating, various factors can influence the nucleation and growth control of the metal to be plated. One of the representative factors is additives added to the plating solution.

When the additive is added, a large change may occur in the surface shape, surface roughness (surface roughness) and physical properties of the plating layer formed by electroplating. The present inventors add various organic additives to the electrolytic solution in copper (Cu) electroplating. Changes in factors such as surface shape, residual stress, and grain size of the copper (Cu) plating layer, and the resulting etching characteristics of the copper plating layer were investigated.

In the copper plating solution, as shown in Table 1, a total of six organic additives (A, B, C, D, E, and F) for controlling the physical properties of the copper plating layer such as the residual stress and the size of crystal grains, respectively, were added to the electrolyte solution. Was added, the specific composition of the additive is shown in Table 2 below. Dual additives A to D are gelatin-based compositions, A is the product name 'gelatin' of Miyagi, Japan, and additives B to D are the product names' Colagel-A ',' Gelitasol-LDA 'and' Gelitasol-PA, respectively. 'to be.

Additive type Molecular Weight Classification A (gelatin series) 15,000-25,000 The B (gelatin series) 18,000 The C (gelatin series) 3,300 medium D (gelatin series) 6,600 medium Polyethylene glycol (E) 200 that F (N, N-Dimethyl-dithiocarbamyl propyl sulfonic acid sodium salt) 265 that

Electroplating was performed using the copper plating solution prepared as described above with a current density of 10-40 A / dm ² and a reaction temperature of 50 ° C.

In this case, the anode where the copper plating layer is electrodeposited is used after polishing the titanium plate uniformly using silicon carbide paper (CC 3000) and degreasing it for 20 minutes at 50 ° C 1M NaOH to completely remove organic substances and impurities on the surface. As a positive electrode, a dimensionally stable anode (DSA) was used as a noble metal oxide coating electrode that suppresses oxidative decomposition of organic matter as much as possible.

copper Plating  Surface shape

The bonding force between the raw copper plating layer and the resin should be good, and the surface shape of the copper plating layer formed has a great influence on the bonding force between the copper plating layer and the resin. In other words, the more uniform the surface shape, the better the bonding force, and the more uneven the surface shape, the lower the bonding force. Therefore, in order to use for PCB pattern formation, the surface shape of the copper plating layer formed needs to be uniform.

Accordingly, the present inventors first investigated how the organic additives used had an effect on the surface shape of the copper plating layer formed.

Figure 2 shows the surface shape of the copper plating layer according to the type and concentration change of the organic additive. On the other hand, all of the copper plating layer of Figure 2 is formed with a current density of 30 A / dm ² , a reaction temperature of 50 ℃, the flow rate of the electrolyte solution 2.5 L / min.

As shown in FIG. 2, when no additive is present in the electrolyte, it can be seen that the grain size on the surface of the copper plating layer is large and uneven.As a result of the addition, a significant change occurs in the grain size and uniformity of the surface of the copper plating layer. It can be seen.

Among the high molecular weight additives A and B, the medium molecular weight additive D, and the low molecular weight additive E, the surface shape does not change significantly even if each additive concentration is increased. It can be seen that the most uniform surface shape can be obtained in the case of B which is a system additive.

On the other hand, in the case of the medium molecular weight additive C and the low molecular weight additive F, respectively, as the concentration of the additive increases, the surface shape not only becomes largely uneven, but also the grain size increases considerably.

Therefore, assuming that the effects of the anchor treatment in the post treatment nodule treatment are the same, in view of the bonding strength between the formed copper plating layer and the resin, the copper formed using the plating liquid containing additive B is used. It can be seen that the plating layer is most suitable for PCB pattern formation.

copper Plating Residual stress

The residual stress (residual stress) of the copper plating layer formed as shown in FIG. 2 was investigated using XRD.

division Additive A Additive B Additive C Additive D Additive E Additive F Residual stress (MPa) -11.4 ± 4.2 1.8 ± 2.8 2.7 ± 2.1 -4.5 ± 0.8 27.5 ± 10.5 -1.0 ± 4.5 Additive concentration 1 ppm 1 ppm 1 ppm 1 ppm 10ppm 10ppm Residual stress (MPa) 24.9 ± 5.1 4.9 ± 3.4 5.7 ± 2.3 -4.6 ± 2.1 25.5 ± 7.4 12.5 ± 10.0 Additive concentration 2 ppm 2 ppm 5 ppm 5 ppm 20 ppm 20 ppm Residual stress (MPa) -11.1 ± 3.8 3.3 ± 3.4 21.6 ± 1.1 4.8 ± 1.4 38.6 ± 7.5 29.0 ± 15.7 Additive concentration 4 ppm 4 ppm 10ppm 10ppm 40 ppm 50 ppm

As can be seen in Table 3, the residual stress varies from -11.4 MPa (compressive stress) to 38.6 MPa (tensile stress), depending on the type of additive used in copper electroplating, and the concentration of each additive increases. Accordingly, it can be seen that the residual stress in the plating layer also tends to increase.

Among the various additives, when the high molecular weight additive B is used, the residual stress of the plating layer is the lowest and the change of the residual stress is small even when the concentration of the additive is increased.

copper Plating  Grain size

In addition, the grain size of the copper plating layer formed as shown in FIG. 2 was measured. The grain size was measured by precisely polishing and etching the copper plating layer surface and analyzing the image taken by the high magnification optical microscope, and the results are shown in Table 4 below.

division Additive B (1 ppm) Additive A (1 ppm) Additive E (40 ppm) Crystal grain size (㎛) 0.53 0.59 0.63 Residual stress (MPa) 1.8 ± 2.8 -11.4 ± 4.2 38.6 ± 7.5

As can be seen in Table 4, the grain size of the copper plating layer formed of the three kinds of additives was 0.53㎛ ~ 0.63㎛, compared with the residual stress of the copper plating layer, the size of the residual stress as the grain size increases You can see that it grows.

copper Plating  Etching characteristics

In order to examine the etching characteristics when the actual circuit of the copper plating layer formed as shown in FIG. 2 is formed, the copper plating layer prepared by the organic additive and the resin layer are laminated, and as shown in FIG. 3, Line / Space = 100/30 A circuit of size was formed.

In forming the circuit as described above, half etching was performed to grasp the anisotropic etching characteristic of the copper plating layer.

In addition, in order to evaluate the etching characteristics, an etching value was defined and used as shown in FIG. 4. An etching value is calculated | required by following formula 1.

[Formula 1]

Etch Value = H / (W-P) / 2

(H is the etching depth, W is the line spacing on the surface, P is the line spacing on the bottom)

According to Equation 1, the smaller the W-P is, the larger the etching value is. Therefore, the larger the etching value, the larger the anisotropy capable of rapid etching in the thickness direction of the copper plating layer.

FIG. 5 shows a photograph of the cross-sectional shape of the microcircuit formed by the subtractive method with the copper plating layer prepared in the embodiment of the present invention, and the etching index obtained for the plating layer for each additive type and concentration.

As shown in FIG. 5, the etching values of the prepared microcircuits ranged from 2.17 to 8.63. Among these, high molecular weight additives B and low molecular weight additives F exhibited the highest etching values, and copper plating layers formed using copper plating solutions containing additives B and F showed the lowest residual stress values. .

6 is a graph showing the correlation between the residual stress and the circuit etching value of the copper plating layer prepared as described above. As shown in FIG. 6, it can be seen that the lower the residual stress in the residual stress of the copper plating layer and the etching property of the circuit, the higher the etching value of the circuit. In other words, the lower the residual stress of the copper plating layer, the better the anisotropic etching property of the circuit.

On the other hand, the copper plating layer prepared by the additive F is excellent in terms of anisotropic etching property, but is not suitable for use in the microcircuit pattern because the surface shape is very uneven and the bonding strength with the resin is reduced as shown in FIG. .

On the other hand, in the case of the copper plating layer formed by using the additive B, the anisotropic etching property is increased by about 100% or more compared to the etching value of the additive A which is generally used in copper foil production because the surface shape is uniform and there is almost no residual stress. do. Therefore, the copper plating layer prepared according to the embodiment of the present invention can be used very well for the implementation of the microcircuit.

Claims (7)

Copper plating layer for pattern formation of a printed circuit board formed by electroplating using an electrolytic plating solution,
The electrolytic plating solution is CuSO ₄ 5H ₂ O (based on Cu): 20 ~ 80 g / l, H ₂ SO ₄ : 120 ~ 140 g / L, Cl: 10 ~ 30 ppm and a concentration of 1 ~ 5ppm gelatinous material That includes colagel-A,
The copper plating layer is a copper plating layer for forming a printed circuit board pattern, characterized in that the absolute value of the residual stress is 5 MPa or less, the average grain size is 0.7 μm or less, and the etching value represented by the following formula (1) is 6 or more.
[Formula 1]
Etch Value = H / (WP) / 2
Where H is the etch depth, W is the line spacing at the surface, and P is the line spacing at the bottom. delete delete delete A method of manufacturing a copper plating layer for pattern formation of a printed circuit board by an electroplating method using an electrolytic plating solution,
The electrolytic plating solution is CuSO ₄ 5H ₂ O (based on Cu): 20 ~ 80 g / l, H ₂ SO ₄ : 120 ~ 140 g / L, Cl: 10 ~ 30 ppm and a concentration of 1 ~ 5ppm gelatinous material Contains an organic additive consisting of,
The organic additive is colagel-A,
The absolute value of the residual stress of the formed copper plating layer is 5 MPa or less, the average crystal grain size is 0.7㎛ or less, and the etching value represented by the following formula 1 is 6 or more, characterized in that the copper plating layer for forming a printed circuit board pattern.
[Formula 1]
Etch Value = H / (WP) / 2
Where H is the etch depth, W is the line spacing at the surface, and P is the line spacing at the bottom.
delete delete

Images