KR101233729B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The liquid crystal display of the present invention and a method of manufacturing the same are for reducing the parasitic capacitance between the pixel electrode and the data line at the edge of the pixel to improve the luminance characteristics of the pixel. The gate is arranged vertically and horizontally on the first substrate to define the pixel region. Lines and data lines; A thin film transistor formed at an intersection of the gate line and the data line; A common line arranged in the same direction as the gate line; Left and right first dummy lines connected to the common line and arranged in the same direction as the data lines; A pixel electrode formed in the pixel region and having a vertically asymmetrical structure such that a portion of a side surface thereof has a different width and overlaps with a portion of the left and right first dummy lines at upper and lower portions of the pixel region; And a second substrate bonded to the first substrate.

Pixel electrode, data line, parasitic capacitance, dummy line

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a plan view schematically illustrating a portion of an array substrate of a general liquid crystal display;

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

4 is a schematic cross-sectional view taken along line III-III 'of the array substrate shown in FIG.

5 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

6A through 6D are cross-sectional views sequentially illustrating a manufacturing process along the line VV ′ of the array substrate illustrated in FIG. 5.

DESCRIPTION OF REFERENCE NUMERALS

16,116,216: Gate line 17,117: Data line

18,118,218: pixel electrodes 108,108 ', 208,208': first dummy line

108l, 208l: Common line 108s, 208s: Storage electrode

209,209 ': Second dummy line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same. More particularly, a liquid crystal display (LCD) having reduced parasitic capacitance between a pixel electrode and a data line to improve luminance characteristics of a pixel, and a manufacturing method thereof It is about a method.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the array substrate 10 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. It consists of (8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of mask processes in terms of productivity is required. It is required.

2 is a plan view schematically illustrating a portion of an array substrate of a general liquid crystal display device.

As shown in the figure, a gate line 16 and a data line 17 are formed on the array substrate 10 to be arranged vertically and horizontally on the array substrate 10 to define a pixel area. In this case, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 16 and the data line 17, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 18 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 21 constituting a part of the gate line 16, a source electrode 22 connected to the data line 17, and a drain electrode 23 connected to the pixel electrode 18. It is. In addition, the thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 21 and the source / drain electrodes 22 and 23 and the source electrode by the gate voltage supplied to the gate electrode 21. It includes an active pattern (not shown) to form a conductive channel between the 22 and the drain electrode (23).

In general, the pixel electrode of the array substrate forms a liquid crystal capacitor together with the common electrode of the color filter substrate, and the pixel voltage applied to the liquid crystal capacitor is not maintained until the next signal and leaks and disappears. Therefore, in order to maintain the applied pixel voltage for a predetermined time, the storage capacitor should be connected to the liquid crystal capacitor.

In this case, as the size of the liquid crystal display increases, the capacity of the storage capacitor must be increased to maintain the pixel voltage stably. However, the structure of a general liquid crystal display has a limitation in increasing the capacity of the storage capacitor.

In addition, an inorganic insulating film having a high dielectric constant, such as a silicon oxide film and a silicon nitride film, is generally used as a protective film of an array substrate, and parasitic capacitance is generated between the pixel electrode and the data line between the inorganic insulating film. . In this case, in order to minimize the coupling effect due to the parasitic capacitance, the data line should be formed with the pixel electrode at a constant horizontal interval, for example, a horizontal interval of 3 to 5 μm. In this case, light leaks into the gap between the data line and the pixel electrode, thereby degrading the image quality of the liquid crystal display.

In order to block the light causing the deterioration of the image quality, there is a method of covering the area where the light leaks by increasing the width of the black matrix formed on the color filter substrate. However, when the pixel pitch is increased or when applied to a large-area substrate, the black matrix width must be designed to be larger in consideration of the variation in the bonding process, thereby reducing the aperture ratio of the liquid crystal display.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, in which a parasitic capacitance between a pixel electrode and a data line is reduced by forming a dummy line under the data line.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which further reduce the parasitic capacitance between the pixel electrode and the data line by forming the structure of the pixel electrode up and down asymmetrically.

Other objects and features of the present invention will be described in the following description of the invention and claims.

In order to achieve the above object, the liquid crystal display device of the present invention comprises a gate line and a data line arranged vertically and horizontally on the first substrate to define a pixel region; A thin film transistor formed at an intersection of the gate line and the data line; A common line arranged in the same direction as the gate line; Left and right first dummy lines connected to the common line and arranged in the same direction as the data lines; A pixel electrode formed in the pixel region and having a vertically asymmetrical structure such that a portion of a side surface thereof has a different width and overlaps with a portion of the left and right first dummy lines at upper and lower portions of the pixel region; And a second substrate bonded to the first substrate.

In addition, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate; Forming a common line in the same direction as the gate line while forming a gate electrode and a gate line on the first substrate; Forming a first insulating film on the first substrate on which the gate electrode, the gate line, and the common line are formed; Forming an active pattern on the first substrate on which the first insulating film is formed; Forming a source electrode and a drain electrode on the first substrate on which the active pattern is formed, and forming a data line crossing the gate line to define a pixel region; Forming a second insulating film on the first substrate on which the source electrode, the drain electrode, and the data line are formed; Forming a pixel electrode having a vertically asymmetrical structure in the pixel region where the second insulating film is formed; And bonding the first substrate and the second substrate to each other, wherein the common line is formed under the pixel electrode in the same direction as the data line, a part of which is disposed above and below the pixel region. The left and right first dummy lines having different widths and overlapping sides of the pixel electrode may be formed.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 4 is a schematic view illustrating a cross section taken along line III-III ′ of the array substrate illustrated in FIG. 3. to be.

At this time, although N gate lines and M data lines cross MxN pixels on the actual array substrate, one pixel is shown in the figure for simplicity of explanation.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged on the array substrate 110 in a vertical direction to define a pixel area. In this case, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 116 and the data line 117, and is connected to the thin film transistor in the pixel area, and the common electrode of a color filter substrate (not shown). In addition, a pixel electrode 118 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 121 constituting part of the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the pixel electrode 118. It is. In addition, the thin film transistor is formed by the first insulating film 115a for insulating the gate electrode 121 and the source / drain electrodes 122 and 123 and the gate electrode 122 supplied by the gate voltage supplied to the gate electrode 121. ) And an active pattern 124 ′ forming a conductive channel between the drain electrode 123 and the drain electrode 123.

In this case, a part of the drain electrode 123 extends toward the pixel region and is electrically connected to the pixel electrode 118 through the contact hole 140 formed in the second insulating layer 115b.

In this case, the common line 108l is arranged in the pixel area in substantially the same direction as the gate line 116, and a part of the common line 108l is formed of the first insulating film 115a and the second insulating film ( The storage electrode 108s forming the first storage capacitor Cst1 overlaps the upper pixel electrode 118 with the 115b interposed therebetween.

The storage capacitor keeps the pixel voltage applied to the liquid crystal capacitor constant until the next signal is input. In addition to maintaining the signal, the storage capacitor provides stability of gray scale display, flicker, and afterimage. ) Has the effect of reducing.

The storage capacitor can be formed by two methods, a method of forming an electrode for the storage capacitor separately and connecting the common capacitor and using a part of the front gate line as an electrode of the storage capacitor of the corresponding pixel. The former is called a storage on common method or an independent storage capacitor method, and the latter is called a storage on gate or a prior gate method.

In this case, the first embodiment has been described, for example, in which the storage capacitor is formed by the storage on common method, but the present invention is not limited thereto, and the present invention is not limited thereto. Applicable

In addition, in the first embodiment, dummy lines 108 and 108 'are additionally configured on the array substrate 110 to increase the aperture ratio by reducing the variation in the bonding process described above.

In this case, the dummy lines 108 and 108 ′ are connected to the common line 108l and formed in substantially the same direction as the data line 117, and a part of the dummy lines 108 and 108 ′ overlap the upper pixel electrode 118. The second storage capacitor Cst2 is formed.

Since the dummy lines 108 and 108 ′ are formed on the array substrate 110, the bonding margin as in the black matrix is not required, and the aperture ratio can be increased by reducing the black matrix width corresponding to the overlap region. In addition, the capacity of the storage capacitors Cst1 and Cst2 is increased to improve the image quality of the liquid crystal display.

In this case, the dummy lines 108 and 108 ′ form a horizontal electric field with the data line 117 at the edge of the pixel electrode 118 that is an overlapping region, causing a foreground phenomenon. When the overlap region between the left and right dummy lines 108 and 108 ′ is different, the left and right parasitic capacitances formed between the pixel electrode 118 and the left and right data lines 117 are different.

5 is a plan view schematically illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

At this time, although N gate lines and M data lines cross MxN pixels on the actual array substrate, one pixel is shown in the figure for simplicity of explanation.

In addition, the liquid crystal display of the second embodiment has the same configuration as the liquid crystal display of the first embodiment described above except that the pixel electrodes have a vertically asymmetric structure and a second dummy line is formed under the data line.

As shown in the figure, a gate line 216 and a data line 217 are formed on the array substrate 210 in the second embodiment, which are arranged horizontally and horizontally on the array substrate 210 to define a pixel area. In this case, a thin film transistor, which is a switching element, is formed in an intersection area of the gate line 216 and the data line 217, and is connected to the thin film transistor in the pixel area and is connected to a common electrode of a color filter substrate (not shown). A pixel electrode 218 for driving a liquid crystal (not shown) is formed.

The thin film transistor includes a gate electrode 221 constituting a part of the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the pixel electrode 218. It is. In addition, the thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 221 and the source / drain electrodes 222 and 223 and a gate voltage supplied to the gate electrode 221. An active pattern (not shown) forming a conductive channel between the 222 and the drain electrode 223 is included.

In this case, a part of the drain electrode 223 extends toward the pixel region to be electrically connected to the pixel electrode 218 through a contact hole 240 formed in a second insulating layer (not shown).

In this case, a common line 208l is arranged in the pixel area in substantially the same direction as the gate line 216, and a part of the common line 208l is interposed between the first insulating film and the second insulating film. The storage electrode 208s overlapping the upper pixel electrode 218 to form a storage capacitor Cst is formed.

At this time, the first dummy lines 208 and 208 'are connected to the common line 208l as in the first embodiment, and the first dummy lines 208 and 208' are connected to the common line 208l. ) Is formed in substantially the same direction as the data line 217. In this case, a part of the first dummy lines 208 and 208 'overlaps with the upper pixel electrode 218. The pixel electrode 218 of the second embodiment has an asymmetric top and bottom structure, and thus the first dummy line. The regions overlapping the lines 208 and 208 'are different from each other in the upper and lower sides and the left and right sides of the pixel electrode 218. The pixel electrode 218 has an up-down asymmetrical structure such that a portion of the pixel electrode 218 has a different width and overlaps with a portion of the first dummy lines 208 and 208 'above and below the pixel area.

That is, the left and right side surfaces of the pixel electrode 218 may include a first dummy line 208 positioned on the left side of the pixel electrode 218 and a first position positioned on the right side of the pixel electrode 218, respectively. The overlapping width between the dummy lines 208 'is different. In this case, a portion of the left side of the pixel electrode 218 is reduced to the inside of the pixel area in the upper portion of the pixel electrode 218 so that it overlaps less with the first dummy line 208 on the left side of the pixel electrode 218. In FIG. 2, the right side of the pixel electrode 218 is reduced into the pixel area, so that the right side of the pixel electrode 218 overlaps the first dummy line 208 ′ of the right side.

As such, when the pixel electrode 218 has a vertically asymmetric structure as shown in FIG. 5, the capacitance between the pixel electrode 218 and the data line 217 on the left side of the pixel electrode 218 is above. In the lower portion of the pixel electrode 218, the capacitance between the pixel electrode 218 and the right data line (not shown) is reduced.

In addition, since the first dummy lines 208 and 208 'are formed on the array substrate 210, the bonding margin as in the black matrix is not required, and the aperture ratio can be increased by reducing the black matrix width corresponding to the overlap region. Will be.

In this case, the array substrate 210 of the second embodiment includes second dummy lines 209 and 209 'formed under the data line 217 and made of the same conductive material as the common line 208l. The second dummy lines 209 and 209 'are positioned under the data line 217 to reduce parasitic capacitances between the data line 209 and the pixel electrode 218.

As described above, in the liquid crystal display of the second embodiment, the pixel electrodes are formed in an up-down asymmetric structure, the first dummy line is formed below the pixel electrode to overlap the pixel electrode, and the second dummy line is formed below the data line. The parasitic capacitance between the data line and the pixel electrode can be reduced, and as a result, the luminance characteristic of the pixel is improved. In this case, the first dummy line and the second dummy line may be formed using the same conductive material as the common line when forming the common line, which will be described in detail through the following manufacturing process of the liquid crystal display. .

6A through 6D are cross-sectional views sequentially illustrating a manufacturing process along a line VV ′ of the array substrate illustrated in FIG. 5.

As shown in FIG. 6A, a gate electrode 221 and a gate line (not shown) are formed on a substrate 210 made of a transparent insulating material such as glass.

The gate electrode 221 and the gate line are formed by depositing a first conductive layer on the entire surface of the substrate 210 and then patterning the same through a photolithography process (first mask process). A common line (not shown), a first dummy line 208, and a second dummy line 209 and 209 ′ are formed on the substrate 210 using a first conductive layer.

Although not shown in the drawing, the common line is formed in substantially the same direction as the gate line, and a part of the common line forms a pixel electrode and a storage electrode 208s forming a storage capacitor, which will be described later.

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. The gate electrode 221, the gate line, the common line, the first dummy line 208, and the second dummy line 209 and 209 ′ may have a multilayer structure in which two or more low resistance conductive materials are stacked. It may be.

Next, as shown in FIG. 6B, the gate electrode 221, the gate line, the common line, the first dummy line 208, and the second dummy line 209 and 209 ′ are formed on the entire surface of the substrate 210. After depositing the first insulating film 215a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second thin film were subjected to a photolithography process (second mask process). By selectively patterning the conductive film, an active pattern 224 'made of the amorphous silicon thin film is formed on the gate electrode 221, and a source electrode 222 and a drain electrode 223 made of the second conductive film are formed. do.

In this case, the n + amorphous silicon thin film is formed on the active pattern 224 ', and is patterned in the same form as the source / drain electrodes 222 and 223 to form a predetermined region and the source of the active pattern 224' below. An ohmic contact layer 225n for ohmic contacting the / drain electrodes 222 and 223 is formed. In this case, a portion of the source electrode 222 substantially crosses the gate line to form a data line 217 defining a pixel region.

In this case, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy may be used as the second conductive layer.

In addition, the data line 217 is formed on the second dummy lines 209 and 209 ', so that the data line 217 has a larger line width than the second dummy lines 209 and 209'. The second dummy lines 209 and 209 'may be formed to be insulated from the data line 217 and the common line.

As described above, in the second embodiment, the active pattern 224 'and the source / drain electrodes 222 and 223 are simultaneously formed by one mask process (second mask process) using diffraction exposure. However, the present invention is not limited thereto, and may also be applied to the case in which the active pattern 224 'and the source / drain electrodes 222 and 223 of the present invention are formed through two mask processes.

For reference, reference numerals 224 "and 225" are formed under the data line 217, and indicate an amorphous silicon thin film pattern made of the amorphous silicon thin film and an n + amorphous silicon thin film pattern made of an n + amorphous silicon thin film.

6C, after depositing a second insulating film 215b on the entire surface of the substrate 210 on which the source electrode 222 and the drain electrode 223 are formed, a photolithography process (third mask process) is performed. A portion of the second insulating layer 215b may be removed to form a contact hole 240 exposing a portion of the drain electrode 223.

Thereafter, as illustrated in FIG. 6D, a transparent conductive material is deposited on the entire surface of the substrate 210 and then selectively patterned using a photolithography process (a fourth mask process) to form a drain electrode through the contact hole 240. The pixel electrode 218 electrically connected to the 223 is formed.

In this case, the transparent conductive material includes a conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In this case, a portion of the pixel electrode 218 overlaps the lower storage electrode 208s and the storage capacitor 208s together with the storage electrode 208s with the first insulating layer 215a and the second insulating layer 215b therebetween. Cst (see FIG. 5) is formed.

In addition, the left and right side portions of the pixel electrode 218 overlap the first dummy line 208 at the bottom, and the overlapping regions have an asymmetrical structure so as to be different from each other in the upper and lower portions of the pixel region.

The array substrate 210 configured as described above is bonded to face the color filter substrate (not shown) by a sealant (not shown) formed at the outer side of the image display area to form a liquid crystal display panel. The bonding of the color filter substrate is performed through a bonding key (not shown) formed on the array substrate 210 and the color filter substrate.

At this time, the embodiment has been described using an amorphous silicon thin film transistor using an amorphous silicon thin film as an active pattern, for example, but the present invention is not limited thereto, and the present invention is a polycrystalline silicon thin film transistor using a polycrystalline silicon thin film as the active pattern. Also applies.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

As described above, the liquid crystal display and the method of manufacturing the same according to the present invention provide an effect of improving the luminance characteristic of the pixel by reducing the parasitic capacitance between the data line and the pixel electrode.

Claims (17)

Gate lines and data lines arranged vertically and horizontally on the first substrate to define pixel regions; A thin film transistor formed at an intersection of the gate line and the data line; A common line arranged in the same direction as the gate line; Left and right first dummy lines connected to the common line and arranged in the same direction as the data lines; A pixel electrode formed in the pixel region and having a vertically asymmetrical structure such that a portion of a side surface thereof has a different width and overlaps with a portion of the left and right first dummy lines at upper and lower portions of the pixel region; And And a second substrate bonded to the first substrate. delete delete delete The pixel electrode of claim 1, wherein a left side of the pixel electrode is reduced into the pixel area in the upper portion of the pixel electrode so as to overlap the left first dummy line, and a right side of the pixel electrode is in the lower portion of the pixel electrode. The liquid crystal display according to claim 1, wherein the liquid crystal display is reduced within the region so as to overlap with the right first dummy line. The liquid crystal display of claim 1, further comprising a second dummy line formed under the data line. The liquid crystal display of claim 6, wherein the first dummy line and the second dummy line are made of the same conductive material as the common line. 7. The liquid crystal display of claim 6, wherein the second dummy line is electrically insulated from the data line and the common line. The liquid crystal display device of claim 1, wherein the common line comprises a storage electrode overlapping a pixel electrode thereon in the pixel region to form a storage capacitor. Providing a first substrate; Forming a common line in the same direction as the gate line while forming a gate electrode and a gate line on the first substrate; Forming a first insulating film on the first substrate on which the gate electrode, the gate line, and the common line are formed; Forming an active pattern on the first substrate on which the first insulating film is formed; Forming a source electrode and a drain electrode on the first substrate on which the active pattern is formed, and forming a data line crossing the gate line to define a pixel region; Forming a second insulating film on the first substrate on which the source electrode, the drain electrode, and the data line are formed; Forming a pixel electrode having a vertically asymmetrical structure in the pixel region where the second insulating film is formed; And And bonding the first substrate and the second substrate, The common line is formed under the pixel electrode in the same direction as the data line, and a part of the common line overlaps the side of the pixel electrode at upper and lower portions of the pixel area and overlaps the left and right sides. 1 is a manufacturing method of a liquid crystal display device characterized by forming a dummy line. delete The pixel electrode of claim 10, wherein a left side of the pixel electrode is shortened to the inside of the pixel area so that the left side of the pixel electrode overlaps the left first dummy line, and a right side of the pixel electrode is located below the pixel electrode. And reducing the inner portion of the pixel area to overlap the right first dummy line. The method of claim 10, wherein the first dummy line is connected to the common line. The method of claim 10, further comprising forming a second dummy line under the data line. 15. The method of claim 14, wherein the first dummy line and the second dummy line are formed through the same mask process as the common line. The method of claim 14, wherein the second dummy line is electrically insulated from the data line and the common line. 12. The liquid crystal display of claim 10, further comprising forming a storage electrode which forms a part of the common line and overlaps the pixel electrode on the upper portion of the common region to form a storage capacitor. Method of manufacturing the device.

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