KR101229649B1 - Method for mounting chips using lateral side, chip assembly mounted by the sam, and method for manufacturing chip for the same - Google Patents

Abstract

Provided are a chip stacking method using side surfaces, and a chip assembly stacked thereon and a chip manufacturing method therefor.
In the chip stacking method according to the present invention, a chip stacking structure in the form of a chip-first insulating layer-chip is formed by coating a first insulating layer on a chip and then stacking another chip on the first insulating layer. Forming;
Stacking a second insulating layer on a side of the chip stack; And
And compressing a conductive connection member having one or more bumps of a predetermined height into the second insulating layer, wherein the chip pad is exposed to the side surface of the chip stack structure, and the bump is formed by the pressing. In contact with the chip pad in the second insulating layer.

Description

Method for mounting chips using lateral side, chip assembly mounted by the sam, and method for manufacturing chip for the same}

The present invention relates to a chip stacking method using side surfaces, a chip assembly stacked thereon, and a chip manufacturing method therefor, and more particularly, electrically connecting chip pads exposed on chip sides by a simple process such as thermocompression bonding. Therefore, the present invention relates to a chip stacking method using side surfaces, which is economical in a process, a chip assembly stacked thereon and a chip manufacturing method therefor.

Recently, as the electronic products have been improved in performance, miniaturization, and weight, chip integration density has increased, and in order to satisfy this, research on three-dimensional packaging in which a plurality of chips are stacked is being actively conducted. Three-dimensional packaging has developed methods such as through silicon via (TSV), wire bonding, and edge traces according to the interconnection method. TSV has the advantage of reducing power consumption, fast signal transmission speed, and high input / output density compared to wire bonding because the length of signal line connecting the stacked chip is the shortest. On the other hand, TSV has a high production cost in the bonding and debonding process. On the other hand, wire bonding has a disadvantage in that the volume of the entire chip is increased because a predetermined distance between layers is to be spaced between dummy wafers called spacers in order to stack chips in a stacking manner in which circuits are connected by wires.

Since the three-dimensional stacking technology of the semiconductor chip is a technology that can increase the integration density of the semiconductor, a number of patents and research papers related to this have been published and disclosed, and various methods for forming circuit lines on the side of the stacked chip have been disclosed. Is being presented. In the “chip stack package” of Korean Patent No. 10-2006-0109524, a method of stacking chips and forming interconnections between pads using wire bonding has been presented. In Korean Patent No. 10-2006-0082924, “Semiconductor Package and Manufacturing Method”, a method of stacking chips and forming signal lines between stacked chips using wire bonding and conductive columns has been presented. Korean Patent No. 10-2006-0001150 "Multi-stack package and its manufacturing method" proposed a thermocompression method for forming a metal bump on the laminated chip and making a joint by applying a pressure . In addition, in Korean Patent No. 10-2008-0072951, 'chip package, a stacked package using the same, and a manufacturing method thereof', signal lines between the stacked chips are formed by using signal lines and solder balls passing through a plurality of chips. The above patents apply a method of wire bonding, TSV, etc., which is a semiconductor bonding method, to manufacture a three-dimensional package by stacking chips. The use of wire bonding in stacking requires the use of spacers, which increases the volume of the chip, and TSV has disadvantages of complicated via drilling and high production costs. In addition to the patent as a prior art, various research papers have been published on the three-dimensional stacking technology of silicon chips. Among them, a research paper ('A review of 3D packaging technology, IEEE Trans.on Components, Packaging and Manufacturing Tech., Vol. 21, No. 1, 1998) describes various three-dimensional stacking technologies. In the case of forming signal lines on the side of the stacked chip among the stacking techniques proposed in the above, methods for preventing a short circuit by forming an insulating layer on the side of the chip are proposed. However, these methods insulate the side of the chip after manufacturing the chip. The process is complicated and the productivity is low because the layer is formed and the vertical patterning process is required.

Accordingly, the present invention has been made to solve the problems of the prior art as described above, there is a problem to be solved by the present invention to provide a chip stacking method that can increase the productivity by forming an electrical interconnection between the stacked chips. .

Another object of the present invention is to provide an electrical interconnection between stacked chips, and to provide a chip stacking means and a method of manufacturing the same, which do not require insulation of a separate chip side.

In the chip stacking method according to the present invention, a chip stacking structure in the form of a chip-first insulating layer-chip is formed by coating a first insulating layer on a chip and then stacking another chip on the first insulating layer. Forming; Stacking a second insulating layer on the side of the chip stack structure; And compressing a conductive connection member having one or more bumps of a predetermined height into the second insulating layer, wherein the chip pads are exposed to side surfaces of the chip stack structure, and bumps are formed by the compression. Is in contact with the chip pad inside the second insulating layer.

The present invention is economical in the lamination process since the chip pad exposed on the chip side is electrically connected by a simple process such as thermocompression bonding or the like. In addition, another adhesive layer provided on the side of the chip has an insulating property so as not only to fit the chip to the conductive connection member that forms the vertical interconnection between the chip, but also insulates the chip side.

Therefore, separate insulation of the chip side is eliminated as in the prior art. In addition, since the conductive connection member in the form of a metal line formed on the substrate may have various shapes using only conventional techniques, it is possible to effectively implement interlayer interconnection of a complicated structure. Furthermore, since the pad metal of the stacked chip and the vertical bump signal line bond the same metal by diffusion bonding, there is an advantage in that mechanical and thermal reliability are excellent. In addition, since the chips stacked vertically and the chips for connecting them on the chip side are made of the same material, there is a high thermal and mechanical reliability of the entire assembly.

1 to 5 are diagrams illustrating a chip stacking method according to an embodiment of the present invention.
6 is an enlarged cross-sectional view of a contact portion between the bump 330 and the chip pad 110 according to FIG. 5.
7 is an exploded perspective view illustrating a structure of a stacked chip assembly according to an embodiment of the present invention.
8 is a schematic diagram illustrating a process of manufacturing a stacking chip in which pads are formed along side surfaces of a chip at a wafer level.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention can be implemented in various different forms, and is not limited to the embodiments described. In order to clearly describe the present invention, parts that are not related to the description are omitted, and the same reference numerals in the drawings denote the same members.

Throughout the specification, when an element is referred to as " including " an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software.

The present invention is provided on top of the chip, and after exposing a chip pad of a predetermined height on the side, using a separate conductive vertical connection for electrically connecting the chip pad to stack the chips.

1 to 5 are diagrams illustrating a chip stacking method according to an embodiment of the present invention.

Referring to FIG. 1, a chip 100 stacked vertically in accordance with the present invention is disclosed.

The chip pad 110, which is a member for connecting signal lines to the outside, is provided on the chip 100 according to an embodiment of the present invention (FIG. 1A). In particular, the chip pad 110 according to an embodiment of the present invention is not a form that is inside the chip, but a form where one side is in contact with an outer boundary of the chip (FIG. 1B). As a result, the side of the chip 100 and the side of the chip pad 110 may be simultaneously exposed to the outside, and the present invention utilizes the exposed side of the chip pad 110 as a chip-to-chip interconnection position.

Referring to FIG. 2, the unit chips 300 including the chip 100 and the chip pad 110 of FIG. 1 are stacked vertically. In this case, a first adhesive layer 310 made of an insulating material is provided between the unit chip 300 and the unit chip 300, whereby the unit chip 300 and the unit chip 300 are separated by a predetermined height. 1 A lamination structure of an adhesive layer-chip is formed. In addition, despite application of the first adhesive layer 310, side surfaces of the chip pad 110 and the chip 100 are exposed to the outside.

Referring to FIG. 3, an insulating second adhesive layer 320 is coated on the chip pad 110 and the chip 100. In one embodiment of the present invention, the first and second adhesives may be at least one heterogeneous material selected from the group consisting of a thermosetting adhesive, a thermoplastic adhesive, a photocurable adhesive, a photoplastic adhesive, and a photosensitive material.

Referring to FIG. 4, a conductive connection member 340 having a metal line shape in which a plurality of bumps 330, which are protruding members for electrically connecting chips, contacting the chip pad 110 is connected to the second adhesive layer 320. Pressed (compressed), and as a result, the bump 330 as the protruding member comes into contact with the corresponding chip pad 110 (see FIG. 5). As such, the one or more bumps 330 are in contact with each of the one or more chip pads, so that the conductive connection member 340 forms the chip-to-chip electrical interconnection stacked in the vertical direction. In one embodiment of the present invention, the conductive connecting member is preferably in the form of a metal line that electrically connects the chip pads constituting the interconnection. Thus, the conductive connecting member may be formed such as a chip for ease of adhesion. The substrate is patterned on a separate substrate 350. In one embodiment of the present invention, the substrate 350 is preferably made of the same material as the chip, thereby having the same physical properties as the thermal expansion coefficient of the chip assembly as a whole. Can be.

In one embodiment of the present invention, the bumps may be various shapes such as conical, hemispherical or flat, and the scope of the present invention is not limited to the bump shapes disclosed in the drawings of the present specification.

In one embodiment of the present invention, the compression direction of the conductive connection member 340 should be a direction in which the bump 330 protruding in a predetermined direction from the connection member 340 may contact the chip pad 110. In addition, in one embodiment of the present invention, the compression is preferably a compression of a method of applying a predetermined heat, such as thermocompression bonding, ultrasonic bonding, thermosonic bonding process. That is, the bump 330 can easily penetrate the softened second adhesive layer 320 by applying heat, thereby effectively inducing electrical contact between the chip pad and the bump.

After contact between the bump 330 and the chip pad 110, the second adhesive layer 320 is cured, whereby the substrate 350 having the conductive connection member 340 patterned thereon is formed on the second adhesive layer 320. It is firmly attached mechanically. Therefore, because of the second adhesive layer 320, a separate insulation treatment step of the side of the chip is unnecessary, the chip stacking method according to the present invention is process economical compared to the prior art.

6 is an enlarged cross-sectional view of a contact portion between the bump 330 and the chip pad 110 according to FIG. 5.

Referring to FIG. 6, the bump 330, which is a protruding metal member having a predetermined height penetrating into the second bonding layer 320, contacts the chip pad 110. In particular, the vertical position of the bump 330 may correspond to the bump 330. It is preferable that the chip pad is the same as or slightly higher than the chip pad, because such a configuration allows selective contact with the chip pad 110.

7 is an exploded perspective view illustrating a structure of a stacked chip assembly according to an embodiment of the present invention.

Referring to FIG. 7, a plurality of chips 100 are stacked in a vertical direction, and an insulating first adhesive layer is coated between the chips. In addition, the chip 100 and the chip pad 110 provided on the chip have exposed sides.

In addition, the substrate 350 for constituting the interconnection in the vertical direction between the chips is bonded to the chip side surface by a second adhesive layer, wherein the bump 330 in contact with the chip pad 110 is formed on the substrate 350. The conductive connection member 340 provided with at least one is laminated and patterned. In FIG. 7, a portion indicated by a dotted line represents a metal line protruding by a predetermined height in an opposite side of the substrate 350, that is, in a chip lateral direction. As such, the conductive connection member in the form of a metal line formed on the substrate may be manufactured in various structures using only conventional patterning techniques. Through the side patterning structure, the present invention effectively realizes interlayer interconnection of a complicated structure.

In the present invention, as described above, for the contact with the bumps, chip pads formed along the same boundary as the chip boundary, that is, along the chip side surface, are very important. Hereinafter, a chip manufacturing method according to an embodiment of the present invention will be described with reference to the drawings.

8 is a schematic diagram illustrating a process of manufacturing a stacking chip in which pads are formed along side surfaces of a chip at a wafer level.

Referring to FIG. 8, first, a metal pad 110 is deposited on a chip substrate 100. The deposition may be performed using electroplating, thermal evaporator, e-beam evaporator, or sputtering.

Thereafter, the metal pad portion is cut by using a dicing blade or a laser having a specific width w to process the pad on the side of the chip. As a result, the predetermined width of the metal pad 110 is removed, thereby completing the stacking chip in which the chip pad 110 is formed along the chip boundary.

The technical details of the chip stacking method of the present invention have been described with reference to the accompanying drawings, but the exemplary embodiments of the present invention are described by way of example and are not intended to limit the present invention.

In addition, it is obvious that any person skilled in the art can make various modifications and imitations within the scope of the appended claims without departing from the scope of the technical idea of the present invention.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art.

Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (16)

A stacking method of a chip having a chip pad provided thereon, the method
Forming a chip stack structure in the form of a chip-first adhesive layer-chip by applying a first adhesive layer over the chip, and then attaching another chip to the first adhesive layer first;
Stacking a second adhesive layer on a side of the chip stack; And
And compressing a conductive connection member having one or more bumps of a predetermined height into the second adhesive layer, wherein the chip pads are exposed to side surfaces of the chip stack structure, and the bumps are formed by the pressing. And a second adhesive layer in contact with the chip pad in the second adhesive layer, wherein the conductive connection member is pressed onto the chip side surface in a direction parallel to the chip stacking direction. The method of claim 1,
And the conductive connecting member is a metal line patterned on another substrate. The method of claim 1,
And the first adhesive layer and the second adhesive layer are made of an insulating material. The method of claim 1,
The first bonding and the second bonding is a chip stacking method, characterized in that the progress in any one of the process of thermocompression bonding, ultrasonic bonding, thermosonic bonding. delete The method of claim 1,
The chip pad is characterized in that formed along the chip side. The method of claim 1,
And the first adhesive layer and the second adhesive layer are selected from the group consisting of a thermosetting adhesive, a thermoplastic adhesive, a photocurable adhesive, a photoplastic adhesive, and a photosensitive material. The method of claim 1,
And wherein said bumps are conical, hemispherical or flat. A chip assembly laminated according to any one of claims 1 to 4 and 6 to 8. The method of claim 9,
The chip assembly is
A first adhesive layer applied between chips having chip pads formed thereon;
A second adhesive layer formed on the side of the chip; And
A substrate on which a conductive connection member stacked and bonded on the second adhesive layer and having at least one bump having a predetermined height is patterned thereon, wherein the bump contacts the chip pad within the second adhesive layer, And the conductive connecting member is pressed onto the side of the chip in a direction parallel to the stacking direction of the chip. The method of claim 10,
And the conductive connection member electrically interconnects the stacked plurality of chips in a vertical direction. 12. The method of claim 11,
And the first adhesive layer and the second adhesive layer are made of an insulating material. A chip used in the lamination method according to any one of claims 1 to 4 and 6 to 8, wherein the chip is a chip for lamination, wherein the chip pad is formed along the chip side. A method for manufacturing a chip for lamination used in the lamination method according to any one of claims 1 to 4 and 6 to 8.
Depositing a metal pad on a chip substrate; And
And cutting the stacked metal pads and the lower chip substrate. The method of claim 14,
The stacking method of the stacking chip, characterized in that the thermal evaporator (Thermal evaporator), an e-beam evaporator (E-beam evaporator) or a sputtering (sputtering) method. The method of claim 14,
The cutting is a method for manufacturing a chip for lamination, characterized in that the metal pad portion is cut using a dicing blade or laser having a specific width.

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