TWI550731B - Chip package process and chip package - Google Patents

Description

Chip packaging process and chip package

The present invention relates to a package process and package structure, and more particularly to a chip package process and a chip package structure.

With the advent of the digital information age, multimedia goods, household appliances, and personal digital goods have developed rapidly. These products usually require features such as small size, high efficiency, versatility, high speed, large capacity, and low price. Therefore, a stacked package or a system in package has been developed in which a plurality of wafers are stacked in parallel in a single semiconductor or vertically stacked on top of one another.

Stacked or system-in-packages, including multiple wafers assembled in a single package, have the advantages of increased electrical performance, reduced package size, and reduced manufacturing costs. However, since the pitch of the wafer pads is small in a stacked package or system level package, the connection between the wafer pads and the interconnection pads of the interconnection substrate is difficult.

To solve this problem, use multiple layers of interconnects in a stacked package or system-in-package A multi-layered interconnection substrate, or an interposer, is used for the connection between the wafer pads and the interconnect pads of the interconnect substrate. That is, in a conventional stacked package or system-in-package, a redistribution layer is formed in a multilayer interconnection substrate or an additional interposer, and then the wafer pad is connected to the interconnect substrate using a reconfiguration wiring layer. Interconnect pads.

However, since the redistribution is performed using a multilayer interconnection substrate or an additional interposer wafer in a conventional stacked package or system-in-package, packaging cost and package thickness are increased, which makes it difficult to meet the thinning requirements of electronic devices today.

The invention provides a chip packaging process, wherein the fabricated wafer package has a thin thickness and a relatively simple process.

The present invention provides a wafer package having a thin package thickness and a relatively simple process.

The wafer packaging process of the present invention comprises the following steps. First, a wafer is provided. The wafer has an active surface and a back side opposite the active surface. The wafer includes a plurality of first wafers that are connected to each other and arranged in an array. Next, a flexible reconfigurable line film is placed on the back side of the wafer. The flexible reconfigurable line film includes a plurality of array arrangements and corresponds to a reconfigured line pattern of the first wafer. Next, the wafer and the flexible reconfigurable wiring film are diced to separate the first wafers from each other and to separate the reconfigured wiring patterns from each other. Next, one of the first wafers is placed on the carrier with the active surface of the first wafer facing the carrier. Next, the electronic components are placed on the reconfiguration line pattern. After that, through multiple connection terminals The electronic component and the carrier are electrically connected.

The present invention provides a chip package including a carrier, a first wafer, a flexible reconfigurable line pattern, an electronic component, and a plurality of connection terminals. The first wafer is disposed on the carrier and has an active surface and a back surface opposite the active surface. The active surface faces the carrier. The flexible reconfiguration line pattern is disposed on the back side of the first wafer. The edges of the flexible reconfigurable line pattern are substantially aligned with the edges of the first wafer. The electronic components are disposed on the flexible reconfigurable line pattern. The connection terminals are electrically connected to the electronic component and the carrier, respectively.

In an embodiment of the invention, the flexible reconfigurable wiring film is attached to the back surface of the wafer by an adhesive layer.

In an embodiment of the invention, the step of providing the flexible reconfigurable line film on the back side of the wafer further comprises the following steps. First, a reconfiguration line component is provided. The reconfiguration line assembly includes a base film, a release film, and a flexible reconfigurable line film. The release film is disposed between the base film and the flexible reconfigurable wiring film. The flexible reconfigurable wiring film includes a flexible substrate and a patterned metal layer. The patterned metal layer is between the release film and the flexible substrate. Next, the flexible substrate of the reconfiguration line assembly is bonded to the back side of the wafer. Next, the wafer and the flexible substrate are diced. Thereafter, the release film is separated from each of the first wafers to expose the patterned metal layer on each of the first wafers.

In an embodiment of the invention, the method of separating the release film from each of the first wafers comprises the following steps. First, push the base film through a thimble to reduce one of them. The bonding area of the first wafer and the release film. Picking up the first wafer that is pushed by the thimble.

In an embodiment of the invention, the first wafer is disposed on the carrier by flip chip bonding.

In an embodiment of the invention, the electronic component further includes a plurality of solder balls, and the reconfigurable circuit pattern includes a plurality of solder pads for respectively bonding with the solder balls, and the carrier further includes a plurality of pads. The electronic component is electrically connected to the carrier through solder balls, pads, connection terminals, and pads.

In an embodiment of the invention, the method for electrically connecting the electronic component and the carrier through the connection terminal comprises the following steps: First, forming a plurality of first terminals on the bonding pads respectively. Then, a plurality of second end points are respectively formed on the pads. A connection terminal is formed by connecting a plurality of conductive materials from the first end points to the second end points, respectively.

In an embodiment of the invention, the electronic component includes a second wafer.

In an embodiment of the invention, the electronic component comprises a memory or a passive component.

In an embodiment of the invention, the flexible reconfigurable wiring film has a thickness of between 25 μm and 150 μm.

In an embodiment of the invention, the connecting terminal includes a first end point, a second end point, and a bonding wire. Each first end point is disposed on a corresponding pad. Each second end point is disposed on a corresponding pad. Each bond wire is connected by a corresponding first end point to a corresponding second end point.

Based on the above, the present invention provides a flexible reconfigurable wiring film on a wafer. On the back side, wherein the flexible reconfigurable film comprises a plurality of reconfigured line patterns arranged in an array and corresponding to a plurality of wafers of the wafer. The dicing process is then performed to separate the wafers from each other and to separate the reconfigured line patterns from each other. In this way, each of the diced wafers has a reconfigured line pattern, and the singulated plurality of wafers are respectively disposed with an interposer having a reconfigured circuit layer for subsequent processing after the wafer is diced according to a conventional process. Component stacking process. In addition, since the thickness of the reconfigured wiring film is thinner than the conventional interposer in the wafer package produced by the process, the present invention can not only greatly simplify the conventional chip packaging process, but also effectively reduce the chip package. thickness.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ Chip package

20‧‧‧ thimble

30‧‧‧ Pick up fixture

100‧‧‧ wafer

110‧‧‧Active surface

120‧‧‧Back

130‧‧‧First chip

134‧‧‧Bumps

200‧‧‧Reconfigure line components

210‧‧‧ base film

220‧‧‧ release film

230‧‧‧Flexible reconfigurable line film

232‧‧‧Flexible substrate

234‧‧‧ patterned metal layer

234a‧‧‧Reconfigured line pattern

234b, 132‧‧‧ solder pads

234c‧‧‧second mat

240‧‧‧Adhesive layer

300‧‧‧ Carrier

310‧‧‧First mat

400‧‧‧Electronic components

410‧‧‧ solder balls

500‧‧‧Connecting terminal

510‧‧‧ first endpoint

520‧‧‧second endpoint

530‧‧‧welding line

D1‧‧‧Top direction

1A to 1G are schematic cross-sectional views showing a process of a wafer packaging process in accordance with an embodiment of the present invention.

2 is a top plan view of the flexible reconfigurable wiring film of FIG. 1G.

1A to 1G are schematic cross-sectional views showing a process of a wafer packaging process in accordance with an embodiment of the present invention. In this embodiment, the wafer packaging process includes the following steps: First, referring to FIG. 1A, a wafer 100 is provided. Wafer 100 has an active surface 110 and a back surface 120 opposite one of active surfaces 110. Wafer 100 includes multiple Each of the first wafers 130 that are connected to each other and arranged in an array is provided with a plurality of pads 132 on the first wafers 130. In a preferred embodiment, the pads 132 of the first wafers 130 may be pre-formed with bumps 134. The pre-formed bumps 134 may be solder balls, stud bumps, gold bumps or copper pillars, and the like. Next, referring to FIG. 1B, a flexible reconfigurable wiring film 230 is disposed on the back surface 120 of the wafer 100. The flexible reconfigurable wiring film 230 includes a plurality of reconfigured wiring patterns 234a disposed corresponding to the pads 132 of the first wafer 130.

Specifically, in the present embodiment, the method of providing the flexible reconfigurable line film 230 on the back surface 120 of the wafer 100 further includes the following steps: First, a reconfigurable line assembly 200 as shown in FIG. 1B is provided. The reconfiguration line assembly 200 includes a base film 210, a release film 220, and a flexible reconfigurable wiring film 230, wherein the release film 220 is disposed on the base film 210 and is flexible Between the line films 230 is disposed. In general, the release film 220 is a film having a separation surface which does not have a viscosity or only a slight viscosity after contact with a specific material under specific conditions. The flexible reconfigurable wiring film 230 includes a flexible substrate 232 and a patterned metal layer 234, wherein the patterned metal layer 234 is located between the release film 220 and the flexible substrate 232, and has the above A plurality of rearrangement line patterns 234a arranged in an array and corresponding to the pads 132 of the first wafer 130.

Next, the flexible substrate 232 and wafer of the line component 200 will be reconfigured The back side 120 of 100 is joined. In detail, the reconfiguration line assembly 200 further includes an adhesive layer 240 that attaches the flexible substrate 232 to the back surface 120 of the wafer 100 through the adhesive layer 240. In this embodiment, the adhesive layer 240 can be, for example, a tape, a B-Stage adhesive or a DAD. Next, referring to FIG. 1C, the wafer 100 and the flexible rearrangement line film 230 are diced to separate the first wafers 130 from each other and to separate the rearrangement line patterns 234a from each other. Next, the release film 220 is separated from each of the first wafers 130 by the characteristics that the release film 220 is easily peeled off to expose the patterned metal layer 234 on each of the first wafers 130. It should be noted that the cutting step of the present embodiment does not cut off the release film 220 and the base film 210 of the reconfiguration line assembly 200.

For example, the method of separating the release film 220 from each of the first wafers 130 may include the steps of: as shown in FIG. 1D, pushing the base film 210 upward through a ejector pin 20 to reduce one of the first wafers 130 and The joint area of the release film 220. In other words, due to the ejector of the ejector pin 20, the base film 210 and the release film 220 are deflected in a pushing direction D1, thereby bringing the contact area of the release film 220 and the patterned metal layer 234 on the first wafer 130. Reduced to approximately equal to the size of the cross-sectional area of the thimble 20. at this time. The first wafer 130 is separated from the release film 220 by, for example, picking up the jig 30 and picking up the first wafer 130 pushed up by the ejector pin 20. In this embodiment, the pick-up jig 30 can be a vacuum nozzle (illustration is merely illustrative).

As described above, as shown in FIG. 1E, the first wafer 130 to be picked up is disposed on the carrier 300, and the active surface 110 of the first wafer 130 is oriented toward the carrier. Device 300. In this embodiment, the first wafer 130 is disposed on the carrier 300 through a flip chip package. In other preferred embodiments, the carrier 300 can be a lead frame, a substrate, a flexible board (such as a film), or a printed circuit board or the like. Next, as shown in FIG. 1F, the electronic component 400 is placed on the relocation line pattern 234a. In this embodiment, the electronic component 400 can be a second wafer stacked on the first wafer 130. In other embodiments of the present invention, the electronic component 400 may be other electronic components such as a memory, a passive component, or a heat sink. The invention does not limit the type of the electronic component 400. The electronic component 400 includes a plurality of solder balls 410 that are respectively bonded to the plurality of pads 234b on the rearrangement line pattern 234a via the solder balls 410.

2 is a top plan view of the flexible reconfigurable wiring film of FIG. 1G. Next, referring to FIG. 1G and FIG. 2 simultaneously, the electronic component 400 and the carrier 300 are electrically connected through the plurality of connection terminals 500. In this embodiment, the carrier 300 includes a plurality of first pads 310, and the reconfiguration line pattern 234a includes a plurality of pads 234b and a plurality of second pads 234c, as shown in FIG. 1G and FIG. Used to bond with the solder ball 410. The second pad 234c is for engaging with the connection terminal 500. The electronic component 400 is electrically connected to the carrier 300 through an electrical connection path formed by the solder ball 410, the solder pad 234b, the second pad 234c, the connection terminal 500, and the first pad 310. Specifically, the connection terminal 500 is electrically connected to the electronic component 400 and the carrier 300 in a reverse wire-bonding manner. Further, the embodiment can be, for example, through a wire bonding machine on the carrier. A plurality of first end points 510 are formed on the first pads 310 of the 300, and then the second wire pad 234c is used by the wire bonding machine. Forming a plurality of second end points 520, moving the wire bonding machine from the first end point 510 to the second end point 520, and the wire bonding machine stably releases a conductive material during the movement to form a connection first end point 510 and the second end point 520 of the bonding wire 530, the connecting terminal 500 is composed of the first end point 510, the second end point 520 and the bonding wire 530. Preferably, the bonding wire 530 material can be selected from copper and silver. , gold or its alloys. In this way, the electronic component 400 and the carrier 300 can be electrically connected in a reverse wire bonding manner. This manner of reverse wire bonding can reduce the effect of the wire height on the thickness of the wafer package 10, thereby further reducing the thickness of the chip package 10.

As such, in the present embodiment, a flexible reconfigurable wiring film 230 is disposed on the back surface 120 of the wafer 100. The flexible reconfigurable film includes a plurality of arrays arranged and corresponding to the plurality of wafers 130 of the wafer 100. The line pattern 234a is disposed, and then a dicing process is performed to separate the wafers 130 from each other and to separate the reconfigured line patterns 234a from each other. In this way, each of the diced wafers 130 after the dicing has the reconfigured circuit pattern 234a, and the singulated wafers are disposed one by one after the wafer dicing process. Intermediary layer for subsequent component stacking processes. Therefore, this embodiment can omit the conventional interposer process, and can greatly simplify the complicated process of the chip package 10. Further, since the thickness of the flexible rearrangement line film 230 is thinner than that of the conventional interposer, the present embodiment can replace the interposer with the flexible rearrangement line film 230, and the thickness of the wafer package 10 can be effectively reduced.

The wafer encapsulation process as described above can produce a wafer package as shown in FIG. 1G. Install 10. In the present embodiment, the chip package 10 includes a carrier 300, a first wafer 130, a flexible reconfigurable line pattern 234a, an electronic component 400, and a plurality of connection terminals 500. It is to be noted that the same reference numerals are used to designate the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted part, reference may be made to the foregoing embodiment, and the description is not repeated herein. The first wafer 130 is disposed on the carrier 300 and has an active surface 110 and a back surface 120 opposite the active surface 110. The active surface 110 faces the carrier 300. The flexible reconfiguration line pattern 234a is disposed on the back surface 120 of the first wafer 130, and the edge of the flexible reconfiguration line pattern 234a is substantially aligned with the edge of the first wafer 130. The thickness of the flexible reconfigurable wiring film 230 is between 25 μm and 150 μm. The electronic component 400 is disposed on the flexible reconfiguration line pattern 234a. The connection terminals 500 are electrically connected to the electronic component 400 and the carrier 300, respectively. In this embodiment, the connection terminal 500 is electrically connected to the electronic component 400 and the carrier 300 by means of reverse wire bonding. In more detail, the connection terminal 500 includes a first end point 510 and a second end point. 520 and a bonding wire 530. Each of the first end points 510 is disposed on the corresponding second pad 234c. Each of the second end points 520 is disposed on the corresponding first pad 310. Each bond wire 530 is coupled to a corresponding second end point 520 by a corresponding first end point 510. This manner of reverse wire bonding can reduce the effect of the wire height on the thickness of the wafer package 10, thereby further reducing the thickness of the chip package 10.

In summary, the present invention sets a flexible reconfigurable line film on the crystal On the back side of the circle, wherein the flexible reconfigurable film comprises a plurality of reconfigured line patterns arranged in an array and corresponding to a plurality of wafers of the wafer. The dicing process is then performed to separate the wafers from each other and to separate the reconfigured line patterns from each other. In this way, each of the diced wafers has a reconfigured line pattern, and the singulated plurality of wafers are respectively disposed with an interposer having a reconfigured circuit layer for subsequent processing after the wafer is diced according to a conventional process. Component stacking process. Therefore, the present invention can omit the process of the interposer, and can greatly simplify the complicated copying process of the conventional chip package. In addition, in the wafer package produced by the process, since the thickness of the re-arranged line film is thinner than the conventional interposer, the present invention can effectively reduce the chip package by replacing the interposer with a flexible reconfigurable line film. thickness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ Chip package

130‧‧‧First chip

230‧‧‧Flexible reconfigurable line film

232‧‧‧Flexible substrate

234a‧‧‧Reconfigured line pattern

234b‧‧‧ solder pads

234c‧‧‧second mat

300‧‧‧ Carrier

310‧‧‧ pads

400‧‧‧Electronic components

410‧‧‧ solder balls

500‧‧‧Connecting terminal

510‧‧‧ first endpoint

520‧‧‧second endpoint

530‧‧‧welding line

Claims (12)

A wafer packaging process includes: providing a wafer having an active surface and a back surface opposite to the active surface, wherein the wafer includes a plurality of first wafers connected to each other and arranged in an array; Reconfiguring the line film on the back side of the wafer, wherein the flexible reconfigurable line film comprises a plurality of array arrangements and corresponding to the reconfigured line patterns of the first wafers, wherein the flexible reconfiguration is set The step of the line film on the back side of the wafer further includes: providing a reconfiguration line assembly including a base film, a release film, and the flexible reconfiguration a wiring film disposed between the base film and the flexible reconfigurable wiring film, the flexible reconfigurable wiring film comprising a flexible substrate and a patterned metal layer, the patterned metal a layer between the release film and the flexible substrate; bonding the flexible substrate of the reconfigurable circuit assembly to the back surface of the wafer; cutting the wafer and the flexible substrate; as well as Separating the release film from each of the first wafers to expose the patterned metal layer on each of the first wafers; cutting the wafers and the flexible reconfigurable wiring film to cause the first wafers to be in contact with each other Separating and separating the reconfigured line patterns from each other; disposing one of the first wafers on a carrier and directing the active surface of the first wafer toward the carrier; and disposing an electronic component on the first wafer And reconfiguring the line pattern; and electrically connecting the electronic component and the carrier through the plurality of connection terminals. The wafer packaging process of claim 1, wherein the flexible reconfigurable wiring film is attached to the back surface of the wafer by an adhesive layer. The wafer packaging process of claim 1, wherein the release film is The step of separating from each of the first wafers includes: pushing the base film through a thimble to reduce a bonding area of one of the first wafers with the release film; and picking up the first wafer pushed by the ejector. The wafer packaging process of claim 1, wherein the first wafer is disposed on the carrier by flip chip bonding. The wafer packaging process of claim 1, wherein the electronic component comprises a plurality of solder balls, and the reconfigurable circuit pattern comprises a plurality of pads for respectively bonding with the solder balls, and the carrier comprises a plurality of The electronic component is electrically connected to the carrier through the solder balls, the solder pads, the connecting terminals, and the pads. The chip packaging process of claim 5, wherein the step of electrically connecting the electronic component and the carrier through the plurality of connection terminals comprises: forming a plurality of first end points on the pads respectively; respectively forming The plurality of second terminals are on the pads; and the plurality of conductive materials are respectively connected to the second terminals by the first end points to form the connection terminals. The wafer packaging process of claim 1, wherein the electronic component comprises a second wafer, a memory or a passive component. A chip package comprising: a carrier; a first wafer disposed on the carrier and having an active surface and a back surface opposite the active surface, the active surface facing the carrier; a flexible reconfigurable line a pattern disposed on the back surface of the first wafer, the edge of the flexible reconfigurable line pattern being substantially aligned with an edge of the first wafer, wherein the flexible reconfigurable line pattern comprises a flexible base And a patterned metal layer disposed between the patterned metal layer and the first wafer; An electronic component disposed on the flexible reconfiguration circuit pattern; and a plurality of connection terminals electrically connecting the electronic component and the carrier, respectively. The wafer package of claim 8, wherein the flexible reconfigurable wiring film has a thickness of between 25 μm and 150 μm. The chip package of claim 8, wherein the electronic component further comprises a plurality of solder balls, and the reconfigurable circuit pattern comprises a plurality of solder pads respectively bonded to the solder balls, the carrier further comprising a plurality of connections The electronic component is electrically connected to the carrier through the solder balls, the pads, the connecting terminals, and the pads. The chip package of claim 10, wherein each of the connection terminals comprises a first end point, a second end point, and a bonding wire, each of the first end points being disposed on a corresponding pad, each of the The second end point is disposed on the corresponding pad, and each of the bonding wires is connected to the corresponding second end point by the corresponding first end point. The wafer package of claim 8, wherein the electronic component comprises a second wafer, a memory or a passive component.