JP4183070B2 - Multi-chip module - Google Patents
Multi-chip module Download PDFInfo
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- JP4183070B2 JP4183070B2 JP2003011214A JP2003011214A JP4183070B2 JP 4183070 B2 JP4183070 B2 JP 4183070B2 JP 2003011214 A JP2003011214 A JP 2003011214A JP 2003011214 A JP2003011214 A JP 2003011214A JP 4183070 B2 JP4183070 B2 JP 4183070B2
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- semiconductor element
- connection terminal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】
【発明の属する技術分野】
複数の半導体素子を接続して構成するマルチチップパッケージに係わり、特に半導体素子およびマルチチップパッケージの構造に関する。
【０００２】
【従来の技術】
電子機器の高性能化、小型化に伴い一つのパッケージ内に複数の半導体チップを配置してマルチチップパッケージとすることにより、半導体装置の高性能化と小型化とが図れている。そして、マルチチップパッケージには、複数の半導体素子を実装基板上に平面に並べたタイプ（例えば、特許文献１参照。）、複数の半導体素子を厚み方向（実装基板に対して垂直方向）に積層するタイプがある。
【０００３】
平面に並べたマルチチップパッケージは、広い実装面積を必要とするため、電子機器の小型化への寄与には限界がある。
垂直方向に積層したマルチチップパッケージには、複数の半導体素子の外形寸法の大きさにしたがってピラミッド状に積層し、各半導体チップの端子電極をワイヤボンディングによつて接続する構造や、同一形状の半導体素子の表裏を配線して素子間をバンプ接続する構造のものがある。
【０００４】
【特許文献１】
特開平８−８３９２号公報
【０００５】
【発明が解決しようとする課題】
ところが、従来構造のマルチチップパッケージでは、積層する順位がチップサイズにより規制されてしまい、積層の自由度が少なく、また、チップ間の端子電極の接合にワイヤボンディングを利用して行うため端子間の距離が一定せず、ボンディング長さに起因する電気特性の劣化が生じる問題がある（図１１参照。図中、１は半導体素子、１３は実装基板、１４はボンディングワイヤを示す。）。
【０００６】
また、積層型のマルチチップパッケージでは、横方向（水平方向）への展開が困難であった（図１２参照。図中、１は半導体素子、１１はハンダバンプ、１３は実装基板、１５はコンタクト用のスルーホールを示す。）。
【０００７】
【課題を解決するための手段】
第一の発明は、半導体素子の周縁部を素子部の基板厚さよりも薄く加工し、前記周縁部上に接続端子を形成し、素子部と配線する。
異なる半導体素子の前記接続端子同士を対面接続すると、接続端子は素子部の基板厚さよりも薄く形成されているので、貼り合わせ後の厚さは素子部の基板厚さの2倍より薄くなる。例えば、周縁部の基板厚さを素子部の基板の略半分に形成した場合、貼り合わせ後の厚さは略素子部の基板厚さと同じになる。
【０００８】
第二の発明は、前記半導体素子を複数用い、実装基板上で互いに対面するように接続する。
複数の半導体素子を前記接続端子で次々と貼り合わせて、水平方向に１列で半導体素子が貼り合わされて行き、貼り合わせ後のマルチチップパッケージの厚みは半導体素子の厚さである。
【０００９】
第三の発明は、半導体素子が、素子部と同一平面上に設けられた第１の接続端子と、周縁部の表面に設けられた第２の接続端子と、周縁部の裏面に設けられた第３の接続端子からなり、第２の接続端子と第３の接続端子が半導体基板の側面を経由して配線されたものである。
接続端子を３箇所有することにより、横隣、上、下の各半導体素子と接続が可能となる。
【００１０】
第四の発明は、半導体素子が、素子部と同一平面上に設けられた第１の接続端子と、周縁部の表面に設けられた第２の接続端子と、周縁部の裏面に設けられた第３の接続端子からなり、第２の接続端子と第３の接続端子が周縁部の半導体基板を貫通するスルーホールで配線されたものである。
接続端子を３箇所有することにより、横隣、上、下の各半導体素子と接続が可能となる。
【００１１】
第五の発明は、前記第２の接続端子同士を対面接続して、横隣の半導体素子と貼り合わせ、上下の半導体素子との貼り合わせには、第１の接続端子あるいは第３の接続端子同士を対面接続あるいは背面接続する。
前記第２の接続端子同士を対面接続すると、第二の発明の様に、水平方向１列に半導体素子を並べられる。水平方向に並んだ１つの半導体素子の列と、上下を逆にして貼り合わせた別の一つの半導体の列を作り、これを先に作った一つの半導体素子の列の上に重ねて貼り合わせる。この時、第３の接続端子同士、あるいは第１の接続端子同士が背面あるいは対面で接続することになる。同様にして水平方向に並んだ一つの半導体素子の列を積み上げて行くと、水平方向の列と垂直方向の列からなる、半導体素子の垂直二次元配列からなるマルチチップパッケージが得られる。
【００１２】
【発明の実施の形態】
（実施例１）
本発明の第一の実施形態を示す。図１は、半導体素子の構造を示す図である。上図は半導体素子の斜視図、下図は断面図である。図中、１は半導体素子、２は素子部、３は周縁部、４は接続端子、５は絶縁膜、６は配線、７はコンタクトホール、８は内部配線パッドである。
【００１３】
以下に、本発明の半導体素子の作製方法について述べる。半導体素子１の内部配線パッド８および素子部２に回路機能を作り込んだ厚さ約７００μmのウェハを用い、
１−１）厚さ４００μmまで裏面研削する。（必要に応じて、バックコンタクトを形成する。）
１−２）先端断面が台形形状のブレードを有するダイサで、半導体素子の周縁部３を深さ２００μm切削する。
１−３）ウェハ全面にポリイミド樹脂を塗布し、キュアする。
１−４）内部配線パッド部８のポリイミド（絶縁膜５）にコンタクトホール７を形成する。
１−５）Ａｌを蒸着して、周縁部３の接続端子４−２と配線６を形成する。
１−６）周縁部３の接続端子４−２に（必要に応じ、コンタクトホール上の接続端子にも）ハンダ層９を形成する。（ボンディング用の端子とする場合は、ハンダ層を形成しない。）
１−７）ダイサでチップ切断する。
【００１４】
図２は、図１に示す半導体素子Ａ，Ｂ，Ｃの３つを平面的に配置したものである。図中、１１はハンダバンプ、１２はメタルパターン、１３は実装基板、１４はボンディングワイヤである。上図は実装基板にボンディングする場合を示している。半導体素子Ａ，Ｃの素子部面を上向きに、半導体素子Ｂの素子部面を下向きにし、各半導体素子の周縁部の接続端子４−２同士をその上に設けたハンダ層９で接続して実装基板上に接着剤で固定する。そして、半導体素子Ａ，Ｃの接続端子４−２と実装基板のメタルパターンをボンディングする。
【００１５】
下図は、上述したと同様に半導体素子Ａ，Ｂ，Ｃを各々その周縁部の接続端子４−２で互いに接続する。半導体素子Ａの左側、Ｃの右側のコンタクトホール７の上に設けた接続端子４−１に周縁部３の接続端子４−２に設けたハンダ層より融点の低いハンダ層を設ける。接続を完了した半導体素子Ａ，Ｂ，Ｃが一体化したものを上下逆にして、接続端子４−１を実装基板上１３に設けた融点の低いハンダバンプ上に合わせて載せ、融着してマルチチップパッケージとする。
（実施例２）
次に、本発明の第二の実施形態を示す。図３は半導体素子の構造を示す。周縁部が略２００μm素子部よりも低く形成された一つの半導体素子１に対し、
２−１）素子全面にポリイミド樹脂５を塗布し、キュアする。
２−２）内部配線パッド部のポリイミドにコンタクトホール７を形成する。
２−３）全面にＡｌを蒸着する。
２−４）内部配線パッド部の上の接続端子４−１、周縁部の表面の接続端子４−２、その裏面の接続端子４−３と配線をエッチングで形成する。
２−５）各接続端子上にハンダ層９を形成する。
２−６）ダイサでチップ切断する。
【００１６】
本半導体素子を用いて、立体的に複数の半導体素子を実装する例を図４に示す。図中、番号および名称は図２で用いたものと同じである。第一の実施形態で示したように、平面的に複数の半導体素子Ａ，Ｂ，Ｃを接続する。そして、この平面的に配列されたものを、上下反転して積み上げ、さらに、もう一度上下反転したものを積み上げるようにして、多段に積層することが可能である。図４から判るように、水平方向にはＡ，Ｂ，Ｃの半導体素子が、垂直方向には４段半導体素子を積み重ねた立体的に配置されたマルチチップパッケージを作製できる。
（実施例３）
次に、本発明の第三の実施形態を示す。図５は半導体素子の構造を示す。第一の実施形態で述べたのと同様に、１−２）の工程まで進め、次に、
３−３）周縁部の接続端子４−２を形成する位置に異方性のドライエッチングによりシリコン基板に約８０μmのスルーホール１５を形成する。
３−４）ウェハの表裏の全面にポリイミド樹脂５を塗布する。（スルーホールはポリイミド樹脂で埋め込まれる。）
３−５）埋め込まれたポリイミド樹脂をレーザで焼き切り、側壁にポリイミドを残し、中央に再びスルーホールを形成する。
３−６）スルーホールを埋め込み、スルーホールの周囲を銅メッキする。
３−７）表裏面にＡｌを蒸着する。
３−８）コンタクトホール上の接続端子４−１、周縁部の接続端子４−２、配線パターンのエッチングを行なう。また、裏面の接続端子４−３のパターンをエッチング形成する。
３−９）各接続端子上にハンダ層９を形成する。
３−１０）ダイサでチップ切断する。
【００１７】
本半導体素子を用いて、立体的に複数の半導体素子を実装する例を図６に示す。図中の番号および名称は図２で用いたものと同じである。組み上げ方法は実施例２と同様である。
（変形例１）
本発明の請求項３に記載する半導体素子は、素子部に隣接した周縁部を掘り下げた構造となっているが、逆に裏面側から掘り下げる構造としても良い。図７にその構造を示す。この構造により、半導体素子面積に対する素子部の面積比率を大きくできる。
（変形例２）
半導体素子の周辺部の４辺に段差を設け、更に、半導体素子の４隅を切断する。具体的には、図８に示す様な形状となる。
（変形例３）
図８に示す半導体素子を用いて、平面上に複数の半導体素子を配置する。その実装例を図９に示す。
（変形例４）
図９に示す平面的に配列した複数の半導体素子と、前記複数の半導体素子を上下反転して配置した複数の半導体素子とを上下に重ね合わせる。更に、同様の上下反転して配置した複数の半導体素子を重ね合わせることによって三次元的に配列のマルチチップパッケージが得られる。その構造を図１０に示す。
【００１８】
以上、本発明の内容をまとめると、
（付記１）回路機能を形成した素子部と外部接続のための接続端子を形成した周縁部を有する半導体素子において、周縁部が素子部の基板厚さよりも薄く形成され、かつ素子部と接続端子を配線したことを特徴とする半導体素子。
（付記２）実装基板上に、付記１記載の半導体素子を対面接続して水平方向に一列に配置したことを特徴とするマルチチップパッケージ。
【００１９】
（付記３）半導体素子の素子部と同一平面上に第１の接続端子を設け、周縁部に第２の接続端子を設け、前記第１および第２の接続端子を経由して前記半導体素子の側面から裏面に設けた第３の接続端子へ配線されていることを特徴とする付記１記載の半導体素子。
（付記４）半導体素子の素子部と同一平面上に第１の接続端子を設け、周縁部に第２の接続端子を設け、前記第１および第２の接続端子を経由して前記半導体素子の基板に設けたスルーホールから裏面に設けた第３の接続端子へ配線されていることを特徴とする付記１記載の半導体素子。
【００２０】
（付記５）付記３または４記載の複数の半導体素子を表面に設けた第２の接続端子同士で対面接続して平面的に配置し、さらに裏面に設けた第３および表面の第１の接続端子同士で背面および対面接続して、前記半導体素子を水平方向の列と垂直方向の列からなる垂直二次元配置したことを特徴とするマルチチップパッケージ。
【００２１】
（付記６）半導体素子の周辺部の４辺の基板厚さを素子部の基板厚さよりも薄く形成し、かつ、半導体素子の４隅を素子部の外側でかつ段差部より内側で切断したことを特徴とする付記３または４記載の半導体素子。
（付記７）付記６記載の半導体素子を複数用い、交互に上下逆転して前記第２の接続端子で貼り合わせ、二次元平面に配列したことを特徴とするマルチチップパッケージ。
【００２２】
（付記８）付記６記載の二次元平面に配列された半導体素子と、上下が逆転して二次元平面に配列された半導体素子を積み重ね、前記第１の接続端子または第３の接続端子で貼り合わせて三次元に配列したことを特徴とするマルチチップパッケージ。
（付記９）半導体素子の接続端子にはハンダ層が設けられ、前記第２の接続端子のハンダの融点が、前記第１および３の接続端子のハンダ融点よりも高いことを特徴とする付記３、４、６記載の半導体素子。
【００２３】
【発明の効果】
本発明の半導体素子を平面的に配列したマルチチップパッケージは、半導体素子の基板厚さよりも薄く形成した段差部の接続端子同士で貼り合わせるため、半導体素子２つ分のより薄く実装できる。
半導体素子の４辺に段差を設け、４隅を切断したことによって、二次元平面に半導体素子を配置でき、さらに、それを積み重ねることで、三次元的な配置も可能である。
【００２４】
この結果、従来には無い実装密度の高いマルチチップパッケージを作製できる。
【図面の簡単な説明】
【図１】 本発明の半導体素子の構造を示す図
【図２】 半導体素子を水平一列に配列したマルチチップパッケージを示す図
【図３】 ３つの接続端子を有し、半導体素子の側面を配線した本発明の半導体素子の構造を示す図
【図４】 半導体素子を水平方向と垂直方向の垂直二次元に配置したマルチチップパッケージの構造を示す図
【図５】 ３つの接続端子を有し、半導体素子の基板に設けたスルーホールを経由して配線した本発明の半導体素子の構造を示す図
【図６】 半導体素子を水平方向と垂直方向の垂直二次元に配置したマルチチップパッケージの構造を示す図
【図７】 半導体素子の裏面側に段差を設けた本発明の半導体素子の変形例を示す図
【図８】 四辺に段差を設け、４隅を切り取った半導体素子の構造を示す図
【図９】 半導体素子を二次元平面に配列したマルチチップパッケージの構造を示す図
【図１０】 半導体素子を三次元配列したマルチチップパッケージの構造を示す図
【図１１】 異種半導体素子を積み上げ実装した従来例
【図１２】 同種半導体素子を積み上げ実装した従来例
【符号の説明】
１ 半導体素子
２ 素子部
３ 周縁部
４ 接続端子
５ 絶縁膜
６ 配線
７ コンタクトホール
８ 内部配線パッド
９ ハンダ層
１１ ハンダバンプ
１２ メタルパターン
１３ 実装基板
１４ ボンディングワイヤ
１５ コンタクト用のスルーホール[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multichip package configured by connecting a plurality of semiconductor elements, and more particularly to a structure of a semiconductor element and a multichip package.
[0002]
[Prior art]
With the increase in performance and size of electronic devices, a plurality of semiconductor chips are arranged in one package to form a multi-chip package, thereby improving the performance and size of the semiconductor device. In the multichip package, a plurality of semiconductor elements are arranged in a plane on a mounting substrate (see, for example, Patent Document 1), and a plurality of semiconductor elements are stacked in a thickness direction (perpendicular to the mounting substrate). There is a type to do.
[0003]
Multi-chip packages arranged in a plane require a large mounting area, and thus there is a limit to the contribution to downsizing of electronic devices.
Multi-chip packages stacked in the vertical direction are stacked in a pyramid shape according to the size of the external dimensions of a plurality of semiconductor elements, and the terminal electrodes of each semiconductor chip are connected by wire bonding, or semiconductors of the same shape There is a structure in which the front and back of the element are wired and the elements are bump-connected.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 8-8392
[Problems to be solved by the invention]
However, in the multi-chip package having the conventional structure, the stacking order is restricted by the chip size, and the degree of freedom of stacking is small. Further, since the bonding of the terminal electrodes between the chips is performed by using wire bonding, the terminals are not connected. There is a problem in that the distance is not constant and electrical characteristics are deteriorated due to the bonding length (see FIG. 11. In the figure, 1 is a semiconductor element, 13 is a mounting substrate, and 14 is a bonding wire).
[0006]
Further, in the multi-chip package of the stacked type, it is difficult to develop in the lateral direction (horizontal direction) (see FIG. 12. In the figure, 1 is a semiconductor element, 11 is a solder bump, 13 is a mounting substrate, and 15 is for contact. Shows a through hole.)
[0007]
[Means for Solving the Problems]
In the first invention, the peripheral portion of the semiconductor element is processed to be thinner than the substrate thickness of the element portion, a connection terminal is formed on the peripheral portion, and the element portion is wired.
When the connection terminals of different semiconductor elements are face-to-face connected, the connection terminals are formed thinner than the substrate thickness of the element portion, so that the thickness after bonding is less than twice the substrate thickness of the element portion. For example, when the substrate thickness of the peripheral portion is formed to be approximately half of the substrate of the element portion, the thickness after bonding is substantially the same as the substrate thickness of the element portion.
[0008]
A second invention uses a plurality of the semiconductor elements and connects them so as to face each other on a mounting substrate.
A plurality of semiconductor elements are bonded together one after another at the connection terminals, and the semiconductor elements are bonded in a row in the horizontal direction, and the thickness of the multi-chip package after the bonding is the thickness of the semiconductor elements.
[0009]
According to a third aspect of the invention, the semiconductor element is provided on the first connection terminal provided on the same plane as the element part, the second connection terminal provided on the surface of the peripheral part, and the back surface of the peripheral part. It consists of a third connection terminal, and the second connection terminal and the third connection terminal are wired via the side surface of the semiconductor substrate.
By having three connection terminals, it is possible to connect to the semiconductor elements on the side, top, and bottom.
[0010]
In a fourth aspect of the invention, the semiconductor element is provided on the first connection terminal provided on the same plane as the element part, the second connection terminal provided on the surface of the peripheral part, and the back surface of the peripheral part. It consists of a third connection terminal, and the second connection terminal and the third connection terminal are wired by through-holes penetrating the peripheral semiconductor substrate.
By having three connection terminals, it is possible to connect to the semiconductor elements on the side, top, and bottom.
[0011]
According to a fifth aspect of the present invention, the second connection terminals are connected face-to-face and bonded to the adjacent semiconductor element, and the first connection terminal or the third connection terminal is used for bonding to the upper and lower semiconductor elements. Connect each other face-to-face or back.
When the second connection terminals are connected face-to-face, the semiconductor elements are arranged in one horizontal row as in the second invention. Make a row of semiconductor elements aligned in the horizontal direction and another row of semiconductors pasted upside down, and stack them on top of the one row of semiconductor elements created earlier. . At this time, the third connection terminals or the first connection terminals are connected to each other on the back surface or the face-to-face. Similarly, by stacking one row of semiconductor elements arranged in the horizontal direction, a multi-chip package comprising a vertical two-dimensional array of semiconductor elements, which is composed of a horizontal row and a vertical row, is obtained.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(Example 1)
1 shows a first embodiment of the present invention. FIG. 1 is a diagram showing a structure of a semiconductor element. The upper figure is a perspective view of the semiconductor element, and the lower figure is a sectional view. In the figure, 1 is a semiconductor element, 2 is an element portion, 3 is a peripheral portion, 4 is a connection terminal, 5 is an insulating film, 6 is a wiring, 7 is a contact hole, and 8 is an internal wiring pad.
[0013]
Hereinafter, a method for manufacturing the semiconductor element of the present invention will be described. Using a wafer having a thickness of about 700 μm in which a circuit function is built in the
1-1) The back surface is ground to a thickness of 400 μm. (If necessary, back contact is formed.)
1-2) A
1-3) A polyimide resin is applied to the entire surface of the wafer and cured.
1-4) A
1-5) Al is vapor-deposited to form the connection terminals 4-2 and
1-6) The
1-7) The chip is cut with a dicer.
[0014]
FIG. 2 is a plan view of three semiconductor elements A, B, and C shown in FIG. In the figure, 11 is a solder bump, 12 is a metal pattern, 13 is a mounting substrate, and 14 is a bonding wire. The upper figure shows the case of bonding to the mounting substrate. The element surfaces of the semiconductor elements A and C are faced upward, the element part face of the semiconductor element B is faced down, and the connection terminals 4-2 at the periphery of each semiconductor element are connected to each other by a
[0015]
In the figure below, the semiconductor elements A, B, and C are connected to each other at the peripheral connection terminals 4-2 in the same manner as described above. A solder layer having a melting point lower than that of the solder layer provided on the connection terminal 4-2 of the
(Example 2)
Next, a second embodiment of the present invention is shown. FIG. 3 shows the structure of the semiconductor element. For one
2-1) A
2-2) A
2-3) Al is vapor-deposited on the entire surface.
2-4) The connection terminal 4-1 on the internal wiring pad portion, the connection terminal 4-2 on the front surface of the peripheral portion, and the connection terminal 4-3 on the back surface thereof are formed by etching.
2-5) A
2-6) Cutting the chip with a dicer.
[0016]
FIG. 4 shows an example in which a plurality of semiconductor elements are mounted three-dimensionally using this semiconductor element. In the figure, the numbers and names are the same as those used in FIG. As shown in the first embodiment, a plurality of semiconductor elements A, B, and C are connected in a plane. Then, it is possible to stack the multi-layered structure in such a manner that the two-dimensionally arranged ones are turned upside down and stacked, and the ones turned upside down once again are stacked. As can be seen from FIG. 4, a multichip package in which A, B, and C semiconductor elements are horizontally arranged and four-stage semiconductor elements are stacked in the vertical direction can be manufactured.
(Example 3)
Next, a third embodiment of the present invention will be shown. FIG. 5 shows the structure of the semiconductor element. In the same manner as described in the first embodiment, the process proceeds to step 1-2).
3-3) A through
3-4) The
3-5) The embedded polyimide resin is burned off with a laser, leaving the polyimide on the side wall, and forming a through hole in the center again.
3-6) The through hole is filled and the periphery of the through hole is plated with copper.
3-7) Al is vapor-deposited on the front and back surfaces.
3-8) Etching of the connection terminal 4-1 on the contact hole, the connection terminal 4-2 on the periphery, and the wiring pattern. Further, the pattern of the connection terminal 4-3 on the back surface is formed by etching.
3-9) A
3-10) Cutting the chip with a dicer.
[0017]
An example of mounting a plurality of semiconductor elements in three dimensions using this semiconductor element is shown in FIG. The numbers and names in the figure are the same as those used in FIG. The assembly method is the same as in the second embodiment.
(Modification 1)
The semiconductor element according to
(Modification 2)
Steps are provided on the four sides of the periphery of the semiconductor element, and four corners of the semiconductor element are cut. Specifically, the shape is as shown in FIG.
(Modification 3)
A plurality of semiconductor elements are arranged on a plane using the semiconductor element shown in FIG. An example of the implementation is shown in FIG.
(Modification 4)
A plurality of semiconductor elements arranged in a plan view shown in FIG. 9 and a plurality of semiconductor elements in which the plurality of semiconductor elements are arranged upside down are superposed one above the other. Furthermore, a multi-chip package having a three-dimensional arrangement can be obtained by superposing a plurality of semiconductor elements arranged in the same manner upside down. The structure is shown in FIG.
[0018]
The contents of the present invention are summarized as follows.
(Supplementary note 1) In a semiconductor element having an element portion in which a circuit function is formed and a peripheral portion in which a connection terminal for external connection is formed, the peripheral portion is formed thinner than the substrate thickness of the element portion, and the element portion and the connection terminal A semiconductor element characterized by wiring.
(Appendix 2) A multi-chip package, wherein the semiconductor elements described in
[0019]
(Supplementary Note 3) A first connection terminal is provided on the same plane as the element portion of the semiconductor element, a second connection terminal is provided at the peripheral portion, and the semiconductor element is connected to the semiconductor element via the first and second connection terminals. The semiconductor device according to
(Supplementary Note 4) A first connection terminal is provided on the same plane as the element portion of the semiconductor element, a second connection terminal is provided at the peripheral portion, and the semiconductor element is connected to the semiconductor element via the first and second connection terminals. The semiconductor element according to
[0020]
(Supplementary Note 5) A plurality of semiconductor elements described in
[0021]
(Appendix 6) The thickness of the substrate on the four sides of the peripheral portion of the semiconductor element is formed thinner than the substrate thickness of the element portion, and the four corners of the semiconductor element are cut outside the element portion and inside the step portion. The semiconductor element according to
(Supplementary note 7) A multichip package comprising a plurality of semiconductor elements according to
[0022]
(Appendix 8) The semiconductor elements arranged in the two-dimensional plane according to
(Supplementary Note 9) The connection terminal of the semiconductor element is provided with a solder layer, and the melting point of the solder of the second connection terminal is higher than the solder melting point of the first and third connection terminals. 4. The semiconductor device according to 4, 6.
[0023]
【The invention's effect】
Since the multichip package in which the semiconductor elements of the present invention are arranged in a plane is bonded to the connection terminals of the step portions formed thinner than the substrate thickness of the semiconductor elements, it can be mounted thinner than two semiconductor elements.
By providing steps on four sides of the semiconductor element and cutting the four corners, the semiconductor element can be arranged on a two-dimensional plane, and further, three-dimensional arrangement is possible by stacking them.
[0024]
As a result, a multi-chip package with a high mounting density that is not available in the past can be manufactured.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a semiconductor device according to the present invention. FIG. 2 is a diagram showing a multi-chip package in which semiconductor devices are arranged in a horizontal row. FIG. FIG. 4 is a diagram showing the structure of a semiconductor device according to the present invention. FIG. 4 is a diagram showing the structure of a multichip package in which semiconductor devices are arranged two-dimensionally in a horizontal direction and a vertical direction. FIG. The figure which shows the structure of the semiconductor element of this invention wired via the through hole provided in the board | substrate of a semiconductor element. FIG. 6: The structure of the multichip package which has arrange | positioned the semiconductor element in the vertical two dimensions of a horizontal direction and a perpendicular direction. FIG. 7 is a diagram showing a modification of the semiconductor element of the present invention in which a step is provided on the back side of the semiconductor element. FIG. 8 is a diagram showing a structure of the semiconductor element in which a step is provided on four sides and four corners are cut off. Fig. 9 Semiconductor element FIG. 10 is a diagram showing the structure of a multi-chip package in which semiconductor elements are arranged in a two-dimensional plane. FIG. 10 is a diagram showing the structure of a multi-chip package in which semiconductor elements are arranged in three dimensions. ] Conventional example of stacking and mounting the same kind of semiconductor elements [Explanation of symbols]
DESCRIPTION OF
Claims (4)
前記半導体素子を構成する基板は、中央部に平坦な平坦部及び前記平坦部より低く形成された平坦面からなる周縁部を有する主面と、平坦な基板裏面とを有し、
前記半導体素子は、前記平坦部に形成された外部接続用の第１の接続端子と、前記第１の接続端子と導通する前記周縁部に形成された外部接続用の第２の接続端子とを有し、
前記実装基板上に、前記主面を上向きに間隔を設けて一列に搭載された複数の第１の前記半導体素子と、
隣接する第１の前記半導体素子の前記第２の接続端子間を架橋するように第１の前記半導体素子間に配置され、前記第２の接続端子を介して前記隣接する第１の前記半導体素子と互いに前記周縁部を対向させて接続された第２の前記半導体素子とを有することを特徴とするマルチチップモジュール。In a multichip module in which a plurality of semiconductor elements are mounted on a mounting board,
The substrate constituting the semiconductor element has a main surface having a flat portion at the center and a peripheral portion made of a flat surface formed lower than the flat portion, and a flat substrate back surface,
The semiconductor element includes a first connection terminal for external connection formed in the flat portion, and a second connection terminal for external connection formed in the peripheral portion that is electrically connected to the first connection terminal. Have
A plurality of the first semiconductor elements mounted in a row on the mounting substrate with the main surface facing upwards; and
The first semiconductor element that is disposed between the first semiconductor elements so as to bridge between the second connection terminals of the adjacent first semiconductor elements, and that is adjacent to the first semiconductor element via the second connection terminals. And a second semiconductor element connected with the peripheral edge facing each other. A multi-chip module comprising:
前記半導体素子を構成する基板は、中央部に平坦な平坦部及び前記平坦部より低く形成された平坦面からなる周縁部を有する主面と、平坦な基板裏面とを有し、
前記半導体素子は、前記平坦部に形成された外部接続用の第１の接続端子と、前記第１の接続端子と導通する前記周縁部に形成された外部接続用の第２の接続端子と、前記第２の接続端子と導通する前記基板裏面に形成された外部接続用の第３の接続端子とを有し、
前記実装基板上に、前記主面を上向きに間隔を設けて一列に搭載された複数の第１の前記半導体素子と、
隣接する第１の前記半導体素子の前記第２の接続端子間を架橋するように第１の前記半導体素子間に配置され、前記第２の接続端子を介して前記隣接する第１の前記半導体素子と互いに前記周縁部を対向させて接続された第２の前記半導体素子と、
第２の前記半導体素子上に互いに裏面を対向させて搭載され、前記第３の接続端子を介して接続された第３の前記半導体素子と、
第１の前記半導体素子上に互いに前記平坦部を対向させ、かつ、第３の前記半導体素子と前記周縁部を対向させて搭載された第４の前記半導体素子とを有し、
第４の前記半導体素子は、前記第１の接続端子を介して第１の前記半導体素子に接続され、かつ、前記第２の接続端子を介して第３の前記半導体素子に接続されていることを特徴とするマルチチップモジュール。In a multichip module in which a plurality of semiconductor elements are mounted on a mounting board,
The substrate constituting the semiconductor element has a main surface having a flat portion at the center and a peripheral portion made of a flat surface formed lower than the flat portion, and a flat substrate back surface,
The semiconductor element includes a first connection terminal for external connection formed on the flat portion, a second connection terminal for external connection formed on the peripheral edge portion that is electrically connected to the first connection terminal, A third connection terminal for external connection formed on the back surface of the substrate that is electrically connected to the second connection terminal;
A plurality of the first semiconductor elements mounted in a row on the mounting substrate with the main surface facing upwards; and
The first semiconductor element that is disposed between the first semiconductor elements so as to bridge between the second connection terminals of the adjacent first semiconductor elements, and that is adjacent to the first semiconductor element via the second connection terminals. And the second semiconductor element connected with the peripheral edge facing each other,
A third semiconductor element mounted on the second semiconductor element with the back surfaces facing each other and connected via the third connection terminal;
And the fourth semiconductor element mounted on the first semiconductor element with the flat portions facing each other and with the third semiconductor element and the peripheral edge facing each other.
The fourth semiconductor element is connected to the first semiconductor element through the first connection terminal, and is connected to the third semiconductor element through the second connection terminal. Multi-chip module characterized by
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| JP5087995B2 (en) * | 2007-05-30 | 2012-12-05 | ソニー株式会社 | Semiconductor device and manufacturing method thereof |
| KR100945504B1 (en) * | 2007-06-26 | 2010-03-09 | 주식회사 하이닉스반도체 | Stack package and method for manufacturing of the same |
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