KR101226030B1 - Circuit with hysteresis and power on reset/brownout detection circuit comprising the same - Google Patents

Abstract

PURPOSE: A circuit having hysteresis characteristic and a power on reset/brownout detection circuit including thereof are provided to reduce current consumption by preventing the formation of DC current path in the operating state of circuit which has hysteresis characteristic. CONSTITUTION: An inverter comprises more hysteresis generator(1010). The hysteresis generating unit comprises more current path interrupter. The current path interrupter is formed with the 3rd transistor(T3). A gate of the third transistor is connected to a sauce of a second transistor(T2). The hysteresis generator comprises a gate connected to an input terminal, and a first transistor(T1) which has the source connected to a first terminal. The second transistor has a connected source to the output terminal, a drain connected to a second terminal, and a source connected to a drain of the first transistor.

Description

CIRCUIT WITH HYSTERESIS AND POWER ON RESET / BROWNOUT DETECTION CIRCUIT COMPRISING THE SAME}

The present invention relates to a circuit having hysteresis characteristics and a power-on reset / brownout detection circuit including the same, and more particularly, to a circuit capable of stably providing hysteresis with low current consumption.

In general, in the operation of a chip including a memory, a latch, a flip-flop, a register, and the like, the magnitude of the supply voltage is very important. If the supply voltage falls below a certain level than normally provided, the various devices on the chip will not work properly.

Therefore, when the power supply voltage drops above a certain level, there is a need for a circuit that resets devices or circuits existing on the chip and releases the reset when the power supply voltage returns to a normal level. Such a circuit is called a POR / BOD (Power On Reset / Brown Out Detection) circuit.

For example, assuming that a 5V power supply voltage is applied and the power supply voltage is less than 3V, the circuits present on the chip do not operate normally, the POR / BOD circuit resets when the power supply voltage drops below 3V. And reset when the power supply voltage is over 3V.

In general, however, there are noises due to many factors on the chip. For example, when the supply voltage is near 3V, if the noise is continuously changed to 3V up and down, the POR / BOD circuit repeats the operation of reset and reset.

To eliminate this noise effect, the POR / BOD circuit typically outputs a reset signal when the supply voltage drops to a voltage slightly lower than 3V, and resets when the supply voltage again rises to slightly higher than 3V. Release it. That is, there is a difference, i.e., hysteresis, between the value of the power supply voltage to be reset and the power supply voltage to be reset.

However, in the related art, there are problems such as a large current consumption in a circuit for providing such hysteresis, or normal operation under a specific condition.

Korean Patent Publication No. 1997-0072706 (published: 1997.11.07)

It is an object of the present invention to provide a circuit having a hysteresis characteristic that performs an inverting function but provides hysteresis between a voltage going from low to high and a voltage going from high to low.

It is another object of the present invention to provide a circuit having low hysteresis characteristics in operation and capable of generating hysteresis normally under all conditions.

It is another object of the present invention to provide a power on reset / brown out detection (POR / BOD) circuit comprising a circuit having the above characteristics.

According to an embodiment of the invention, the inverter; And a hysteresis generator coupled between the input terminal and the output terminal of the inverter, the hysteresis generator providing hysteresis between the voltage at the time of changing from low to high and the voltage at the time of changing from high to low in the output voltage of the inverter. A circuit having hysteresis characteristics is provided.

The hysteresis generator may include a transistor having a gate connected to the output terminal, a drain connected to the input terminal, and a source connected to the first terminal.

In another embodiment, the hysteresis generator may include: a first transistor having a gate connected to the input terminal and a source connected to the first terminal; And a second transistor having a gate connected to the output terminal, a drain connected to a second terminal, and a source connected to the drain of the first transistor.

In still another embodiment, the hysteresis generator may further include a current path blocking unit that turns off the first transistor when the output voltage of the output terminal is high to block a current path through the first and second transistors. can do.

The current path blocking unit may include a third transistor having a gate connected to the output terminal, a drain connected to the input terminal, and a source connected to the first terminal.

The current path blocking unit may include a third transistor having a gate connected to a source of the second transistor, a drain connected to the input terminal, and a source connected to the first terminal.

The inverter may include a first conductivity type transistor having a gate connected to an input terminal and a source connected to the second terminal; And a second conductive transistor having a gate connected to the input terminal and a drain connected to a drain of the first conductive transistor, wherein the drain of the first transistor can be connected to a source of the second conductive transistor. have.

The first conductivity type and the second conductivity type may be any one of p-type and n-type, respectively, and may be mutually exclusive.

The transistor may be either p-type or n-type.

The first terminal and the second terminal may be any one of a ground and a power terminal, respectively, and may be mutually exclusive.

Meanwhile, according to another embodiment of the present invention, another circuit including a circuit having low current consumption and capable of normal hysteresis generation operation, and a power on reset / brownout detection circuit including such a circuit may be provided. .

According to the present invention, while the inverter performs an inverting function, hysteresis may be generated between a voltage from which the output voltage goes from low to high and from high to low.

In addition, according to the present invention, a DC current path is not formed in the operation of a circuit having hysteresis characteristics, thereby preventing current consumption, and hysteresis can be normally generated under all conditions.

Meanwhile, according to the present invention, a circuit having a hysteresis characteristic that operates stably can be applied to a power-on reset / brownout detection circuit.

1 is a waveform diagram illustrating power on reset / brown out detection.
2 is a circuit diagram showing the configuration of a general inverter.
FIG. 3 is a waveform diagram illustrating the operation of the inverter of FIG. 2.
4 is a circuit diagram showing the configuration of a circuit having hysteresis characteristics according to the first embodiment of the present invention.
FIG. 5 is a waveform diagram illustrating the operation of a circuit having the hysteresis characteristic of FIG. 4.
6 is a circuit diagram showing the configuration of a circuit having hysteresis characteristics according to the second embodiment of the present invention.
FIG. 7 is a waveform diagram illustrating the operation of a circuit having the hysteresis characteristic of FIG. 6.
8 is a circuit diagram showing the configuration of a circuit having hysteresis characteristics according to the third embodiment of the present invention.
9 is a waveform diagram illustrating the operation of a circuit having the hysteresis characteristic of FIG. 8.
10 is a circuit diagram showing a configuration of a circuit having hysteresis characteristics according to the fourth embodiment of the present invention.
FIG. 11 is a waveform diagram illustrating the operation of a circuit having the hysteresis characteristic of FIG. 10.
12 is a circuit diagram illustrating an embodiment of a POR / BOD circuit to which a circuit having hysteresis characteristics is applied according to an embodiment of the present invention.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiment of the Present Invention]

POR Of BOD  Circuit

First, a power on reset / brown out detection (POR / BOD) circuit to which a circuit having hysteresis characteristics according to an exemplary embodiment of the present invention may be applied will be described.

1 is a waveform diagram illustrating power on reset / brown out detection.

In FIG. 1, "VDD" represents a power supply voltage, and "RESETB" is an output signal of a POR / BOD circuit. The "RESETB" signal is a signal to prevent malfunction of the circuit inside the chip, and resets a circuit requiring initialization when the power supply voltage drops below a certain level. When the "RESETB" signal is low, the circuits are reset, and when the "RESETB" signal is high, the reset is reversed.

Referring to FIG. 1, when the power supply voltage VDD is below a predetermined level, the "RESETB" signal goes low. For example, when the power supply voltage VDD decreases below a certain level for some reason such as noise or discharge, some circuits (eg, memory, latch, flip-flop, or register, etc.) operate correctly. You may need to reset them because you may not be able to. Thus, in this case, the POR / BOD circuit outputs a low signal as a "RESETB" signal, thereby resetting the corresponding circuits.

Next, the basic operation of the inverter will be briefly described before the description of the circuit having the hysteresis characteristic according to the embodiment of the present invention.

inverter

FIG. 2 is a circuit diagram showing the configuration of a general inverter, and FIG. 3 is a waveform diagram illustrating the operation of the inverter of FIG.

Referring to FIG. 2, an inverter generally includes a first conductivity type transistor PM having a gate connected to an input terminal IN, a drain connected to an out terminal OUT, and a source connected to a power supply terminal. It may include a second conductivity type transistor NM connected to an input terminal IN, a drain connected to an out terminal OUT, and a source connected to ground.

Hereinafter, the first conductivity type transistor and the second conductivity type transistor will be described as an example of being a p-type transistor and an n-type transistor. However, this is merely for convenience of description, and p-type and n-type may be substituted for each other.

Referring to FIG. 3, the thin solid line represents the change in magnitude of the power supply voltage VDD, the broken line represents the change in the input voltage of the inverter, and the thick solid line represents the change in the output voltage of the inverter. It is assumed that the power supply voltage VDD and the input voltage to the inverter change as shown in the graph shown in FIG. 3. The input voltage to the inverter may be generated in a waveform as shown in FIG. 3 by, for example, a current reference circuit. The saturation state voltage of the input voltage is assumed to be greater than the threshold voltage of the transistor.

The p-type transistor PM is turned on when the difference between the power supply voltage VDD and the input voltage is greater than the threshold voltage Vthp, and the n-type transistor NM has a threshold voltage Vthn. Since it is ON during a greater period, the output voltage of the inverter is the same high signal as the supply voltage VDD only if the difference between the supply voltage VDD and the input voltage of the inverter is greater than the threshold voltage Vthp. Becomes

However, when noise or the like is present at a point where the output signal of the inverter goes from low to high or at a point that changes from high to low, the output signal of the inverter continuously changes according to the noise. As a result, unnecessary changes exist in the output signal of the inverter, and power consumption also increases.

Therefore, a circuit having hysteresis characteristics was developed to eliminate such noise effects. A circuit with hysteresis ensures that there is a difference between the voltage when the output waveform goes from low to high and the voltage from high to low. This difference is called a hysteresis band. When the power supply voltage changes from low to high due to the hysteresis band, the output voltage of the inverter changes from the ideal value, and when the power supply voltage changes from high to low, the output voltage of the inverter changes slightly lower than the ideal case. do. This results in insensitivity to noise as large as the hysteresis band.

In the present specification, the "circuit having hysteresis characteristics" may be implemented in the form of a Schmitt trigger circuit or a hysteresis inverter, but a circuit providing the hysteresis band described above is not limited thereto, and accordingly, according to the present invention. It can be included in a circuit having hysteresis characteristics.

Hysteresis  Circuit with characteristics

1st Example

4 is a diagram illustrating a configuration of a circuit having hysteresis characteristics according to the first embodiment, and FIG. 5 is a waveform diagram illustrating an operation of the circuit having hysteresis characteristics of FIG. 4.

Referring to FIG. 4, the circuit having hysteresis characteristics according to the embodiment is a structure in which the hysteresis generator 410 is added to the structure of the general inverter described with reference to FIG. 2. The hysteresis generator 410 is a part for providing hysteresis as described above, and may be implemented with, for example, one transistor T.

As described above, the inverter may be implemented with a p-type transistor PM and an n-type transistor NM, in which a transistor T constituting the hysteresis generator 410 is additionally provided. The gate of the transistor T is connected to the output terminal OUT, the drain is connected to the input terminal IN, and the source is connected to ground. The hysteresis generator 410 also allows the voltage at the input terminal IN to become the ground voltage when the output terminal OUT voltage is high.

Referring to FIG. 5, the operation of the circuit having the hysteresis characteristic of FIG. 4 will be described. In FIG. 5, the thin solid line represents the change in the magnitude of the power supply voltage VDD, the broken line represents the change in the voltage of the input terminal IN, and the thick solid line represents the change in the voltage of the output terminal OUT. As the input voltage, a voltage having a waveform is input as shown in FIG. 3, and such a voltage may be generated by, for example, a current reference circuit or the like. The saturation state voltage of the input voltage is assumed to be greater than the threshold voltage of the transistor.

The p-type transistor PM is turned on when the power supply voltage VDD is greater than or equal to the threshold voltage Vthp than the input terminal IN voltage. When the p-type transistor PM is in an ON state, the output terminal OUT voltage becomes equal to the magnitude of the power supply voltage VDD. That is, it becomes a high level. Since the high level signal is input to the gate of the transistor T, the transistor T is turned ON, so that the voltage at the input terminal IN is set to the ground voltage.

When the power supply voltage VDD is gradually lowered and the difference from the voltage of the input terminal IN set to the ground voltage is smaller than the threshold voltage Vthp of the p-type transistor PM, the p-type transistor PM is turned off. It becomes a state. At this time, since the transistor T is turned off, the input terminal IN has the same waveform as the voltage input from the current reference circuit, and the n-type transistor NM is turned on. The output terminal OUT voltage goes low. According to this operation, an output waveform as shown in Fig. 5 is obtained, and a difference, i.e., hysteresis, is generated between the voltage Vth_H from which the output waveform goes from low to high and the voltage Vth_L from high to low. Able to know.

In the above description, the inverter is configured by the p-type transistor PM and the n-type transistor NM, and the transistor T is implemented by the n-type transistor, but the conductivity type of each transistor may be changed. For example, the conductivity types of the p-type transistor PM and the n-type transistor NM of the inverter are reversed, and the hysteresis generator 410 transistor T may be implemented as a p-type transistor. In this case, the terminal connected to the power supply voltage VDD and the ground terminal will be reversed. Meanwhile, the type of transistor may also be variously implemented as a BJT, a FET, a MOSFET, or an application transistor thereof.

In the circuit having the hysteresis characteristic shown in Fig. 4, since the n-type transistor NM is turned off when the p-type transistor PM is ON, the DC current does not flow unnecessarily and consumes power. Has the advantage of being less. However, there is a disadvantage in that the voltage Vth_L at the point where the output waveform is changed from high to low is very low at the level of the threshold voltage Vthp of the transistor. In general, the threshold voltage of the transistor is about 0.6V to 0.8V, and implementation problems occur when a voltage at which the output waveform of the circuit changes from high to low is specified at a voltage level higher than the threshold voltage. A circuit having hysteresis characteristics for solving this problem is described below.

Second Example

FIG. 6 is a diagram showing the configuration of a circuit having hysteresis characteristics according to the second embodiment, and FIG. 7 is a waveform diagram for explaining the operation of the circuit having hysteresis characteristics in FIG.

Referring to FIG. 6, the circuit having hysteresis characteristics according to the second embodiment may further include a hysteresis generator 610 in the structure of the general inverter described with reference to FIG. 2. The hysteresis generator 610 is a part for providing hysteresis as described above. The hysteresis generator 610 according to the second embodiment is implemented with two n-type transistors T1 and T2. That is, the p-type transistor PM and the n-type transistor NM constitute a general inverter, wherein the first and second transistors T1 and T2 are additionally provided. The gate of the first transistor T1 is connected to the input terminal IN, the drain is connected to the source of the n-type transistor NM, and the source is connected to ground. In addition, the gate of the second transistor T2 is connected to the output terminal OUT, the drain is supplied with the power supply voltage VDD, and the source is connected to the source of the n-type transistor NM and the drain of the first transistor. . Hereinafter, a case where the first and second transistors T1 and T2 are implemented as n-type transistors will be described as an example.

The operation of the circuit having the hysteresis characteristic of FIG. 6 will be described with reference to FIG. 7. In FIG. 7, the thin solid line represents the change in the magnitude of the power supply voltage VDD, the broken line represents the change in the voltage of the input terminal IN, and the thick solid line represents the change in the voltage of the output terminal OUT. In addition, the dashed-dotted line represents a change in the source voltage of the second transistor T2. As the input voltage, a voltage having a waveform is input as shown in FIG. 3, and such a voltage may be generated by, for example, a current reference circuit or the like. The saturation state voltage of the input voltage is assumed to be greater than the threshold voltage of the transistor.

The p-type transistor PM is turned on when the power supply voltage VDD is greater than or equal to the threshold voltage Vthp than the input terminal IN voltage. When the p-type transistor PM is in an ON state, the output terminal OUT voltage is equal to the magnitude of the power supply voltage VDD, and becomes a high level. Since the high level signal is input to the gate of the second transistor T2, the second transistor T2 is turned on. The source voltage of the second transistor T2 is reduced by the gate-source voltage Vgs from the output terminal OUT voltage. In addition, since the voltage difference between the input terminal IN voltage and ground is larger than the threshold voltage of the first transistor T1, the first transistor T1 is turned on. As a result, a DC current path from the power supply terminal to the ground via the second transistor T2 and the first transistor T1 is formed.

When the power supply voltage VDD gradually decreases, the output terminal OUT voltage also decreases in the same manner as the power supply voltage VDD. When the difference between the power supply voltage VDD and the input terminal IN is smaller than the threshold voltage of the p-type transistor PM, the p-type transistor PM is turned off. The output terminal OUT voltage is turned low when both the n-type transistor NM and the first transistor T1 are ON. Since the first transistor T1 is currently in an ON state, when the n-type transistor NM is in an ON state, the output terminal OUT voltage may be low. The n-type transistor NM is turned on when the voltage of the input terminal IN and the source voltage of the second transistor T2 (that is, the gate-source voltage Vgs of the n-type transistor NM) are greater than the threshold voltage. ) State can be. The source voltage of the second transistor T2 is subtracted from the power supply voltage VDD by the gate-source voltage Vgs, and the gate-source voltage Vgs may vary depending on the size of the second transistor T2. have. The size of a transistor can be expressed as W / L, where W is the width of the transistor and L is the length of the transistor. Since the power supply voltage VDD continuously decreases, the source voltage of the second transistor T2 also decreases, and is continuously reduced to become smaller than the input terminal IN voltage, and the difference from the input terminal IN voltage. Is greater than the threshold voltage of the n-type transistor NM, the n-type transistor NM is turned on. Since both the n-type transistor NM and the first transistor T1 are turned ON, the output terminal OUT voltage becomes a ground voltage. The voltage Vth_L at which the output terminal OUT voltage changes from high to low may vary according to the size of the second transistor. For example, when the gate-source voltage is increased according to the size of the second transistor T2, the output terminal OUT voltage when the n-type transistor NM is turned on becomes large, and accordingly, The Vth_L value becomes large. That is, the voltage Vth_L when the output terminal OUT voltage changes from high to low according to the size of the second transistor T2 can be adjusted, and the voltage when the output terminal OUT voltage changes from low to high. Can be different from (Vth_L).

In the above, the inverter is configured by the p-type transistor PM and the n-type transistor NM, and the transistors T1 and T2 of the hysteresis generator 610 are described as an example of the n-type transistor. The conductivity type may change. For example, the conductivity types of the p-type transistor PM and the n-type transistor NM of the inverter are reversed, and the hysteresis generator 610 transistors T1 and T2 may be implemented as p-type transistors. In this case, the terminal connected to the power supply voltage VDD and the ground terminal will be reversed. Meanwhile, the type of transistor may also be variously implemented as a BJT, a FET, a MOSFET, or an application transistor thereof.

The circuit having the hysteresis characteristic according to the second embodiment has an advantage that the voltage Vth_L when the voltage of the output terminal OUT is changed from high to low can be made larger than in the first embodiment. However, when the output terminal OUT voltage is high, since the first and second transistors T1 and T2 are turned ON, the power source is grounded through the second transistor T2 and the first transistor T1 from the power supply. A DC current path leading to is formed, which results in a large current consumption.

Hereinafter, a configuration of a circuit having hysteresis characteristics in which this disadvantage is overcome will be described.

Third Example

FIG. 8 is a diagram showing the configuration of a circuit having hysteresis characteristics according to the third embodiment, and FIG. 9 is a waveform diagram for explaining the operation of the circuit having hysteresis characteristics of FIG.

Referring to FIG. 8, the circuit having hysteresis characteristics according to the third embodiment further includes a hysteresis generator 810 in the structure of the general inverter described with reference to FIG. 2. The hysteresis generator 810 according to the third embodiment is a portion for providing hysteresis and combines the hysteresis generator of the first embodiment and the hysteresis generator of the second embodiment. Alternatively, the hysteresis generation unit of the second embodiment may further include a current path blocking unit 811. Specifically, the hysteresis generator 810 according to the third embodiment is implemented with three transistors T1, T2, and T3, of which the third transistor T3 serves as the current path blocking unit 811. can do. That is, the p-type transistor PM and the n-type transistor NM constitute a general inverter, and the first, second, and third transistors T1, T2, and T3 are additionally provided. Hereinafter, an example in which the first to third transistors T1, T2, and T3 are implemented as n-type transistors will be described. The gate of the first transistor T1 is connected to the input terminal IN, and the drain thereof is connected to the source of the n-type transistor NM. The gate of the first transistor T1 is connected to the input terminal IN, the drain is connected to the source of the n-type transistor NM, and the source is connected to ground. The gate of the second transistor T2 is connected to the output terminal OUT, the drain is supplied with the power supply voltage VDD, and the source is connected to the source of the n-type transistor NM and the drain of the first transistor T1. do. In addition, the gate of the third transistor T3 is connected to the output terminal OUT, the drain is connected to the input terminal IN, and the source is connected to the ground.

In FIG. 8, an inverter includes a p-type transistor PM and an n-type transistor NM, and the transistors T1, T2, and T3 of the hysteresis generator 810 are illustrated as an n-type transistor. The conductivity type of each transistor may be changed. For example, the conductivity types of the p-type transistor PM and the n-type transistor NM of the inverter are reversed, and the hysteresis generator 810 transistors T1, T2, and T3 may be implemented as p-type transistors. In this case, the terminal connected to the power supply voltage VDD and the ground terminal will be reversed. Meanwhile, the type of transistor may also be variously implemented as a BJT, a FET, a MOSFET, or an application transistor thereof.

Referring to FIG. 9, the operation of the circuit having the hysteresis characteristic of FIG. 8 will be described below. In FIG. 9, the thin solid line represents the change in the magnitude of the power supply voltage VDD, the dashed line represents the change in the voltage of the input terminal IN, and the thick solid line represents the change in the voltage of the output terminal OUT. As the input voltage, a voltage having a waveform is input as shown in FIG. 3, and such a voltage may be generated by, for example, a current reference circuit or the like. The saturation state voltage of the input voltage is assumed to be greater than the threshold voltage of the transistor.

The p-type transistor PM is turned on when the power supply voltage VDD is greater than or equal to the threshold voltage Vthp than the input terminal IN voltage. When the p-type transistor PM is in an ON state, the output terminal OUT voltage is equal to the magnitude of the power supply voltage VDD, and becomes a high level. Since the high level output terminal OUT voltage is input to the gate of the third transistor T3, the third transistor T3 is turned on, and thus the input terminal IN is set to the ground voltage. Is set. When the output terminal OUT voltage is at the high level, the second transistor T2 is turned on, but since the input terminal IN voltage is set to the ground voltage, the first transistor T1 is turned off ( OFF) state, so that no DC current path is formed. That is, when the third transistor T3 constituting the current path blocking unit 811 has the output terminal OUT voltage high, the first transistor T1 is turned off to thereby turn off the first and second transistors T1 and T2. Shut off the current path through). Therefore, it is possible to prevent current consumption, which is a problem of the circuit having the hysteresis characteristic described with reference to FIG. 6. However, as the turn-on voltage that is too strong is applied to the gate of the third transistor T3, the third transistor T3 is always in an ON state and the voltage at the input terminal IN is continuously set to the ground voltage. Can be. Accordingly, there may be a problem that the output terminal OUT voltage does not change from high to low under certain conditions.

The hysteresis in which all these problems are improved is a circuit having the hysteresis characteristics of the fourth embodiment described below.

Fourth Example

FIG. 10 is a diagram illustrating a configuration of a circuit having hysteresis characteristics according to the fourth embodiment, and FIG. 11 is a waveform diagram illustrating the operation of the circuit having hysteresis characteristics in FIG. 10.

Referring to FIG. 10, the circuit having hysteresis characteristics according to the fourth embodiment also includes a hysteresis generator 1010 in the structure of the general inverter described with reference to FIG. 2. In addition, as in the third embodiment, the hysteresis generation unit of the second embodiment may further include a current path blocking unit 1011. The current path blocking unit 1011 may be implemented with a third transistor T3. Except that the gate of the third transistor (T3) is connected to the source of the second transistor (T2) is the same as the configuration of the hysteresis generator 810 according to the third embodiment described with reference to FIG.

Referring to FIG. 11, the operation of the circuit having the hysteresis characteristic of FIG. 10 will be described below. In FIG. 11, the thin solid line shows the change in the magnitude of the power supply voltage VDD, the broken line shows the change in the voltage of the input terminal IN, and the thick solid line shows the change in the voltage of the output terminal OUT. In addition, the dashed-dotted line represents a change in the source voltage of the second transistor T2. As the input voltage, a voltage having a waveform is input as shown in FIG. 3, and such a voltage may be generated by, for example, a current reference circuit or the like. The saturation state voltage of the input voltage is assumed to be greater than the threshold voltage of the transistor.

The p-type transistor PM is turned on when the power supply voltage VDD is greater than or equal to the threshold voltage Vthp than the input terminal IN voltage. When the p-type transistor PM is in an ON state, the output terminal OUT voltage is equal to the magnitude of the power supply voltage VDD, and becomes a high level. Since the high level signal is input to the gate of the second transistor T2, the second transistor T2 may be in an ON state. The source voltage of the second transistor T2 is reduced by the gate-source voltage Vgs from the output terminal OUT voltage. The size W / L of the second transistor T2 may determine its gate-source voltage Vgs. Since the source voltage of the second transistor T2 also increases when the output terminal OUT voltage goes high, this signal is input to the gate of the third transistor T3, and this value is input to the third transistor T3. If the threshold voltage is greater than, the third transistor T3 is turned on, and the input terminal IN is set to the ground voltage. At this time, since the first transistor T1 is in an OFF state, a DC current path from the power supply terminal to the ground is not formed, and thus a problem of current consumption can be prevented. That is, in the fourth embodiment, the first and second transistors T1 are turned off when the third transistor T3 constituting the current path blocking unit 1011 is turned off when the output terminal OUT voltage is high. It is possible to block the current path via T1, T2). The voltage input to the gate of the third transistor T3 is reduced in magnitude from the power supply voltage VDD by the gate-source voltage Vgs of the second transistor T2. Therefore, a voltage having a relatively lower magnitude than that in the third embodiment is input to the gate of the third transistor T3 so that the third transistor T3 is always in the ON state even when the power supply voltage VDD decreases. The problem that the output terminal OUT voltage does not change from high to low can be solved.

When the power supply voltage VDD gradually decreases, the output terminal OUT voltage also decreases in the same manner as the power supply voltage VDD. When the difference between the power supply voltage VDD and the input terminal IN is smaller than the threshold voltage of the p-type transistor PM, the p-type transistor PM is turned off. When the source voltage of the second transistor T2 is lower than the threshold voltage of the third transistor T3, the third transistor T3 is turned off so that the input terminal IN voltage is input from the current reference circuit. Will be equal to The output terminal OUT voltage is turned low when the n-type transistor NM and the first transistor T1 are both in an ON state, and the voltage input from the current reference circuit is n-type transistor NM and the first voltage. Since the threshold voltage of the first transistor T1 is greater than the threshold voltage, the output terminal OUT is turned low, and thus, the source voltage of the second transistor T2 is also set to the ground voltage. The voltage Vth_L when the output terminal OUT voltage changes from high to low is the magnitude of the output terminal OUT voltage when the third transistor T3 changes from an ON state to an OFF state. That is, the output terminal OUT voltage at the point where the voltage obtained by subtracting the gate-source voltage Vgs of the second transistor T2 from the output terminal OUT voltage falls below the threshold voltage of the third transistor T3 is " Vth_L "value.

In the circuit having the hysteresis characteristic according to the fourth embodiment, the DC current path is not formed when the output terminal OUT voltage is high, so that current consumption can be prevented, and the gate-source of the third transistor T3 is prevented. Too much voltage can be prevented from occurring. That is, all the problems of the circuit having the hysteresis characteristic described above can be solved.

In FIG. 10, an inverter includes a p-type transistor PM and an n-type transistor NM, and the transistors T1, T2, and T3 of the hysteresis generator 1010 are illustrated as an n-type transistor. The conductivity type of each transistor may be changed. For example, the conductivity types of the p-type transistor PM and the n-type transistor NM of the inverter are reversed, and the hysteresis generator 1010 transistors T1, T2, and T3 may be implemented as p-type transistors. In this case, the terminal connected to the power supply voltage VDD and the ground terminal will be reversed. Meanwhile, the type of transistor may also be variously implemented as a BJT, a FET, a MOSFET, or an application transistor thereof.

POR Of BOD  Circuit design

12 is a diagram illustrating an embodiment of a POR / BOD circuit to which a circuit having hysteresis characteristics is applied according to an embodiment of the present invention.

Referring to FIG. 12, the POR / BOD circuit may include a current reference circuit 1210 and a circuit 1220 having hysteresis characteristics.

The current reference circuit 1210 is a circuit for generating an input signal to the circuit 1220 having hysteresis characteristics, and generates an input signal as shown by broken lines in FIGS. 5, 7, 9, and 11. Detailed description of the operation of the current reference circuit 1210 will be omitted. The current reference circuit 1210 shown in FIG. 12 is merely one implementation and may be implemented in a different manner.

The circuit 1220 having hysteresis characteristics may be implemented as a circuit having hysteresis characteristics as shown in any one of FIGS. 4, 6, 8, and 10.

Features, structures, effects, and the like described in the above embodiments are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in each embodiment may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

410, 610, 810, and 1010: hysteresis generator

Claims (11)

delete delete inverter; And
A hysteresis generator coupled between an input terminal and an output terminal of the inverter, the hysteresis generator providing hysteresis between the voltage at the time of changing from low to high and the voltage at the time of changing from high to low in the output voltage of the inverter,
The hysteresis generator,
A first transistor having a gate connected to the input terminal and a source connected to the first terminal; And
And a second transistor having a gate connected to the output terminal, a drain connected to a second terminal, and a source connected to the drain of the first transistor. The method of claim 3,
The hysteresis generator,
And a current path blocking section for turning off the first transistor when the output voltage of the output terminal is high to cut off the current path via the first and second transistors. 5. The method of claim 4,
The current path blocking unit,
And a third transistor having a gate connected to the output terminal, a drain connected to the input terminal, and a source connected to the first terminal. 5. The method of claim 4,
The current path blocking unit,
And a third transistor having a gate connected to the source of the second transistor, a drain connected to the input terminal, and a source connected to the first terminal. The method according to any one of claims 3 to 6,
The inverter,
A first conductive transistor having a gate connected to the input terminal and a source connected to the second terminal; And
A second conductive transistor having a gate connected to the input terminal and a drain connected to a drain of the first conductive transistor;
Wherein the drain of the first transistor is connected to the source of the second conductivity type transistor. The method of claim 7, wherein
Wherein the first conductivity type and the second conductivity type are any one of p type and n type, and are mutually exclusively selected. The method according to any one of claims 3 to 6,
Wherein the transistor is either p-type or n-type. The method according to any one of claims 3 to 6,
Wherein the first terminal and the second terminal are each one of a ground and a power supply terminal, and are mutually exclusively selected. A power-on reset / brownout detection circuit comprising a circuit having hysteresis characteristics according to any one of claims 3 to 6.

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