KR101225372B1

KR101225372B1 - thin film transistor, fabricating method of the same, and flat panel display having the thin film transistor

Info

Publication number: KR101225372B1
Application number: KR1020050132916A
Authority: KR
Inventors: 김진욱
Original assignee: 엘지디스플레이 주식회사
Priority date: 2005-12-29
Filing date: 2005-12-29
Publication date: 2013-01-22
Also published as: KR20070070407A

Abstract

The present invention relates to a thin film transistor, comprising: a substrate having a gate electrode formed thereon; A gate insulating film formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode; A semiconductor layer on the gate insulating layer; And a source / drain electrode formed spaced apart from each other on both ends of the semiconductor layer, and a method of manufacturing the same.

Thin film transistor, gate insulating film, buffer layer, organic-inorganic, PMMA, PDMS

Description

Thin film transistor, fabrication method thereof and flat panel display device comprising the thin film transistor

1A to 1E are process diagrams illustrating a manufacturing process of a thin film transistor according to a first exemplary embodiment of the present invention.

2A to 2F are process diagrams illustrating a manufacturing process of a thin film transistor according to a second exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100, 200: substrate 110, 240: gate electrode

120, 230: gate insulating film 130, 220: semiconductor layer

140a, 260a: source electrode 140b, 260b: drain electrode

210: buffer layer 250: interlayer insulating film

The present invention relates to a thin film transistor, and more particularly to a thin film transistor and a method for manufacturing the same that can be formed in an easy process.

In general, a flat panel display device is divided into a passive matrix method and an active matrix method according to a driving method, and an active driving method has circuits using thin film transistors (TFTs). Such circuits are typically used in flat panel displays such as liquid crystal displays (LCDs) and organic electroluminescence displays (OLEDs).

Such a thin film transistor includes a semiconductor layer, a gate electrode, and a source / drain electrode made of amorphous silicon or polycrystalline silicon, and the gate electrode and the semiconductor layer are separated by a gate insulating film interposed therebetween.

Here, the silicon nitride film formed by the vacuum deposition method is mainly used as the gate insulating film. The vacuum deposition method not only requires expensive vacuum equipment and deposition equipment, but also has a problem of low production yield. In addition, in the thin film transistor that can realize a large area and a high resolution, the thickness of the gate electrode is increasing in order to prevent the RC wiring delay phenomenon. In particular, in a bottom gate type thin film transistor in which the gate insulating film is formed on the gate electrode, a short phenomenon may occur between the gate electrode and the source / drain electrode, thereby increasing the thickness of the gate insulating film. Should be formed. However, since it is difficult to form a thick silicon nitride film used as the gate insulating film, the gate insulating film is formed through at least two deposition processes. Accordingly, there is a problem that the production yield decreases as the deposition process is increased.

In addition, in the case of a top gate thin film transistor in which a semiconductor layer is formed on a substrate, a buffer layer interposed between the substrate and the semiconductor layer is provided to protect the semiconductor layer by impurities discharged from the substrate. do. Here, the buffer layer is also formed of a silicon nitride film or a silicon oxide film, so the vacuum deposition process must be performed.

As a result, the gate insulating film or the buffer layer may be formed of an organic or organic-inorganic insulating material, and may be formed through a simple wet process. However, adhesion between the gate insulating film and the semiconductor layer or between the buffer layer and the semiconductor layer may be reduced. As a result, the thin film transistor may be defective.

In order to solve the above problems, an object of the present invention is to provide a thin film transistor and a method of manufacturing the same that can form an insulating film using an easy wet process.

Another object of the present invention is to provide a thin film transistor and a method for manufacturing the same, which can improve the adhesive force between the gate insulating film and the semiconductor layer.

In addition, another object of the present invention is to provide a thin film transistor and a method of manufacturing the same, which can improve the adhesion between the buffer layer and the semiconductor layer.

Furthermore, another object of the present invention is to provide a flat panel display device having the thin film transistor.

In order to achieve the above technical problem, an aspect of the present invention provides a thin film transistor. The thin film transistor may include a substrate on which a gate electrode is formed; A gate insulating film formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode; A semiconductor layer on the gate insulating layer; And source and drain electrodes spaced apart from each other on both ends of the semiconductor layer.

Another aspect of the present invention to achieve the above technical problem provides a thin film transistor. The thin film transistor includes a substrate; A buffer layer formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the substrate; A semiconductor layer formed on the buffer layer; A gate insulating film formed on the substrate including the semiconductor layer; A gate electrode formed on the gate insulating layer corresponding to a portion of the semiconductor layer; An interlayer insulating layer formed on the semiconductor layer and having contact holes exposing both ends of the semiconductor layer, respectively; And source / drain electrodes positioned on the interlayer insulating layer and in contact with both ends of the semiconductor layer.

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a thin film transistor. The manufacturing method includes forming a gate electrode on a substrate; Forming a gate insulating film by applying a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode; Forming a semiconductor layer on the gate insulating layer; And forming source / drain electrodes spaced apart from each other on both ends of the semiconductor layer.

Another aspect of the present invention to achieve the above technical problem provides a method of manufacturing a thin film transistor. The manufacturing method includes applying a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on a substrate to form a buffer layer; Forming a semiconductor layer on the buffer layer; Forming a gate insulating film on the substrate including the semiconductor layer; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film having contact holes exposing the source / drain regions, respectively, on the semiconductor layer; And forming a source / drain electrode on the interlayer insulating layer and in contact with the source / drain region, respectively.

Hereinafter, with reference to the drawings of the thin film transistor according to the present invention will be described in detail. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of an apparatus may be exaggerated for convenience. Like numbers refer to like elements throughout.

Referring to FIG. 1A, first, a metal film is formed on a substrate 10 and then patterned to form a gate electrode 110. The gate electrode 110 may include at least one selected from the group consisting of Al, AlNd, Cr, Al / Cu, Au / Ti, Au / Cr, and MoW.

A gate insulating layer 120 is formed on the substrate 100 including the gate electrode 110. The gate insulating layer 120 may be formed of a composition including a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-AB-) represented by Chemical Formula 1 as an organic-inorganic hybrid insulating material. . That is, the composition containing the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-AB-) is at least one of a wet process, such as a dip coating method, a spray coating method, a spin coating method, a bar coating method, and a roll coating method. The film can be formed in one way.

In this case, the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-A-B-) is a linear polymer, and it is preferable that the polymer is a diblock copolymer in which the polymerization degree of the PMMA and the PDMS is 1: 1.

[Formula 1]

Here, n and m are integers of 10-1000.

The gate insulating layer 120 is formed with the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-A-B-) unevenly arranged on the substrate 100.

Referring to FIG. 1B, a heat treatment process is performed on the gate insulating layer 120 to constantly rearrange the PMMA-PDMS (PMMA-PDMS) copolymer (-AB-) forming the gate insulating layer 120. do. In this case, the PMMA (A) is arranged on the surface of the substrate 100, that is, under the gate insulating film 120, and the PDMS (B) is arranged in the air, that is, above the gate insulating film 120. do. The PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) is able to be behaved by the heat energy applied in the heat treatment process, and the surface energy of the PMMA (A) is higher than that of the PDMS (B). This is because the PDMS (B) easily interfaces with air.

In the heat treatment process, the PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) may behave, and the PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) of the PMMA (A) In consideration of the temperature that can prevent the degradation of the can be carried out at 100 to 120 ℃ for 10 to 60 minutes.

Referring to FIG. 1C, UV is irradiated onto the gate insulating layer 120 to convert the PDMS (B) into silica (B ′) in the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-AB-). Let's do it. This is to improve the adhesion with the amorphous silicon formed in the process to be described later.

In this case, the UV irradiation process may use a wavelength of 180 to 259nm sufficient to convert the PDMS (B) to silica (B ').

As a result, the gate insulating layer 120 may be formed by arranging PMMA (A) below and silica (B) above.

Although not illustrated, an inorganic insulating layer may be further formed on the gate insulating layer 120. The inorganic insulating film may be any one of a silicon oxide film, a silicon nitride film, or a stacked film thereof.

Referring to FIG. 1D, amorphous silicon (a-Si) is deposited on the gate insulating layer 120 by chemical vapor deposition, and then doped with impurities on the amorphous silicon (a-Si) layer 130a. An amorphous silicon (n + a-Si) layer 130b to which impurities are added is formed.

The silicon (n + a-Si) layer 130b to which the impurity is added has ohmic contact characteristics when it is bonded with a metal. The semiconductor layer 130 through a photolithography process using anisotropic etching so that only a portion of the amorphous silicon layer 130a and the doped silicon (n + a-Si) layer 130b correspond to the gate electrode 110. To form.

Referring to FIG. 1E, a metal film is formed on the gate insulating layer 120 including the semiconductor layer 130, and then patterned to form source / drain electrodes respectively positioned on both ends of the semiconductor layer 130. 140a, 140b). The source / drain electrodes 140a and 140b may include at least one of Cr, Mo, and Al.

Thus, in order to form the thin film transistor, the gate insulating film may be formed through an easy wet process with a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer. In addition, as the surface of the gate insulating film is converted into silica by performing a heat treatment process and a UV irradiation process on the gate insulating film, adhesion between the gate insulating film and the semiconductor layer may be improved.

Furthermore, the flat panel display may be manufactured using the thin film transistor manufactured as described above.

Although not shown in the drawing, a protective film is formed on the source / drain electrodes 140a and 140b and a contact hole exposing a portion of the drain electrode 140b is formed. Here, the protective film may be made of silicon nitride, silicon oxide, an acrylic compound, BCB or PFCB.

Thereafter, a pixel electrode is formed on the passivation layer to be electrically connected to the drain electrode 140b through the contact hole.

In this case, when the flat panel display device is a liquid crystal display device, a liquid crystal display device may be manufactured by attaching an opposing substrate having a color filter and a transparent electrode to a substrate on which the thin film transistor is formed, and then injecting liquid crystal. .

In addition, when the flat panel display is an organic light emitting display device, an organic layer including an emission layer may be formed on the pixel electrode, and then an organic light emitting display device may be manufactured by forming an opposite electrode on the organic layer. Here, the organic layer may further include a charge transport layer or a charge injection layer.

Referring to FIG. 2A, first, a buffer layer 210 is formed on a substrate 200. Here, the buffer layer 210 serves to protect the semiconductor layer to be formed on the substrate 200 from impurities contained in the substrate 200.

The buffer layer 210 may be formed of a composition including a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-A-B-) represented by Chemical Formula 1 as an organic-inorganic hybrid insulating material. That is, the composition containing the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-AB-) is at least one of a wet process, such as a dip coating method, a spray coating method, a spin coating method, a bar coating method, and a roll coating method. The film can be formed in one way.

[Formula 1]

Here, n and m are integers of 10-1000.

The buffer layer 210 is formed with the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-A-B-) unevenly arranged on the substrate 200.

Referring to FIG. 2B, a heat treatment process is performed on the buffer layer 210 to constantly rearrange the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-A-B-) forming the buffer layer 210. At this time, as described above, the PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) is due to the difference between the thermal energy applied in the heat treatment process and the surface energy of the PDMS (B) and PMMA (A) The PMMA (A) is arranged on the surface of the substrate 200, that is, under the buffer layer 210, and the PDMS (B) is arranged in the air, that is, above the buffer layer 210.

In the heat treatment process, the PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) may behave, and the PMMA-PDMS (polymethyl methacrylate-polydimethylsiloxane) copolymer (-AB-) of the PMMA (A) In consideration of the temperature that can prevent the occurrence of degradation of the can be carried out at 100 to 120 ℃ for 10 to 60 minutes.

Referring to FIG. 2C, UV is irradiated onto the buffer layer 210 to convert the PDMS (B) in the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer (-AB-) into silica (B ′). .

Referring to FIG. 2D, an amorphous silicon film 220 is formed on the buffer layer 210. The amorphous silicon film 220 may be formed by chemical vapor deposition (CVD). Here, the chemical vapor deposition method may be a method selected from the group consisting of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) and plasma chemical vapor deposition (PECVD). The amorphous silicon film 220 is crystallized to form a polysilicon film, and then patterned to form a semiconductor layer 220. The method of crystallization may be performed using one method selected from the group consisting of SPC, ELA, SLS, MILC, and MIC.

Referring to FIG. 2E, a gate insulating layer 230 is formed on the buffer layer 210 including the semiconductor layer 220. The gate insulating layer 230 may be formed using a chemical vapor deposition method using a silicon oxide film (SiO 2) or a silicon nitride film (SiN x). Alternatively, the composition comprising the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer may be formed by a wet process, such as a dip coating method, a spray coating method, a spin coating method, a bar coating method, or a roll coating method. can do.

A gate electrode 240 is formed on the gate insulating layer 230. The gate electrode 240 is formed by forming a metal film on the entire substrate and patterning the semiconductor layer 220 to correspond to the lower semiconductor layer 220. Ion implantation is performed on the semiconductor layer 220 using the patterned gate metal layer 240 as a mask. Due to the ion implantation, the source and drain regions of the semiconductor layer 220 are set, and the channel region is defined by setting the source and drain regions.

Referring to FIG. 2F, an interlayer insulating layer 250 is formed on the gate electrode 240. The interlayer insulating layer 250 is formed by using a chemical vapor deposition method using a silicon oxide film (SiO 2) or a silicon nitride film (SiN x), or wet the composition including the polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer. It can form through a process.

Thereafter, contact holes exposing portions of the source and drain regions of the semiconductor layer 220 are formed in the interlayer insulating layer 250 and the gate insulating layer 230. Source and drain electrodes 260a and 260b connected to the source and drain regions are formed through the contact hole, respectively.

Thus, in order to form the thin film transistor, the buffer layer may be formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer through an easy wet process. In addition, as the surface of the buffer layer 210 is converted into silica by performing a heat treatment and UV irradiation process on the buffer layer, adhesion between the buffer layer 210 and the semiconductor layer 220 may be improved. In addition, the interlayer insulating film 250 and the gate insulating film 230 in addition to the buffer layer 210 may be formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer, thereby forming a thin film transistor through an easy wet process. .

Although not shown in the drawings, a passivation layer is formed on the source / drain electrodes 260a and 260b and a contact hole exposing a portion of the drain electrode 260b is formed. Here, the protective film may be made of silicon nitride, silicon oxide, an acrylic compound, BCB or PFCB.

Thereafter, after forming the pixel electrode on the passivation layer to be electrically connected to the drain electrode 260b through the contact hole, as described in the first embodiment of the present invention, a flat panel display device is formed on the pixel electrode. A unit pixel of can be formed to manufacture a flat panel display device.

As described above, the thin film transistor according to the present invention may form an insulating film by a wet process using a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer, thereby improving productivity.

In addition, through the heat treatment and UV irradiation process on the gate insulating film and the buffer layer formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer can be improved adhesion to the semiconductor layer.

In addition, an insulating film can be formed by a wet process using inexpensive equipment instead of a deposition process that requires expensive equipment, thereby reducing production equipment investment.

Although described above with reference to embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the invention described in the claims below. You will understand.

Claims

A substrate on which a gate electrode is formed;

A gate insulating film formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode;

A semiconductor layer on the gate insulating layer; And

A thin film transistor comprising a source electrode and a drain electrode formed on both ends of the semiconductor layer spaced apart from each other.

The method of claim 1,

The PMMA-PDMS copolymer is a thin film transistor, characterized in that the diblock copolymer (diblock copolymer).

The method of claim 1,

PDMS of the PMMA-PDMS copolymer, characterized in that the thin film transistor is converted to silica.

The method of claim 3, wherein

The PDMS-converted silica of the PMMA-PDMS copolymer is arranged toward the lower surface of the semiconductor layer, wherein the PMMA is thin film transistor, characterized in that arranged toward the substrate surface.

The method of claim 1,

A thin film transistor, characterized in that an inorganic insulating film is further formed on the gate insulating film.

6. The method of claim 5,

The inorganic insulating film is a thin film transistor, characterized in that any one of a silicon oxide film, a silicon nitride film or a laminated film thereof.

Board;

A buffer layer formed of a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the substrate;

A semiconductor layer formed on the buffer layer;

A gate insulating film formed on a substrate including the semiconductor layer;

A gate electrode formed on the gate insulating layer corresponding to a portion of the semiconductor layer;

An interlayer insulating layer formed on the semiconductor layer and having contact holes exposing both ends of the semiconductor layer, respectively; And

And a source electrode and a drain electrode on the interlayer insulating layer and in contact with both ends of the semiconductor layer, respectively.

The method of claim 7, wherein

The method of claim 9,

The method of claim 7, wherein

The gate insulating film is a thin film transistor, characterized in that formed of a single layer or a double film selected from the group consisting of PMMA-PDMS copolymer, silicon oxide film, silicon nitride film.

The method of claim 7, wherein

The interlayer insulating film is a thin film transistor, characterized in that formed of a single layer or a double film selected from the group consisting of PMMA-PDMS copolymer, silicon oxide film, silicon nitride film.

A flat panel display device comprising the thin film transistor according to any one of claims 1 to 12.

Forming a gate electrode on the substrate;

Forming a gate insulating film by applying a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode;

Forming a semiconductor layer on the gate insulating layer; And

Forming a source electrode and a drain electrode spaced apart from each other on both ends of the semiconductor layer.

15. The method of claim 14,

In the step of forming a gate insulating film by applying a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the gate electrode

And applying a composition including a PMMA-PDMS copolymer on the substrate including the gate electrode, and then performing a heat treatment process and a UV irradiation process.

16. The method of claim 15,

The heat treatment process is a method of manufacturing a thin film transistor, characterized in that carried out at 100 to 120 ℃.

16. The method of claim 15,

The UV irradiation process is a method of manufacturing a thin film transistor, characterized in that using a wavelength of 180 to 259 nm.

15. The method of claim 14,

The PMMA-PDMS copolymer is a diblock copolymer, characterized in that a thin film transistor manufacturing method.

15. The method of claim 14,

After forming a gate insulating film by applying a PMMA-PDMS copolymer on the gate electrode,

And forming an inorganic insulating film on the gate insulating film.

20. The method of claim 19,

And the inorganic insulating film is any one of a silicon oxide film, a silicon nitride film or a laminated film thereof.

Coating a polymethyl methacrylate-polydimethylsiloxane (PMMA-PDMS) copolymer on the substrate to form a buffer layer;

Forming a semiconductor layer on the buffer layer;

Forming a gate insulating film on the substrate including the semiconductor layer;

Forming a gate electrode on the gate insulating film;

Forming an interlayer insulating film having contact holes exposing the source and drain regions, respectively, on the semiconductor layer; And

And forming a source electrode and a drain electrode on the interlayer insulating layer and in contact with the source and drain regions, respectively.

22. The method of claim 21,

In the step of forming a buffer layer by applying the PMMA-PDMS copolymer on the substrate

After applying the PMMA-PDMS copolymer on the substrate, a method of manufacturing a thin film transistor comprising the step of performing a heat treatment process and a UV irradiation process.

23. The method of claim 22,

24. The method of claim 23,

22. The method of claim 21,

The gate insulating film is a method of manufacturing a thin film transistor, characterized in that formed of a single layer film or a double film selected from the group consisting of PMMA-PDMS copolymer, silicon oxide film, silicon nitride film.

22. The method of claim 21,

The interlayer insulating film is a method of manufacturing a thin film transistor, characterized in that formed of a single layer film or a double film selected from the group consisting of PMMA-PDMS copolymer, silicon oxide film, silicon nitride film.