KR100623686B1 - Method of fabricating TFT - Google Patents

Abstract

Provided is a method of manufacturing a thin film transistor. The manufacturing method includes forming an amorphous silicon film on the upper and lower surfaces of a substrate having an upper surface and a lower surface; Forming an inorganic protective film on the amorphous silicon film formed on the upper surface; Etching the amorphous silicon film formed on the lower surface; And exposing the amorphous silicon film by removing the inorganic protective film on the upper surface.

Thin film transistors, amorphous silicon, inorganic protective layer

Description

Method of manufacturing thin film transistors {Method of fabricating TFT}

1A to 1D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention;

2A and 2B are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another exemplary embodiment of the present invention;

3 is a diagram showing mobility characteristics of a thin film transistor according to an embodiment of the present invention;

4 is a diagram showing the S factor characteristics of a thin film transistor according to an embodiment of the present invention,

5 is a diagram illustrating threshold voltage characteristics of a thin film transistor according to an exemplary embodiment of the present invention.

Explanation of reference numerals for the main parts of the drawing

10, 100: insulated substrate,

15: gas for forming an amorphous silicon film

110a, 110b: amorphous silicon film,

110: semiconductor layer,

120: weapon shield,

113 and 116: source and drain regions of the semiconductor layer

The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor capable of improving electrical characteristics.

In general, a flat panel display device is divided into a passive matrix method and an active matrix method according to a driving method, and an active driving method has circuits using thin film transistors (TFTs). Such circuits are typically used in flat panel display devices such as liquid crystal displays (LCDs) and organic electroluminescence displays (OLEDs).

Among the thin film transistors, polycrystalline silicon thin film transistors can be manufactured at a low temperature similar to that of amorphous silicon thin film transistors due to the development of crystallization technology. In addition, the mobility of electrons and holes is higher than that of amorphous silicon thin film transistors, and it is possible to implement a complementary metal-oxide semiconductor (CMOS) thin film transistor including NMOS and PMOS. Can be formed at the same time.

Such a polycrystalline silicon thin film transistor is characterized in that its semiconductor layer is a polycrystalline silicon film. Forming the semiconductor layer which is such a polycrystalline silicon film is performed by laminating an amorphous silicon film on a substrate and crystallizing it. In forming the amorphous silicon film, low pressure chemical vapor deposition (LPCVD) is generally used. In this case, an amorphous silicon film is formed on the upper and lower surfaces of the substrate.

Since the amorphous silicon film formed on the lower surface of the substrate causes defects such as an abnormality in color coordinates during light emission, after the crystallization, a protective film is laminated on the polycrystalline silicon film formed on the upper surface and the lower protective film is used as a mask. The silicon film formed on the surface is removed. Then, the protective film on the upper surface is removed.

However, after the polycrystalline silicon film is formed, various processes such as lamination of the protective film and removal of the protective film are performed on the polycrystalline silicon film, and the polycrystalline silicon film under the protective film may be excessively etched during the removal of the protective film. Therefore, the surface of the polycrystalline silicon film may be poor, thereby lowering the interface characteristics between the polycrystalline silicon film and the insulating film stacked thereon. In addition, in the etching process of the polycrystalline silicon film for forming the semiconductor layer, a problem arises in that the substrate is broken due to the change in capacitance due to the above problem. This may cause degradation of thin film transistor device characteristics.

An object of the present invention is to provide a method of manufacturing a thin film transistor that can stabilize the characteristics of the thin film transistor by using a method of minimizing the effect on the semiconductor layer when removing the silicon film on the back of the insulating substrate.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a thin film transistor. The manufacturing method includes forming an amorphous silicon film on the upper and lower surfaces of a substrate having an upper surface and a lower surface; Forming an inorganic protective film on the amorphous silicon film formed on the upper surface; Etching the amorphous silicon film formed on the lower surface; And exposing the amorphous silicon film by removing the inorganic protective film on the upper surface.

The substrate may further include one substrate selected from the group consisting of glass, plastic, and quartz.

Forming the amorphous silicon film may be performed using a chemical vapor deposition method.

The chemical vapor deposition method may be one method selected from the group consisting of atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) and plasma chemical vapor deposition (PECVD).

Preferably, the amorphous silicon film has a thickness of 300 kPa to 700 kPa.

The inorganic protective film is preferably a silicon oxide film.

The inorganic protective film may be formed to a thickness of 300 kPa to 1000 kPa.

Etching the amorphous silicon film formed on the lower surface may be performed using dry etching.

The manufacturing method of the amorphous silicon film exposed on the upper surface is one selected from the group consisting of excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS) Crystallization using a method.

The manufacturing method may further include patterning an inorganic protective film formed on the amorphous silicon film, and etching the amorphous silicon film formed on the lower surface may include forming an amorphous silicon film on the upper surface using the patterned inorganic protective film as a mask. It can be done simultaneously with patterning.

Etching the amorphous silicon film formed on the lower surface may be performed using dry etching.

The patterned amorphous silicon film is crystallized using one method selected from the group consisting of excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS). desirable.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1A through 1D are cross-sectional views illustrating a method of manufacturing a thin film transistor according to a first exemplary embodiment of the present invention, step by step.

Referring to FIG. 1A, a substrate having an upper surface and a lower surface is loaded into a chamber. The substrate may be one substrate selected from the group consisting of glass, plastic, and quartz. The chamber is provided with a chuck 10 for fixing substrates, and in the chamber, gases 15 for forming an amorphous silicon film react to form amorphous silicon on upper and lower surfaces of various substrates 100 fixed in the chamber. The film 105 is formed. Thus, an amorphous silicon film is formed to the lower surface in addition to the upper surface required for fabrication of the thin film transistor.

As described above, the amorphous silicon film 105 is formed using chemical vapor deposition (CVD). The chemical vapor deposition method may be performed using one method selected from the group consisting of atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) and plasma chemical vapor deposition (PECVD). Preferably, an amorphous silicon film may be formed using low pressure chemical vapor deposition (LPCVD). At this time, the pressure in the chamber is preferably 0.2 to 0.354 torr, and it is preferable that the partial pressure of SiH4 is 200 to 250 sccm. In addition, the amorphous silicon film 105 may be formed to have a thickness of 300 to 700 kPa.

Referring to FIG. 1B, an inorganic passivation layer 120 is formed on the entire surface of the amorphous silicon layer 105a formed on the upper surface of the substrate 100. The inorganic protective film may be SiO ₂ or SiN _x . Preferably, the inorganic protective film 120 is a silicon oxide film (SiO ₂ ), and is preferably formed to a thickness of 300 to 1000 GPa.

Referring to FIG. 1C, the amorphous silicon film 105b formed on the lower surface of the substrate is removed using the inorganic protective film (120 of FIG. 1B) as a mask. Removing the amorphous silicon film 105b may be performed by inverting the substrate on which the films are deposited using a sorter, followed by dry etching. Subsequently, the inorganic protective film 120 is removed. When the inorganic protective layer 120 is a silicon oxide layer, removing the inorganic protective layer 120 may be performed using a wet etching method using 0.5 to 1% HF solution.

As a result, the amorphous silicon film 105b and the inorganic protective film 120 of the lower surface of the substrate are removed, and the amorphous silicon film 105a remains on the upper surface of the substrate 100. The semiconductor layer is formed by forming a polysilicon layer by crystallizing the amorphous silicon film 105a on the upper surface of the substrate 100 and then patterning the polysilicon layer. The crystallization may be performed using excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS).

Referring to FIG. 1D, a gate insulating layer 120 is formed over the entire surface of the semiconductor 110 layer. The gate insulating layer 120 is formed of a conventional insulating material, for example, a silicon nitride film (SiN _x ) or a silicon oxide film (SiO ₂ ).

The gate electrode 130 is formed on the substrate on which the gate insulating layer 120 is formed by using a predetermined conductive material, and ion implantation is performed using the gate electrode as a mask to form a source region 110a and a drain in the semiconductor layer. The region 110c is formed. At the same time, the channel region 110b is defined. In addition, an interlayer insulating layer 140 is formed on the substrate. Contact holes 145 are formed in the interlayer insulating layer 140 and the gate insulating layer 120 to expose the source and drain regions 210a and 210c. Subsequently, a conductive material is stacked on the substrate on which the contact hole 145 is formed and patterned, thereby contacting the source and drain regions 110a and 110c exposed in the contact hole 145, respectively. To form.

2A is a cross-sectional view illustrating some process steps of a method of manufacturing a thin film transistor according to a second exemplary embodiment of the present invention.

Referring to FIG. 2A, an amorphous silicon film is formed in the same manner as in FIG. 1A, and an inorganic protective film 120 is formed on the amorphous silicon film 105a on the upper surface of the substrate as in FIG. 1B, and then the inorganic The protective film 120a is patterned to match the semiconductor layer region. By using the patterned inorganic protective film 120a as a mask, the amorphous silicon film 105a on the upper surface is patterned, and at the same time, the amorphous silicon film on the bottom of the substrate is removed. Etching the amorphous silicon film formed on the lower surface may be performed using dry etching. After the patterning of the amorphous silicon film, the inorganic protective film 120a remaining on the amorphous silicon film is removed. When the inorganic protective layer 120 is a silicon oxide layer, removing the inorganic protective layer 120 may be performed using a wet etching method using 0.5 to 1% HF solution.

Therefore, after the above process, the patterned amorphous silicon film 105C remains on the substrate 100 and its upper surface. The semiconductor layer is formed by crystallizing the amorphous silicon film 105a from which the inorganic protective film is removed. The crystallization may be performed using excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS).

Referring to FIG. 2B, a gate insulating layer 120 is formed over the entire surface of the semiconductor 110 layer. The gate insulating layer 120 is formed of a conventional insulating material, for example, a silicon nitride film (SiN _x ) or a silicon oxide film (SiO ₂ ).

The gate electrode 130 is formed on a substrate on which the gate insulating layer 120 is formed by using a predetermined conductive material, and ion implantation is performed using the gate electrode as a mask to form a source region 110a and a drain in the semiconductor layer. The region 110c is formed. At the same time, the channel region 110b is defined. In addition, an interlayer insulating layer 140 is formed on the substrate. Contact holes 145 are formed in the interlayer insulating layer 140 and the gate insulating layer 120 to expose the source and drain regions 110a and 110c. Subsequently, a conductive material is stacked on the substrate on which the contact hole 145 is formed and patterned, thereby contacting the source and drain regions 110a and 110c exposed in the contact hole 145, respectively. To form.

Unlike the conventional technique of performing etching and patterning of the silicon film on the lower part of the substrate after the crystallization process, the present invention is a cause that can act as a pollution source at the interface between the semiconductor layer and the gate insulating film by performing the above process in the amorphous silicon film state. You can remove them beforehand. Further, after that, crystallization is performed to stably form a polysilicon film, thereby improving characteristics of the thin film transistor element. That is, by removing the inorganic protective film 120 before the crystallization process and proceeding the crystallization process, it is possible to solve the conventional problem that the silicon film is damaged by the over etching by the etchant used for removing the inorganic protective film, for example, HF solution. The surface characteristics of the semiconductor layer may be improved to bring about stabilization of the process during mass production.

Hereinafter, preferred examples will be presented to aid in understanding the present invention.

Comparative Example

An amorphous silicon film was formed on the insulating substrate using LPCVD, crystallization was performed, and then an inorganic protective film was formed on the upper surface of the substrate. Thereafter, the polysilicon film under the substrate was dry-etched, and the inorganic protective film on the upper surface was removed. The polysilicon layer on the substrate was patterned to form a semiconductor layer, a gate insulating layer was formed on the semiconductor layer, and a gate electrode was formed. After forming the interlayer insulating film and the source drain electrode on the gate electrode, the thin film transistor device was completed.

In the graphs of FIGS. 3 to 5, A is a thin film transistor manufactured by the above method.

Experimental Example

An amorphous silicon film was formed on the insulating substrate using the LPCVD method. At this time, the pressure in the chamber was 0.2 to 0.354 torr, the partial pressure of SiH4 was 200 to 250 sccm, and the thickness of the amorphous silicon film was formed to be 300 to 700 kPa. An SiO ₂ protective film was formed on the upper surface of the substrate to 300 to 1000 GPa. After performing dry etching on the amorphous silicon film under the protective film formed substrate, the protective film on the upper surface of the substrate was removed by wet etching with 0.5 to 1% HF solution. Through the above process, an amorphous silicon film remains on the upper surface of the substrate, and the semiconductor layer was formed by crystallizing the amorphous silicon film.

The semiconductor layer was formed, and a process for forming a thin film transistor on the semiconductor layer was performed in the same manner as the comparative example.

In the graphs of FIGS. 3 to 5, B is a thin film transistor manufactured by the above method.

Characteristics of the thin film transistor according to the comparative example and the experimental example are as shown in the graphs of FIGS.

3 is a graph illustrating mobility characteristics of a thin film transistor.

Referring to FIG. 3, it can be seen that the mobility of the thin film transistor of the method of protecting the amorphous silicon layer using the inorganic protective layer and forming the semiconductor layer is improved, compared to the conventional method of forming the semiconductor layer. In addition, the standard deviation range (SD1) of mobility is also reduced, it is possible to implement a stable mobility characteristics when manufacturing a thin film transistor device.

4 is a graph showing the S factor characteristics of the thin film transistor.

Referring to FIG. 4, the thin film transistor has a lower factor value than the conventional method of forming a semiconductor layer using the inorganic protective layer to protect the amorphous silicon layer and form the semiconductor layer. Therefore, the switching characteristic of a thin film transistor element can be improved.

5 is a graph illustrating threshold voltage characteristics of a thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 5, the thin film transistor of the method of protecting the amorphous silicon layer using the inorganic protective layer and forming the semiconductor layer may move the threshold voltage in a positive direction, rather than the conventional method of forming the semiconductor layer. Therefore, when the threshold voltage characteristic of the device is shifted in the negative direction, when the amorphous silicon layer is removed from the lower surface of the substrate, the improvement of the threshold voltage characteristic can be expected only by manufacturing a thin film transistor using a protective material of the front amorphous silicon layer. . In addition, the standard deviation range of the threshold voltage (SD2) is also reduced, it is possible to implement a stable threshold voltage characteristics when manufacturing a thin film transistor device.

According to the present invention, when the amorphous silicon film is removed from the lower surface of the substrate, when the thin film transistor is manufactured using the silicon layer which protects the amorphous silicon film on the upper surface using the inorganic protective film, the device characteristics of the thin film transistor are improved.

By eliminating the causes that may act as a contaminant at the interface between the semiconductor layer and the gate insulating film in advance, crystallization can be performed to form a polysilicon film stably, and solve the problem of damaging the semiconductor layer by an etchant used to remove the inorganic protective film. This can lead to stabilization of the process during mass production. In addition, the thin film transistor according to the embodiment of the present invention has improved characteristics of charge mobility, threshold voltage, and S factor, so that the response speed and switching characteristics may be improved when the thin film transistor is applied to a flat panel display device.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (15)

Forming an amorphous silicon film on the upper and lower surfaces of the substrate having an upper surface and a lower surface; Forming an inorganic protective film on the amorphous silicon film formed on the upper surface; Etching the amorphous silicon film formed on the lower surface; And Exposing an amorphous silicon film by removing the inorganic protective film on the upper surface.  The method of claim 1, The substrate is a method of manufacturing a thin film transistor further comprising one substrate selected from the group consisting of glass, plastic and quartz.  The method of claim 1, The forming of the amorphous silicon film is a method of manufacturing a thin film transistor using chemical vapor deposition (CVD).  The method of claim 3, wherein The chemical vapor deposition method may be performed by using a method selected from the group consisting of atmospheric chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) and plasma chemical vapor deposition (PECVD). Manufacturing method.  The method of claim 1, The thickness of the amorphous silicon film is 300 Å to 700 두께 manufacturing method of a thin film transistor.  The method of claim 1, The inorganic protective film is a thin film transistor manufacturing method, characterized in that the silicon oxide film.  The method of claim 1, The inorganic protective film is a thin film transistor manufacturing method to form a thickness of 300 kHz to 1000 kHz.  The method of claim 1, And etching the amorphous silicon film formed on the lower surface by using dry etching. The method of claim 1, The amorphous silicon film exposed on the upper surface is selected from the group consisting of excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS). Method of manufacturing a thin film transistor further comprising the step of crystallization. The method of claim 1, Patterning an inorganic protective film formed on the amorphous silicon film, and etching the amorphous silicon film formed on the lower surface simultaneously patterning the amorphous silicon film on the upper surface using the patterned inorganic protective film as a mask Method of manufacturing a thin film transistor, characterized in that carried out. The method of claim 10, And etching the amorphous silicon film formed on the lower surface by using dry etching. The method of claim 10, Crystallizing the patterned amorphous silicon film using one method selected from the group consisting of excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS) Method of manufacturing a thin film transistor further comprising.  Forming an amorphous silicon film on the upper and lower surfaces of the insulating substrate having an upper surface and a lower surface by using low pressure chemical vapor deposition (LPCVD); Forming a silicon oxide film on the amorphous silicon film formed on the upper surface; Dry etching the amorphous silicon film formed on the lower surface; Exposing an amorphous silicon film by removing the inorganic protective film on the upper surface; And And crystallizing the exposed amorphous silicon film. The method of claim 13, Patterning an inorganic protective film formed on the amorphous silicon film, and etching the amorphous silicon film formed on the lower surface simultaneously patterning the amorphous silicon film on the upper surface using the patterned inorganic protective film as a mask Method of manufacturing a thin film transistor, characterized in that carried out. The method of claim 13, The crystallization of the patterned amorphous silicon film is performed using one method selected from the group consisting of excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and sequential lateral solidification (SLS). Method of manufacturing a thin film transistor further comprising.

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