KR101170913B1 - Method for forming Isolation Film of Semiconductor Device - Google Patents

Abstract

The present invention relates to a method for forming a device isolation film of a semiconductor device. Specifically, when forming a device isolation film using a trench formed by a shallow trench isolation (STI) process, an amorphous silicon layer is deposited inside the trench and a field oxide film is embedded. Next, an oxide film is formed on the amorphous silicon layer by an oxygen injection process to form a wide device isolation layer to an active region, thereby forming a safe device isolation layer at which no moat is generated at an interface between the device isolation layers in a subsequent cleaning process. It relates to a device isolation film forming method that can be formed.

Description

Method for forming Isolation Film of Semiconductor Device

1A to 1E are cross-sectional views illustrating a method of forming a device isolation film according to a conventional method.

2A to 2I are cross-sectional views illustrating a method of forming an isolation layer in accordance with the present invention.

<Brief description of the main parts of the drawing>

1, 21: semiconductor substrate 3, 23: pad oxide film

5, 25: pad nitride film 7, 27: photoresist layer

9, 29: trenches 11, 33; Field oxide

13 interface of the device isolation layer 31 amorphous silicon layer

35: oxygen injection process 37: oxide film

The present invention relates to a method for forming a device isolation film of a semiconductor device. Specifically, when forming a device isolation film using a trench formed by a shallow trench isolation (STI) process, an amorphous silicon layer is deposited inside the trench and a field oxide film is embedded. Next, an oxide film is formed on the amorphous silicon layer by an oxygen injection process to form a wide device isolation layer to an active region, so that no moat is generated at the interface of the device isolation layer in a subsequent cleaning process. It relates to a device isolation film forming method capable of forming a.

Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large capacity memory devices is required. Such a large capacity of memory devices is based on the micro process technology that is doubled for each generation. One memory cell is being promoted by research.

In particular, in order to form a transistor, a capacitor, and the like on a semiconductor substrate, an isolation region is formed to separate devices from each other in order to prevent the device from being electrically energized with an active region that is electrically energized. The development of a method for reducing the isolation region has emerged as one of the important issues in the miniaturization technology of the memory device.

The device isolation region has been recently formed using a local oxidation of silicon (LOCOS) process.

The locus process is a process of forming a device isolation film by growing a pad oxide film by forming a pad oxide film and a pad nitride film on a semiconductor substrate, removing the pad nitride film of the predetermined portion by an etching process, and performing an oxidation process.

In this case, the locus process uses a polysilicon film forming process serving as a buffer between the pad oxide film and the nitride film and a PBL (poly buffered locos) process for growing a field oxide film.

However, in order to fabricate a large-capacity memory device that is reduced to submicron or less, as the device design dimension becomes smaller and smaller, and the device isolation region is reduced, when the oxide film is grown by the locus process, the side surface of the device isolation film diffuses. A bird's beak phenomenon has occurred.

The presently developed process to remedy this disadvantage is the STI process.

The STI process is a method of forming an electrically separated device isolation layer by forming a trench having a predetermined depth in a semiconductor substrate and then depositing an oxide material therein and performing a subsequent CMP process to remove unnecessary oxide layers. .

A method of forming an isolation layer according to a conventional STI method may be described with reference to the drawings illustrated in FIGS. 1A to 1E.

Referring to FIG. 1A, the pad oxide film 3 and the pad nitride film 5 and the photoresist layer 7, which are ISO mask layers, are sequentially formed on the semiconductor substrate 1.

A photo / etching process using an isolation mask (not shown) is performed on the entire surface of the layer stacked in FIG. 1A to form an ISO pattern and a trench 9 as shown in FIG. 1B.

After forming a field oxide film (not shown) on the entire surface including the trench 9 of FIG. 1B, a process of chemical mechanical polishing (hereinafter, referred to as "CMP") is performed by using the pad nitride film 5 as an etch stop film. Alternatively, the field oxide film 11 as shown in FIG. 1C is formed by performing a planarization process by an etch-back process.                         

The device isolation layer as shown in FIG. 1D is formed by performing the selective etching process of removing the ISO pattern using the planarized field oxide layer 11 of FIG. 1C using an etching mask.

Next, a subsequent pad nitride film strip process for removing the pad nitride film 5 and the like remaining on the semiconductor substrate 1 on which the device isolation film of FIG. 1D is formed and to alleviate stress of the semiconductor substrate 1 are performed. Additional wet etch process is performed.

In this case, since the stress characteristics are concentrated in the top and bottom corners of the substrate during the trench formation process, the STI method deteriorates device characteristics. It is difficult to stably perform a gap-fill process.

In addition, since the CMP execution time should be adjusted so that the field oxide film remains on the active region in consideration of the polishing margin when the CMP process of planarizing the field oxide film is performed, the process having uniformity is performed. Can not.

That is, when insufficient etching is performed by incorrectly setting the CMP time, an overetch process that requires one more etching process should be applied. However, when performing the transient etching, the micro trench shape generated at the boundary between the deposition slope and the planarization (hereinafter referred to as "PL") mask of the field oxide film penetrates into the active region and enters the active region. As damage is caused, thinning occurs in the subsequent wet etching process step, in which both edge portions of the field oxide film are excessively removed. As a result, as shown in FIG. 1E, a moat is generated at the interface 13 of the device isolation layer, thereby deteriorating the device characteristics due to the hump characteristic.

Due to this problem, a moat is generated at the interface of the device isolation layer as shown in FIG. 1E by a thinning phenomenon in which both edge portions of the field oxide film are excessively removed in a subsequent wet etching process step. Hump characteristics deteriorate device characteristics.

Accordingly, the present inventors have completed the present invention by developing a new concept of method that can overcome the above-mentioned problems without active equipment as a result of active research.

In the present invention, when the device isolation film is formed by the STI process, an amorphous silicon layer and a field oxide film are sequentially formed on the trench, and then an upper portion of the amorphous silicon layer using the oxygen injection process is oxidized, thereby forming a wide device to the active region. An object of the present invention is to provide a method of forming a separator.

In the present invention to achieve the above object,

(a) sequentially forming a pad oxide film and a pad nitride film on the silicon substrate;

(b) forming an ISO pattern and a trench by performing a photo / etch process on the pad oxide layer and the pad nitride layer;

(c) depositing an amorphous silicon layer on the entire surface including the trench;

(d) filling the trench by forming a field oxide layer on the entire surface of the substrate including the trench on which the amorphous silicon layer is deposited;

(e) performing an etching process of removing the field oxide layer over the active region until the amorphous silicon layer is exposed;

(f) planarizing the field oxide layer by performing a polishing process on the amorphous silicon layer and the field oxide layer using the pad nitride layer as an etch stop layer;

(g) oxidizing an upper portion of the amorphous silicon layer by performing an oxygen injection process on the entire surface of the pad nitride layer, the amorphous silicon layer, and the field oxide layer; And

(h) forming a device isolation film by removing the pad oxide film and the pad nitride film over the active region, thereby providing an STI type device isolation film forming method of a semiconductor device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 2A, the pad oxide layer 23, the pad nitride layer 25, which is an ISO mask layer, and the photoresist layer 27 are sequentially formed on the semiconductor substrate 21.

In this case, the pad oxide film 23 is formed to a thickness of 50 ~ 200Å by using a thermal oxidation process, the pad nitride film 25 is formed to a thickness of 1000 ~ 2000Å, the photoresist layer 27 Is formed to 3000 ～ 10000 ～ thickness.

 A photoresist pattern (not shown) exposing the semiconductor substrate 21 is formed by performing a photo / development process using a device isolation mask on the layer formed in FIG. 2A, and then using the photoresist pattern as an etching mask. A dry etching process is performed on the oxide film 23 and the pad nitride film 25 to form an ISO pattern and a trench 29 as shown in 2b.

The dry etching process is an etching gas comprising N ₂ 5-10 sccm, HBr 100-150 sccm, Cl ₂ 35-70 sccm, and O ₂ 0-10 sccm gas alone or mixed under a pressure of 15-45 mT and 430-700 Ws-100-400 Wb power conditions. Is performed.

In this case, the depth and slope of the trench may be formed in a desired size according to the amount of etching gas applied thereto. Preferably, the depth of the trench may be formed using HBr 100˜150 sccm and Cl ₂ 35˜70 sccm mixed gas. 2500 ~ 4000Å, 70 ~ 90 degree inclination based on ISO pattern.

After forming the trench 30, an after treatment chamber (ATC) process may be further performed to compensate for the damaged sidewalls and bottom of the trench.

An amorphous silicon layer 31 is formed on the entire surface of the ISO pattern and trench 29 obtained in FIG. 2B as shown in FIG. 2C.

In this case, the amorphous silicon layer using at least one of SiH ₄ , Si ₂ H ₆ or SiH ₂ Cl ₂ gas, using low pressure chemical vapor deposition (LP-CVD) at a temperature of 400 ~ 600 ℃ Form 10 ～ 200Å thick.

The trench 29 is buried as shown in FIG. 2D by forming a field oxide film 33 on the entire surface including the amorphous silicon layer 31 of FIG. 2C.

The field oxide film forming process is performed such that voids are not formed using a high density plasma (HDP) oxide film according to general gap fill process conditions.

The field oxide film is formed to have a thickness of 4000 to 6000 로부터 from the top of the amorphous silicon oxide film 33 in consideration of the margin of the subsequent polishing process.

In the selective etching process for the field oxide layer 33 formed in FIG. 2D, only the field oxide layer 33 in the upper portion of the active region is removed to expose the amorphous silicon layer 31 in the upper portion of the active region.

In this case, the etching process terminates the etching by an end point detection (EPD) method using an amorphous silicon layer as an etch stop layer.

By performing such an etching process, it is possible to prevent insufficient etching or excessive etching due to an error that occurs when setting the polishing time during the polishing process of planarizing the subsequent field oxide film 33, and the time according to the field oxide film deposition variation. Since the process does not need to be modified, the process is simplified, and since the field oxide layer for etching margin is not left on the active region, the initial field oxide layer may be thinly formed.

In FIG. 2E, the CMP process is performed on the partially removed field oxide layer 33 on the active region to planarize the field oxide layer as shown in FIG. 2F.

Next, an oxygen injection process 33 is performed on the entire surface of the planarized field oxide layer 33, the pad nitride layer 25, and the amorphous silicon layer 31.                     

As shown in FIG. 2G, an oxide film 37 in which an upper portion of the amorphous silicon layer 31 is oxidized is formed by the oxygen injection process of FIG. 2F.

At this time, the oxygen injection step 33 is carried out in the amount of Rp, Dose = 1E10 ~ 1E16 (atoms / cm ² ) under the conditions of 0 ~ 30 ℃ and 60 ~ 130Kev.

When the amorphous silicon layer 31 is formed in accordance with the method of the present invention, and then the oxygen injection process 35 is performed, the oxide film 37 formed on the amorphous silicon layer 31 and the amorphous silicon layer 31 are shown in FIG. 2H. Since the field oxide film 33 is compatible with the field oxide film 33 to have one form, the field oxide film 33 is formed to the active region.

As shown in FIG. 2H, the pad nitride layer 25 and the pad oxide layer 23 may be formed by performing a selective dry etching process on the field oxide layer 33 formed to the active region until the semiconductor substrate 21 is exposed. Upon removal, a fully separated device isolation film is formed.

Subsequently, an additional wet cleaning process using phosphoric acid (H ₃ PO ₄ ) is performed to remove the remaining pad nitride film and the like on the semiconductor substrate on which the device isolation film is completely separated, and as shown in FIG. 2I. A device isolation film can be obtained.

That is, as shown in FIG. 2I, since the device isolation film obtained by the present invention is formed to the active region, even if both edges of the interface 33 of the device isolation film are excessively tinned, no mott is generated at the device isolation film interface. Therefore, since the hump characteristic can be prevented, deterioration of electrical characteristics such as a threshold current of a semiconductor device can be prevented, and a stable device can be manufactured.

As described above, in the method of the present invention, after forming amorphous silicon inside the trench, forming a planarized field oxide film to fill the trench, and performing an oxygen injection process, the device isolation film can be formed to the active region. In the subsequent cleaning process, no moat is generated at the interface between the device isolation layers, thereby preventing hump characteristics, thereby preventing deterioration of electrical characteristics such as a threshold current of the semiconductor device.

In addition, since the amorphous silicon layer is formed on the pad nitride film and in the trenches before the field oxide film is formed, various problems caused by the polishing time setting during the polishing process for planarizing the field oxide film can be prevented. In addition, since the deposition thickness of the initial field oxide film can be lowered, the simplification and uniformity of the polishing process can be improved.

Claims (10)

(a) sequentially forming a pad oxide film and a pad nitride film on the silicon substrate; (b) forming an ISO pattern and a trench by performing a photo / etch process on the pad oxide layer and the pad nitride layer; (c) depositing an amorphous silicon layer on the entire surface including the trench; (d) filling the trench by forming a field oxide layer on the entire surface of the substrate including the trench on which the amorphous silicon layer is deposited; (e) performing an etching process of removing the field oxide layer over the active region until the amorphous silicon layer is exposed; (f) planarizing the field oxide layer by performing a polishing process on the amorphous silicon layer and the field oxide layer using the pad nitride layer as an etch stop layer; (g) oxidizing an upper portion of the amorphous silicon layer by performing an oxygen injection process on the entire surface of the pad nitride layer, the amorphous silicon layer, and the field oxide layer; And (h) forming a device isolation film by removing the pad oxide film and the pad nitride film over the active region. The method of claim 1, The pad oxide film is a method of forming a device isolation film of a semiconductor device, characterized in that formed using a thermal oxidation process having a thickness of 50 ~ 200Å. The method of claim 1, And the pad nitride film is formed to have a thickness of 1000 to 2000 micrometers. The method of claim 1, The dry etching process for forming the trench in step (c) includes N ₂ 5-10 sccm, HBr 100-150 sccm, Cl ₂ 35-70 sccm and O ₂ 0∼ under 15-45 mT pressure and 430-700 Ws-100-400 Wb power conditions. A method of forming a device isolation film for a semiconductor device, characterized in that it is carried out with an etching gas of 10 sccm gas alone or mixed. The method of claim 1, The trench is a device isolation film forming method of a semiconductor device, characterized in that having a depth of 2500 ~ 4000Å and 70 to 90 degrees inclination on the basis of ISO pattern. The method of claim 1, Wherein the amorphous silicon layer is formed using at least one etching gas selected from the group consisting of SiH ₄ , Si ₂ H ₆ and SiH ₂ Cl ₂ . The method of claim 6, Wherein the amorphous silicon layer is formed by low pressure chemical vapor deposition (LP-CVD) at a temperature of 400 to 600 ° C. The method of claim 7, wherein The amorphous silicon layer is a device isolation film forming method of a semiconductor device, characterized in that 10 ~ 200 10 thickness. The method of claim 1, The field oxide film is a method of forming a device isolation film of a semiconductor device, characterized in that formed using a high density plasma (HDP) oxide film to a thickness of 4000 ~ 6000 4000 from the top of the ISO pattern. The method of claim 1, The method of forming an isolation layer of a semiconductor device, characterized in that the step of injecting oxygen in step (g) is performed at Rp, Dose = 1E10-1E16 (atoms / cm ² ) under the conditions of 0-30 ° C and 60-130Kev.

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