KR101160114B1 - A fabricating method of buried contact solar cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a recessed electrode type solar cell. In the present invention, first, the mask layer 110 ′ patterned in a predetermined shape is formed on the entire surface of the silicon substrate 100, and then an etching process is performed using the RIE method. At this time, the etching selectivity between the patterned mask layer 110 ′ and the silicon substrate 100 is appropriately adjusted according to process characteristics to perform an etching process. Then, in one RIE etching process, the front electrode groove G is formed in the silicon substrate 100, the patterned mask layer 110 ′ is removed, and the surface texturing of the silicon substrate 100 is performed. The performed silicon substrate 102 is formed. Thereafter, a high concentration of doped around the formed front electrode groove G and a low concentration of the surface-textured portion are formed to form an optional emitter layer 140 on the silicon substrate 102. After forming the anti-reflection film 150 on the formed selective emitter layer 140, the front electrode 162 is formed inside the front electrode groove G, and the rear electrode 164 is formed on the rear surface. . According to the present invention, it is possible to simultaneously form the front electrode groove G and the surface texturing on the silicon substrate 100 by one etching process, thereby simplifying the overall process.

Solar cell, RIE, Groove, Mask layer, Etch selectivity, Selective emitter

Description

Manufacturing method of recessed electrode solar cell {A FABRICATING METHOD OF BURIED CONTACT SOLAR CELL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell, and more particularly, to a method of manufacturing a recessed electrode type solar cell in which a groove for a front electrode is formed on a surface of a semiconductor substrate and an electrode is formed in the groove.

Recently, as the prediction of depletion of existing energy sources such as oil and coal is increasing, interest in alternative energy to replace them is increasing. Among them, solar cells are particularly attracting attention because they are rich in energy resources and have no problems with environmental pollution. Solar cells include solar cells that generate steam for rotating turbines using solar heat, and solar cells that convert photons into electrical energy using the properties of semiconductors. Refers to photovoltaic cells (hereinafter referred to as "solar cells").

The solar cell uses the photovoltaic effect of the semiconductor, and is made by combining a p-type semiconductor and an n-type semiconductor. When light enters a portion (pn junction) where the p-type semiconductor and the n-type semiconductor come into contact with each other, negative charges (electrons) and positive charges (holes) are generated within the semiconductor by the light energy. The electrons and holes generated by the light energy move to the n-type semiconductor side and the p-type semiconductor side by the internal electric field, and are collected at both electrode portions. Connecting these two electrodes with wires allows the current to flow and can be used as power from the outside.

Such solar cells can be classified into screen printing solar cells (hereinafter abbreviated as 'SPSC') and buried electrode solar cells (hereinafter abbreviated as 'BCSC') according to the electrode type. Can be.

The 'SPSC' is generally easy to manufacture, but the energy conversion efficiency is low. This is due to reflection at the metal electrode, resistance due to back current flow and high recombination rates of carriers in the deeply doped emitter regions. In addition, in the SPSC, the short-circuit current density and blue response characteristics are poor.

On the other hand, although the 'BCSC' has a disadvantage in that the manufacturing cost is more expensive than the 'SPSC' and the process is complicated, the research on 'BCSC' has recently been made due to the advantage of significantly improving the conversion efficiency.

1 shows a manufacturing process diagram of a general 'BCSC'. For convenience of description, a semiconductor substrate which is a manufacturing material of 'BCSC' will be described taking a crystalline silicon (Si) substrate as an example.

Referring to FIG. 1, first, a silicon substrate is cut to a required size, and a cutting and etching process for removing surface defects or damages of the silicon substrate generated during cutting is performed (S10).

A texturing process is performed on the silicon substrate after the etching process by using a reactive ion etching (RIE) method or a wet etching method (S12). When the texturing process is performed, the entire surface of the silicon substrate is formed to reduce reflection of incident light.

A first doping process is performed to form a low concentration emitter layer by doping the texturized silicon substrate with another type of dopant (dopant) (S14). Here, if the emitter layer is formed by doping at a high concentration, a high concentration of dopants present on the surface is present in the silicon substrate to form agglomerates, thereby reducing the life of the charge to increase the operating efficiency of the solar cell Can be degraded. That is why it forms a low concentration of emitter layers.

After the low concentration emitter layer is formed, a first by-product removal process for removing by-products generated when the low concentration emitter layer is formed is performed (S16). The by-product refers to Phosphor-Silicate Glass (PSG) generated when the n-type dopant is diffused on the p-type substrate or BSG (Boro-Silicate Glass) generated when the p-type dopant is diffused on the n-type substrate. Since the PSG or BSG serves to shield the current of the battery, it must be removed using an etching solution or the like to increase battery efficiency.

When the by-products are removed, a process of forming an anti-reflection film to prevent solar reflection on the low concentration emitter layer is performed (S18). The anti-reflection film also serves as a surface passivation layer of the silicon substrate.

After the anti-reflection film is formed, a process of forming a groove for the front electrode to the inside of the front surface of the silicon substrate is performed (S20). The groove is a space where a buried electrode is to be formed, and is formed using a laser or a cutting saw.

When the groove is formed, a second doping process is performed to form a high concentration emitter layer by doping a silicon substrate with another type of impurities on the groove surface to reduce contact resistance with the recessed electrode (S22). As such, forming an emitter layer having different concentrations through the first doping process and the second doping process is called a selective emitter layer.

After the high concentration emitter layer is formed, a second byproduct removal process for removing the by-products generated when the high concentration emitter layer is formed is performed (S24). The byproduct refers to PSG or BSG, as described above.

Subsequently, a process of forming an electrode using a metal paste is performed on all portions of the groove and the rear surface formed on the front surface of the silicon substrate (S26). The metal paste may be silver (Ag), aluminum (Al), or the like. In this case, screen printing may be used. The electrode formed on the front side serves to collect electrons generated by solar absorption, and the electrode formed on the back side increases the light reflection on the back side of the silicon substrate and prevents recombination of electrons.

A heat treatment process is performed such that the electrodes formed on the front and rear surfaces are electrically connected to the silicon substrate (S28). In this case, the metal paste is diffused by a predetermined thickness on the back surface of the silicon substrate to form a back surface field (BSF). The 'BSF' forms an electric field and prevents photoexcited electrons from moving to the rear surface of the silicon substrate.

Meanwhile, the formed front electrode may perform a front electrode function by itself, but may also be used as a seed layer. In this case, a process of forming a plating layer on the formed front electrode may be further performed (S30). This may reduce the resistance of the front electrode and increase the aspect ratio of the completed 'BCSC' substrate.

However, the conventional manufacturing method of 'BCSC' has the following problems.

First, when the groove is formed using a laser or a cutting saw, physical damage may be caused to the silicon substrate. In particular, when the groove is formed using a laser, recrystallization occurs on the surface and the inside of the substrate due to the high temperature. This causes a recombination of carriers generated by absorbing light, which increases the surface recombination rate and reduces the life time of the carrier.

Next, the first and second doping processes must be performed to form the selective emitter layer. This is a complicated process when forming a selective emitter layer, and thus there is a problem that the process cost increases.

In addition, the doping process typically performs a heat treatment process to diffuse impurities into the silicon substrate, and such a high temperature heat treatment process acts as a cause of lowering the quality of the silicon substrate. However, the 'BCSC', as described above, is performing the first and second doping processes, which causes a problem of further degrading the quality of the silicon substrate.

Accordingly, an object of the present invention is to solve the above problems, and to provide a method of manufacturing a recessed electrode type solar cell which prevents a reduction in the life time of a carrier when grooves are formed in a semiconductor substrate.

Another object of the present invention is to perform the groove forming process and the surface texturing process in one etching process.

Another object of the present invention is to simplify the process of forming a selective emitter layer.

According to a feature of the present invention for achieving the above object, the present invention provides a mask layer forming step of forming a mask layer on top of a semiconductor substrate; A mask layer patterning step of removing a portion of the formed mask layer to form a patterned mask layer; An etching step of simultaneously removing the patterned mask layer, surface texturing of the semiconductor substrate, and forming a groove for the front electrode by using an etching gas when the patterned mask layer is formed; An emitter layer forming step of forming an emitter layer by doping impurities on the semiconductor substrate when the etching step is completed; Forming an anti-reflection film on the formed emitter layer; An electrode forming step of forming a front electrode in a portion of the anti-reflection film corresponding to the groove for the front electrode, and forming a rear electrode on a rear front surface of the semiconductor substrate; And a heat treatment step of performing heat treatment such that the formed front and back electrodes are electrically connected to the semiconductor substrate.

The mask layer may be formed of an oxide-based or nitride-based dielectric material capable of controlling etching selectivity with the semiconductor substrate, and the mask layer may be formed by chemical vapor deposition (CVD). , Evaporation, sputtering, spin coating, inkjet, screen printing, or thermal oxidation.

In the mask layer patterning step, the mask layer may be any one of a photo-lithography method, an inkjet or screen printing method using an etching paste, and a laser ablation method. Is patterned by Alternatively, in a state in which the mask layer is not formed on the semiconductor substrate, the mask layer patterned in a predetermined shape may be directly formed on the semiconductor substrate. Here, the patterned mask layer is formed using any one of an inkjet method or a screen printing method.

The etching step is performed by a reactive ion etching (RIE) method or a plasma etching method, and is performed using at least one etching gas.

When one etching gas is used in the etching step, an etching gas having a low etching selectivity is used to etch both the semiconductor substrate and the patterned mask layer.

When two or more etching gases are used in the etching step, an etching gas in which only the semiconductor substrate is etched and an etching gas in which only the patterned mask layer is etched are used among etching gases having a high etching selectivity.

When two or more etching gases are used in the etching step, an etching gas having a high etching selectivity may be etched so that only the semiconductor substrate may be etched, and the semiconductor substrate and the patterned mask layer may be etched. An etching gas having a low etching selectivity is used.

The etching gas is F series or Cl series.

The emitter layer forming step may include applying a first impurity to the inside of the front electrode groove; and when the first impurity is applied, the first impurity applied by the heat treatment process may be around the front electrode groove. And diffusing doped to a high concentration and doping the entire surface of the semiconductor substrate at a low concentration by impurities vaporized in the applied first impurity to form a selective emitter layer on the semiconductor substrate. Impurities have a relatively higher concentration than the second impurity.

Alternatively, the emitter layer forming step may include applying a first impurity inside the groove for the front electrode; When the first impurity is applied, applying a second impurity on the entire surface of the semiconductor substrate and the upper part of the first impurity; When the second impurity is applied, the coated first impurity is diffused around the groove for the front electrode to be doped at a high concentration by the heat treatment process, and the applied second impurity is diffused to the front surface of the semiconductor substrate to have a low concentration. Forming a selective emitter layer on the semiconductor substrate, wherein the first impurity has a relatively higher concentration than the second impurity.

When the etching step is completed, sequentially forming a low concentration emitter layer and an anti-reflection film on the semiconductor substrate; Applying a front electrode paste made of a high concentration of impurities and a metal paste to a portion of the formed anti-reflection film corresponding to the groove for the front electrode, and applying a back electrode paste made of a metal paste to the entire back surface of the semiconductor substrate; ; And forming a front electrode with a metal paste included in the front electrode paste and forming a back electrode with a back electrode paste by performing heat treatment while the front electrode / back electrode paste is coated. When the heat treatment is performed, a high concentration of impurities contained in the front electrode paste is diffused into the semiconductor substrate to form a high concentration of emitter layer around the front electrode groove.

According to the method of manufacturing a recessed electrode solar cell of the present invention having such a configuration, a reactive ion etching (RIE) method or a plasma etching method is performed in a state in which a mask layer patterned in a predetermined shape is formed on a semiconductor substrate. The etching process is performed by a plasma etching method. In this case, the etching gas used in the etching process is used in the same or at least two or more etching gases are sequentially used. Then, in one etching process, the patterned mask layer removing process, the surface texturing process of the semiconductor substrate, and the groove forming process are simultaneously performed. As described above, since the etching process is performed using an etching gas used in an RIE method or a plasma etching method, a carrier life time generated when a groove is formed using a laser as in the related art. (life time) is effective in preventing the phenomenon.

Furthermore, in one etching process, the patterned mask layer removing process, the surface texturing process of the semiconductor substrate, and the groove forming process may be simultaneously performed, thereby simplifying the process.

In addition, by using one of screen printing, auto-doping, and self-doping methods during the doping process, the effect of forming a selective emitter layer in one doping process can be achieved. There is.

Therefore, in manufacturing the recessed electrode type solar cell, the entire process can be simplified, thereby reducing the process cost, and eventually, lowering the production cost can be expected.

In addition, during the doping process, by performing any one of screen printing, auto-doping, and self-doping methods, a diffusion process, that is, a heat treatment process is performed only once, thereby There is an effect that can prevent the degradation of quality.

Hereinafter, a method of manufacturing a depressed electrode solar cell according to the present invention will be described in detail with reference to a preferred embodiment shown in the accompanying drawings. In the embodiment of the present invention, a crystalline silicon (Si) substrate as a semiconductor substrate as a material for manufacturing a solar cell will be described as an example.

2 is a longitudinal sectional view of the manufacturing method of the recessed electrode solar cell according to the preferred embodiment of the present invention, Figure 3 is a process for forming the surface texturing and groove in the process of Figure 2 according to another embodiment The process diagram is shown in longitudinal section, in FIG. 4 a process diagram in accordance with another embodiment of the process of forming the surface texturing and grooves in FIG. 2 is shown in a longitudinal sectional view, and in FIG. 5 the selective emitter in the process of FIG. A process diagram in accordance with another embodiment of a process for forming a layer is shown in a longitudinal sectional view.

Referring to FIG. 2, a saw damage etching process is first performed to cut a silicon substrate 100 to a required size and remove bonding and damage of a surface thereof. This is shown in Figure 2 (a).

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와 같은 산화물(Oxide) 계열 또는 질화물(Nidtride) 계열의 유전체 물질이 사용되는 것이 좋다. 상기 식각 선택비는 식각 작업시 두 물질이 식각되는 식각율의 비를 말한다. 그리고 상기 마스크 층(110)은 화학증착(Chemical Vapor Deposition: CVD), 증류(evaporation), 스퍼터링(sputtering), 스핀 코팅(Spin Coating), 잉크젯(Inkjet), 스크린 프린팅, 열 산화(thermal oxidation) 등의 방법에 의해 형성된다.Next, as shown in FIG. 2B, a process of depositing a mask layer 110 on the entire surface of the etched silicon substrate 100 is performed. The mask layer 110 can easily control etching selectivity with the silicon substrate 100.

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An oxide-based or nitride-based dielectric material, such as, may be used. The etching selectivity refers to a ratio of etching rates at which two materials are etched during an etching operation. The mask layer 110 may include chemical vapor deposition (CVD), evaporation, sputtering, spin coating, inkjet, screen printing, thermal oxidation, and the like. It is formed by the method.

When the mask layer 110 is formed, as shown in FIG. 2C, the mask layer 110 corresponding to a portion of the front surface of the silicon substrate 100 on which a groove for a front electrode is to be formed is formed. A patterning process is performed to remove a portion to form a patterned mask layer 110 ′. The patterning process may be performed by a photo-lithography method, an inkjet or screen printing method using an etching paste, or a laser ablation method using a laser.

Here, in the process of forming the patterned mask layer 110 ′, as described above, the patterning process may be performed while the mask layer 110 is formed in all regions of the entire surface of the silicon substrate 100. By using an inkjet or screen printing method, the mask layer 110 ′ patterned in a predetermined shape may be directly formed on the silicon substrate 100 without a separate patterning process.

When the patterned mask layer 110 ′ is formed, an etching process is performed by using a reactive ion etching (RIE) method or a plasma etching method. In this embodiment, the etching process for forming the front electrode groove G, the patterned mask layer 110 ′, and the surface texturing of the silicon substrate 100 are simultaneously performed in one etching process. This can be done by three methods. Three methods are shown in FIGS. 2 (d), 3 and 4.

First, the first method will be described with reference to FIG. 2 (d). This method is performed by using different etching gas (Etching Gas) according to each process to ensure an optimized etching process. In this case, only one of the patterned mask layer 110 ′ and the silicon substrate 100 may be etched using an etching gas having a high etching selectivity. In this case, the etching gas may be a reaction gas such as F-based or Cl-based. However, the etching gas is not necessarily the same, and the etching gas has a high etching selectivity such that only one of the patterned mask layer 110 ′ and the silicon substrate 100 may be etched. It does not matter if it is a reaction gas.

Referring to FIG. 2 (d), only the silicon substrate 100 starts an etching process using an etching gas that can be etched.

Then, as shown in FIG. 2 (d ′), only the portion of the silicon substrate 100 that is not in contact with the patterned mask layer 110 ′ is selectively etched to form the groove G for the front electrode.

After the groove G for the front electrode is formed to a desired depth, as shown in FIG. 2D, only the patterned mask layer 110 ′ is changed into an etching gas that can be etched to form the patterned mask layer ( 110 '). Of course, it may be performed by adjusting the mixing ratio of the etching gas.

When the patterned mask layer 110 ′ is removed, the entire surface of the silicon substrate 100 is textured by changing the silicon substrate 100 into an etchable gas. Then, as shown in FIG. 2 (d '' '), the substrate surface area is increased and the structure is reduced to reduce the reflection of light incident on the substrate surface. Hereinafter referred to as a textured silicon substrate 102.

Next, a second method will be described with reference to FIG. 3. This method may be implemented when the patterned mask layer 110 ′ is made of a material capable of appropriately adjusting the etch selectivity with the silicon substrate 100. This can save process time compared to the first method.

Referring to FIG. 3, in a state in which a patterned mask layer 110 ′ is formed on the silicon substrate 100 as shown in FIG. 3 (1), only the silicon substrate 100 may be etched using an etching gas. Start the process. Then, only the portion of the silicon substrate 100 that is not in contact with the patterned mask layer 110 ′ is selectively etched to start to form the groove G ′ for the front electrode. In this case, the front electrode groove G 'is formed to have a predetermined depth as shown in FIG. 3 (m'). This is to prevent the grooves for the front electrode should be sufficiently formed at a desired depth at the same time when the etching process is completed, but may be insufficiently formed. This difference may occur because the etching degree of the patterned mask layer 110 ′ is relatively fast. The etching degree may vary depending on the material, the thickness, the etching selectivity, the etching rate, and the like of the patterned mask layer 110 ′. Therefore, the front electrode groove G 'having the predetermined depth is preferably formed in consideration of the degree of etching of the patterned mask layer 110'.

When the groove G 'for the front electrode having the predetermined depth is formed, the etching mask is changed to an etching gas having a low etching selectivity or the etching gas so that both the patterned mask layer 110' and the silicon substrate 100 can be etched. Adjust the mixing ratio of to continue the etching process. As a result, all of the patterned mask layer 110 ′ is removed, as shown in FIG. 3 (m ″), and the front electrode groove G ″ having a deeper depth is formed in the silicon substrate 100.

After all of the patterned mask layer 110 'is etched and removed, the etching process is further performed using the current etching gas. Then, as illustrated in FIG. 3 (m ′ ″), a textured silicon substrate 102 is formed and at the same time a groove G for a front electrode having a desired depth is formed in the textured silicon substrate 102.

Next, a third method will be described with reference to FIG. 4. This method can be performed when the patterned mask layer 110 'is optimally formed in consideration of the degree of etching. That is, the process of removing the patterned mask layer 110 ′ and forming the groove G for the front electrode are simultaneously started. Thus, while the first method and the second method are performed by changing the etching gas, the third method performs the etching process using the same etching gas.

Referring to FIG. 4, first, in a state in which a patterned mask layer 110 ′ is formed on the silicon substrate 100 as shown in FIG. 4 (n), the patterned mask layer 110 ′ and the silicon substrate 100 are formed. The etching process is performed using an etching gas having a low etching selectivity so that all can be etched.

Then, as shown in FIG. 4 (o), the patterned mask layer 110 ′ is removed, and the surface of the silicon substrate 100 is textured, and the silicon substrate having the front electrode groove G having a desired depth is formed. 102 is formed.

As described above, in the present invention, the mask layer 110 ′ is removed, the surface texturing process and the front electrode are processed in one etching process using the etching selectivity of the etching gas used in the RIE method or the plasma etching method. It is possible to carry out the step of forming the grooves G for melting at the same time.

Referring back to FIG. 2, after the etching process is completed, a doping process is performed to form a selective emitter layer 140 on the textured silicon substrate 102. The selective emitter layer 140 may be implemented by any one of a screen printing method, an auto-doping method, and a self-doping method. The self-doping method is different from the process of forming the selective emitter layer 140 will be described in detail below. In the present embodiment, for convenience of description, the screen printing method is omitted and the process of forming the selective emitter layer 140 using the autodoping method will be described.

First, as shown in FIG. 2 (e), the first impurity 120 is applied only to a region where the front electrode groove G is formed in the textured silicon substrate 102 using screen printing or inkjet. do. At this time, the first impurity 120 is preferably higher than the upper portion of the groove (G) for the front electrode. The first impurity 120 has a darker concentration than the second impurity 130 described below. This is also called high concentration impurity.

As shown in FIG. 2 (f), a second impurity 130 is coated on the entire surface of the textured silicon substrate 102 and on the coated first impurity 120. The second impurity 130 has a relatively lighter concentration than the first impurity 120. This is also called low concentration impurity. The second impurity 130 is applied by a method such as spray, spin on dopant, screen printing, inkjet, or the like.

Then, the heat treatment process, as shown in Figure 2 (g), the first impurity 120 is diffused around the groove (G) for the front electrode to form a high concentration of the emitter layer 142, The second impurity 130 is diffused to the surface of the textured silicon substrate 102 to form a low concentration emitter layer 144. Accordingly, an optional emitter layer 140 is formed on the textured silicon substrate 102. In this case, since the second impurity 130 also serves to prevent the first impurity 120 from vaporizing, the second impurity 130 may be formed in a portion other than a region where the first impurity 120 is coated on the textured silicon substrate 102. The periphery is prevented from being heavily doped.

On the other hand, the process of applying the second impurity 130, that is, Figure 2 (f) does not necessarily need to be performed. In this case, during the heat treatment process, the first impurity 120 is diffused onto the front electrode groove G, and the periphery of the front electrode groove G is doped at a high concentration. The surface of the substrate 102 is to be lightly doped. As a result, an optional emitter layer 140 is formed on the textured silicon substrate 102.

And in the selective emitter layer 140 formed by the autodoping method, the high concentration emitter layer 142 is doped to have a sheet resistance of 90 ohm / squar or more, and the low concentration emitter layer 144 ) Is preferably doped to have a sheet resistance of 40 ohms / squar or less.

After the selective emitter layer 140 is formed, a process of removing by-products generated when the selective emitter layer 140 is formed, although not shown in the drawing, is performed. The by-product refers to Phosphor-Silicate Glass (PSG) generated when the n-type dopant is diffused on the p-type substrate or BSG (Boro-Silicate Glass) generated when the p-type dopant is diffused on the n-type substrate. Since the PSG or BSG serves to shield the current of the battery, it must be removed to increase battery efficiency.

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등과 같이 1.1 ~ 2.5 사이의 굴절율을 가지는 유전체 물질로 형성하고, 이는 화학증착(CVD), 스퍼터링(sputtering), 열 산화(thermal oxidation), 스프레이(Spray) 등의 방법에 의해 형성된다. 이는 도 2(h)에 도시되어 있다. 이러한 반사방지막(150)은 실리콘 기판의 표면 보호막(Passivation) 역할도 한다.After the by-products are removed, an anti-reflection film 150 is formed on the selective emitter layer 140 to prevent solar reflection. The anti-reflection film 150

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It is formed of a dielectric material having a refractive index between 1.1 and 2.5, and the like, and is formed by a method such as chemical vapor deposition (CVD), sputtering, thermal oxidation, spray, or the like. This is shown in Figure 2 (h). The anti-reflection film 150 also serves as a surface passivation layer of the silicon substrate.

Subsequently, as shown in FIG. 2 (i), the front electrode 162 is formed in the groove G for the front electrode formed on the front surface of the textured silicon substrate 102. More precisely, the front electrode 162 is formed on the anti-reflection film 150 formed in the front electrode groove G. The rear electrode 164 is formed on all portions of the rear surface of the textured silicon substrate 102. As the front electrode 162 and the back electrode 164, metal pastes such as nickel (Ni), silver (Ag), chromium (Cr), and aluminum (Al) are used. In this case, screen printing, stencil, inkjet, aerosol jet, etc. may be performed by a method. The front electrode 162 collects electrons generated by solar absorption, and the back electrode 164 increases light reflection on the back surface of the textured silicon substrate 102 and prevents recombination of electrons. do.

The heat treatment process is performed at a high temperature of 700 degrees or more so that the front electrode 162 and the back electrode 164 are electrically connected to the textured silicon substrate 102. Then, as shown in FIG. 2 (j), the metal atoms in the front electrode 162 penetrate into the antireflection film 150 formed in the front electrode groove G, and thus the antireflection film 150 is converted into the front electrode 162 '. Will be. Accordingly, the front electrode 162 'is bonded to the silicon substrate to form a ohmic contact. In addition, the back electrode 164 diffuses the metal paste of the back electrode 164 to the rear surface of the textured silicon substrate 102 by a predetermined thickness to form a back surface field (BSF) 166. do. The back surface field layer 166 forms an electric field to prevent photoexcited electrons from moving to the back surface of the textured silicon substrate 102.

On the other hand, the front electrode 162 ′ formed in the form of an ohmic contact may itself function as a front electrode, but may also be used as a seed layer. In this case, a plating process of forming the plating layer 170 on the formed front electrode 162 'may be additionally performed to lower the resistance of the front electrode 162' and increase the aspect ratio. At this time, the plating layer 170, as shown in Figure 2 (k), may be formed of one plating layer 170, but is not necessarily so, it may be formed in a plurality. The plating layer 170 may be a plating material such as copper (Cu), tin (Sn), chromium (Cr), silver (Ag), nickel (Ni), or a mixture of the plating materials.

Meanwhile, the selective emitter layer in the process of FIG. 2 may be formed by a self-doping method. This will be described with reference to FIG. Here, the selective emitter layer before forming the selective emitter layer, that is, the saw damage etching process, the mask layer forming process, the patterned mask layer forming process and the etching process are the same as in FIG. Only the process of forming the film will be described.

Referring to FIG. 5, a process of doping at a low concentration by using impurities of a different type from the textured silicon substrate 102 is performed on the grooves G for the front electrode of the textured silicon substrate 102 and all portions of the front surface. do. Then, as shown in FIG. 5 (p), a lightly doped emitter layer 210 is uniformly formed around and around the front electrode groove G of the textured silicon substrate 102.

Thereafter, as shown in FIG. 5 (q), an anti-reflection film 220 is formed on the low concentration emitter layer 210 to prevent sunlight reflection. The anti-reflection film 220 is the same as the anti-reflection film 150 of FIG. 2.

When the anti-radiation film 220 is formed, as shown in FIG. 5 (r), the front electrode paste 232 is applied only to a portion corresponding to the front electrode groove G in the anti-radiation film 220. Perform the process. In this case, the front electrode paste 232 refers to a paste in which a high concentration of impurities and a metal paste are combined. Then, the metal paste 234 for the rear electrode is applied to all parts of the back surface of the textured silicon substrate 102.

Then, when the heat treatment process is performed at a high temperature of 700 degrees or more, a high concentration of impurity atoms and metal atoms included in the front electrode paste 232 penetrate into the antireflection film 220 formed inside the front electrode groove G, and eventually the The high concentration of impurity atoms diffuse around the front electrode groove G to form the high concentration emitter layer 240. In addition, the anti-reflection film formed in the front electrode groove G by the metal atom is converted into the front electrode 232 ′. That is, the selective emitter layer 250 is formed and the front electrode 232 ′ is formed in the form of a ohmic contact in the groove G for the front electrode. In this case, a back surface field (BSF) 236 is formed on the back surface of the textured silicon substrate 102.

Meanwhile, as described above, when the front electrode 232 'is used as a seed layer, a plating process of forming the plating layer 260 on the formed front electrode 232' is additionally performed.

As described above, the present invention, which is described in the above embodiment, uses a RIE method or a plasma etching method to form a groove G for the front electrode in a single etching process, a surface texturing process of the silicon substrate 100, and The patterned mask layer 110 'removal process may be simultaneously performed, and the selective emitter layer may be formed using any one of autodoping, screen printing, and self-doping methods, thereby simplifying the overall process. This has the advantage of reducing costs.

Although described with reference to the illustrated embodiment of the present invention as described above, this is merely exemplary, those skilled in the art to which the present invention pertains various modifications without departing from the spirit and scope of the present invention. It will be apparent that other embodiments may be modified and equivalent. Therefore, the true scope of the present invention should be determined by the technical idea of the appended claims.

1 is a process chart of the manufacturing method of a typical recessed electrode solar cell.

Figure 2 is a longitudinal cross-sectional view of the process diagram of the manufacturing method of the recessed electrode solar cell according to a preferred embodiment of the present invention.

3 is a longitudinal sectional view of a process diagram according to another embodiment of the process of forming the surface texturing and grooves in the process of FIG.

4 is a longitudinal sectional view of a process diagram according to another embodiment of the process of forming the surface texturing and grooves in the process of FIG.

5 is a longitudinal cross-sectional view of a process diagram according to another embodiment of a process for forming a selective emitter layer of the process of FIG.

* Description of the symbols for the main parts of the drawings *

100 silicon substrate 102 textured silicon substrate

110: mask layer 110 ': patterned mask layer

G: Groove for front electrode 120: High concentration impurity

130: low concentration impurity 140: selective emitter layer

142 low concentration emitter layer 144 high concentration emitter layer

150: antireflection film 162: front electrode

164 back electrode 166 back field layer (BSF)

170: plating layer

Claims (12)

A mask layer forming step of forming a mask layer on the semiconductor substrate; A mask layer patterning step of removing a portion of the formed mask layer to form a patterned mask layer; An etching step of simultaneously removing the patterned mask layer, surface texturing of the semiconductor substrate, and forming a groove for the front electrode by using an etching gas when the patterned mask layer is formed; An emitter layer forming step of forming an emitter layer by doping impurities on the semiconductor substrate when the etching step is completed; Forming an anti-reflection film on the formed emitter layer; An electrode forming step of forming a front electrode in a portion of the anti-reflection film corresponding to the groove for the front electrode, and forming a rear electrode on a rear front surface of the semiconductor substrate; And And a heat treatment step of performing heat treatment such that the formed front electrode and the rear electrode are electrically connected to the semiconductor substrate. The method of claim 1, The mask layer may be formed of an oxide-based or nitride-based dielectric material capable of controlling etching selectivity with the semiconductor substrate. The mask layer is subjected to any one of chemical vapor deposition (CVD), evaporation, sputtering, spin coating, inkjet, screen printing, and thermal oxidation. Method of manufacturing a recessed electrode type solar cell, characterized in that formed by. The method of claim 2, wherein in the mask layer patterning step, The mask layer is patterned by any one of a photo-lithography method, an inkjet or screen printing method using an etching paste, and a laser ablation method using a laser. Method of manufacturing a recessed electrode solar cell. The method of claim 1, wherein the mask layer patterning step, In a state in which the mask layer is not formed on the semiconductor substrate, a mask layer patterned in a predetermined shape is directly formed on the semiconductor substrate, The patterned mask layer is a method of manufacturing a recessed electrode type solar cell, characterized in that formed using any one of the inkjet (Inkjet) method or screen printing method. The method of claim 1, wherein the etching step, By a reactive ion etching (RIE) method or a plasma etching method, Method of manufacturing a recessed electrode type solar cell, characterized in that carried out using at least one etching gas. The method of claim 5, When using one etching gas in the etching step, manufacturing a recessed electrode type solar cell, characterized in that using an etching gas having an etching selectivity (Etching Selectivity) that can be etched both the semiconductor substrate and the patterned mask layer Way. The method of claim 5, When using two or more etching gas in the etching step, the method of manufacturing a recessed electrode type solar cell, characterized in that using the etching gas is etched only the semiconductor substrate, and the etching mask is etched only the patterned mask layer. The method of claim 5, When two or more etching gases are used in the etching step, an etching gas having an etching selectivity in which only the semiconductor substrate can be etched, and an etching in which both the semiconductor substrate and the patterned mask layer can be etched Method of manufacturing a recessed electrode type solar cell, characterized in that using the etching gas having an etching selectivity (Etching Selectivity). The method according to any one of claims 5 to 8, The etching gas is a method of manufacturing a recessed electrode type solar cell, characterized in that the F series or Cl series. The method of claim 1, wherein the emitter layer forming step, Coating a first impurity inside the groove for the front electrode; and When the heat treatment process is performed after the first impurity is applied, the coated first impurity is diffused around the groove for the front electrode to be doped at a first concentration, and the impurities are vaporized in the applied first impurity. A surface of the semiconductor substrate is doped to a second concentration to form a selective emitter layer on the semiconductor substrate; The first concentration is a manufacturing method of a recessed electrode type solar cell, characterized in that having a concentration relatively higher than the second concentration. The method of claim 1, wherein the emitter layer forming step, Applying a first impurity in the groove for the front electrode; When the first impurity is applied, applying a second impurity on the entire surface of the semiconductor substrate and the upper part of the first impurity; And When the second impurity is applied, the applied first impurity is diffused around the groove for the front electrode to be doped at a first concentration by the heat treatment process, and the applied second impurity is diffused to the front surface of the semiconductor substrate. And doped to a second concentration to form a selective emitter layer on the semiconductor substrate; The first concentration is a manufacturing method of a recessed electrode type solar cell, characterized in that having a concentration relatively higher than the second concentration. The method of claim 1, When the etching step is completed, sequentially forming an emitter layer and an anti-reflection film on the semiconductor substrate; Applying a front electrode paste made of impurities and a metal paste to a portion of the formed anti-reflection film corresponding to the groove for the front electrode, and applying a back electrode paste made of a metal paste to the front surface of the semiconductor substrate; And Performing a heat treatment while the front electrode paste and the back electrode paste are coated to form a front electrode with a metal paste included in the front electrode paste and a back electrode with a back electrode paste; , When the heat treatment is performed, impurities contained in the front electrode paste diffuse into the semiconductor substrate, and the inside of the front electrode groove is relatively larger than the emitter layer formed around the front electrode groove and all parts of the front surface of the semiconductor substrate. Method for manufacturing a recessed electrode type solar cell, characterized in that formed of a high concentration of emitter layer.

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