KR101147115B1 - Chip comprising inclined conductive bump and its fabrication method and fabrication method of electronic application having the same - Google Patents

Chip comprising inclined conductive bump and its fabrication method and fabrication method of electronic application having the same Download PDF

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Publication number
KR101147115B1
KR101147115B1 KR1020100042954A KR20100042954A KR101147115B1 KR 101147115 B1 KR101147115 B1 KR 101147115B1 KR 1020100042954 A KR1020100042954 A KR 1020100042954A KR 20100042954 A KR20100042954 A KR 20100042954A KR 101147115 B1 KR101147115 B1 KR 101147115B1
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South Korea
Prior art keywords
chip
conductive bumps
inclined conductive
pad
conductive bump
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KR1020100042954A
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Korean (ko)
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KR20110123456A (en
Inventor
유중돈
김선락
박아영
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한국과학기술원
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Priority to KR1020100042954A priority Critical patent/KR101147115B1/en
Publication of KR20110123456A publication Critical patent/KR20110123456A/en
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Publication of KR101147115B1 publication Critical patent/KR101147115B1/en

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Abstract

이 발명은 표면에 일정한 각도로 경사진 전도성 범프를 갖는 칩에 관한 것이다. 이 발명은 경사진 전도성 범프가 접합 과정에서 압력에 의해 일정한 방향으로 변형됨에 따라 전도성 범프 간의 전기적 단락을 방지하고, 변형된 전도성 범프의 탄성 복원력에 의해 전기적인 접촉을 유지하며, 경사진 전도성 범프를 웨이퍼 레벨(상태)에서 가공함에 따라 생산성이 높은 장점이 있다.This invention relates to a chip having conductive bumps inclined at an angle to a surface. The present invention prevents electrical shorts between conductive bumps as the inclined conductive bumps are deformed in a constant direction by pressure in the bonding process, maintains electrical contact by the elastic restoring force of the deformed conductive bumps, and inclines the conductive bumps. There is an advantage of high productivity due to processing at the wafer level (state).

Description

경사진 전도성 범프를 갖는 칩 및 그 제조방법과, 칩을 구비한 전자부품의 제조방법{CHIP COMPRISING INCLINED CONDUCTIVE BUMP AND ITS FABRICATION METHOD AND FABRICATION METHOD OF ELECTRONIC APPLICATION HAVING THE SAME}Chip having inclined conductive bumps and manufacturing method thereof, and manufacturing method of electronic component having chip {CHIP COMPRISING INCLINED CONDUCTIVE BUMP AND ITS FABRICATION METHOD AND FABRICATION METHOD OF ELECTRONIC APPLICATION HAVING THE SAME}

이 발명은 경사진 전도성 범프를 갖는 칩 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 경사진 전도성 범프의 구조를 단순화함에 따라 웨이퍼 레벨(상태)에서 경사진 전도성 범프를 보다 효율적으로 제조할 수 있어 생산성을 향상시킬 수 있는 경사진 전도성 범프를 갖는 칩 및 그 제조방법에 관한 것이다. 또한, 이 발명은 상기의 경사진 전도성 범프를 갖는 칩을 기판에 접합하여 구성한 전자부품 및 그 제조방법에 관한 것이기도 하다.
The present invention relates to a chip having an inclined conductive bump and a method of manufacturing the same, and more particularly, by simplifying the structure of the inclined conductive bump, it is possible to more efficiently manufacture the inclined conductive bump at the wafer level (state). The present invention relates to a chip having an inclined conductive bump capable of improving productivity and a method of manufacturing the same. The present invention also relates to an electronic component formed by joining a chip having the inclined conductive bump to a substrate and a manufacturing method thereof.

접착제를 이용하여 전자부품을 접합함에 있어서는 이방성 전도 필름(Anisotropic Conductive Film, 이하 ACF)이 사용되고 있다. ACF는 직경이 3~5㎛인 미세한 전도성 입자가 접착제 필름의 내부에 균일하게 분포된 구조를 갖는다. 전도성 입자는 구형 폴리머의 표면에 니켈과 금으로 구성된 금속층이 코팅된 구조로서, 주로 열과 압력을 가하는 열압착 방법으로 접합된다. 한편, 전도성 입자는 접합시에 전자부품과 기판의 전극 역할을 하는 돌출된 금속패드(pad) 사이에 밀착되어 전기적 연결부를 형성한다. ACF는 접착제를 이용하여 접합하기 때문에, 디스플레이, 통신 장비, 반도체 칩 등과 같은 다양한 전자제품의 저온 접합에 널리 사용되고 있다.Anisotropic conductive film (ACF) is used to join an electronic component using an adhesive agent. ACF has a structure in which fine conductive particles having a diameter of 3 to 5 μm are uniformly distributed in the interior of the adhesive film. The conductive particles are coated with a metal layer made of nickel and gold on the surface of the spherical polymer, and are bonded by a thermocompression method that mainly applies heat and pressure. On the other hand, the conductive particles are in close contact between the protruding metal pad (Pad) that serves as an electrode of the electronic component and the substrate at the time of bonding to form an electrical connection. Since ACF is bonded using an adhesive, it is widely used for low temperature bonding of various electronic products such as displays, communication equipment, semiconductor chips, and the like.

그런데, 최근 전자부품의 패드 사이의 간격이 감소하면서 불균일하게 분포된 ACF의 전도성 입자에 의해 패드 사이에 전기적 단락이 발생하거나, 패드에 압착된 전도성 입자의 개수가 일정하지 않음에 따라 전기 전도도가 불균일한 문제점이 발생하고 있다. 이러한 ACF의 문제점은 접합과정에서 압력이 가해지면 접착제 내부에 분포된 전도성 입자들이 이동하기 때문에 발생한다.However, in recent years, as the spacing between pads of electronic components decreases, electrical shorts occur between pads due to non-uniformly distributed ACF particles, or the number of conductive particles pressed on the pads is not constant, resulting in uneven electrical conductivity. One problem is occurring. This problem of ACF occurs because the conductive particles distributed in the adhesive move when pressure is applied during the bonding process.

ACF의 문제점을 보완하기 위하여 전도성 입자와 유사한 구조의 전도성 폴리머 범프를 칩의 패드에 고정시키는 방법들이 제안되었으며, 이와 같은 방법에 의해 폴리머 범프가 칩의 패드에 고정되면 접합과정에서 폴리머 범프가 이동하지 않고 전기 전도도가 일정하며, 저항을 비교적 정확하게 예측할 수 있다는 장점이 있다.In order to solve the problem of ACF, a method of fixing a conductive polymer bump having a structure similar to a conductive particle to a pad of a chip has been proposed. When the polymer bump is fixed to the pad of the chip by this method, the polymer bump does not move during the bonding process. The electrical conductivity is constant and the resistance can be predicted relatively accurately.

미국특허 제5,578,527호의 "Connection construction and method of manufacturing the same", 미국특허 제5,707,902호의 "Composite bump structure and methods of fabrication", 미국특허 제5,508,228호의 "Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and method for forming same", 미국특허 제5,783,465호의 "Compliant bump technology"에는, 칩의 패드에 하나의 폴리머 범프를 형성하고 폴리머 범프의 표면에 금속층을 코팅한 범프 구조가 개시되어 있다. 그리고, 미국특허 제6,972,490호의 "Bonding structure with compliant bumps"에는 폴리머 범프의 균열을 방지하기 위하여 스토퍼(stopper)를 설치하는 구조가 개시되어 있다. 또한, 연구논문 "A new anisotropic conductive film with arrayed conductive particles, IEEE, 1996"과, "Development of 0.025mm pitch anisotropic conductive film, IEEE, 1999"과, "Development of wafer level anisotropic conductive film for flip-chip interconnection, IEEE, 2004"에서는 전기도금을 이용하여 만든 금속과 수직으로 된 금속 범프를 제안하고 있다. 한편, 기술보고서(Technology News Line, No.24, 2007년 11월)에는 Seiko-Epson사에서 개발한 칩의 패드 주위에 스트립 형상의 전도성 폴리머 범프인 레진 코어드 범프(resin cored bump)를 제조하는 방법에 대해 공개되어 있다."Connection construction and method of manufacturing the same" in U.S. Patent 5,578,527, "Composite bump structure and methods of fabrication" in U.S. Patent 5,707,902, "Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and U.S. Patent 5,508,228" "Compliant bump technology" of U.S. Patent No. 5,783,465 discloses a bump structure in which one polymer bump is formed on a pad of a chip and a metal layer is coated on the surface of the polymer bump. In addition, "Bonding structure with compliant bumps" of US Pat. No. 6,972,490 discloses a structure for installing a stopper to prevent cracking of polymer bumps. In addition, the research paper "A new anisotropic conductive film with arrayed conductive particles, IEEE, 1996", "Development of 0.025mm pitch anisotropic conductive film, IEEE, 1999", and "Development of wafer level anisotropic conductive film for flip-chip interconnection , IEEE, 2004 "propose a metal bump perpendicular to the metal made by electroplating. On the other hand, a technology report (Technology News Line, No. 24, November 2007) describes the production of resin cored bumps, which are strip-shaped conductive polymer bumps, around pads of chips developed by Seiko-Epson. The method is open to the public.

그러나 상기의 특허문헌 및 기술문헌의 방법들은, 칩의 패드 표면에 ACF와 동일한 구조의 전도성 폴리머 범프를 형성하기 위해, 폴리머 범프를 형성하고 폴리머 범프의 표면(상면 및 양측면)에 금속층을 코팅한 후 전도성 폴리머 범프를 가공하기 때문에 리소그래피와 에칭공정을 여러 번 사용해야 하며, 이로 인하여 제조공정이 복잡하고 생산비용이 증가할 뿐만 아니라 높은 가공 정밀도가 요구되는 단점이 있다. 한편, 전기도금을 통해 기판과 수직하게 형성된 금속 범프의 경우에는 금속 범프의 양측면을 금속층으로 균일하게 코팅하기가 어렵고, 접착시에 큰 압력이 가해지므로 그에 따른 공정 온도가 증가하는 단점이 있으며, 필름 형태의 ACF를 접착함에 따라 접촉 저항이 증가하는 단점이 있다. 또한, 기존에는 전도성 범프가 수직하게 형성됨에 따라, 전도성 범프에 수직방향의 압력이 가해지면 전도성 범프의 변형방향을 예측할 수 없으므로 전도성 범프 간의 전기적인 단락이 발생할 수 있는 단점이 있다.
However, the methods of the above patent documents and technical documents, in order to form a conductive polymer bump of the same structure as the ACF on the pad surface of the chip, after forming a polymer bump and coating a metal layer on the surface (top and both sides) of the polymer bump Due to the processing of the conductive polymer bumps, the lithography and etching processes have to be used many times, which leads to complicated manufacturing processes, increased production costs, and high processing precision. On the other hand, in the case of metal bumps formed perpendicular to the substrate through electroplating, it is difficult to uniformly coat both sides of the metal bumps with a metal layer, and a large pressure is applied during adhesion, which increases the process temperature. There is a disadvantage that the contact resistance increases as the ACF is bonded. In addition, since the conductive bumps are vertically formed in the related art, when the pressure in the vertical direction is applied to the conductive bumps, the deformation direction of the conductive bumps cannot be predicted, thereby causing an electrical short circuit between the conductive bumps.

따라서, 이 발명은 앞서 설명한 바와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 경사진 전도성 범프의 구조를 단순화함에 따라 웨이퍼 레벨(상태)에서 경사진 전도성 범프를 보다 효율적으로 제조할 수 있어 생산성을 향상시킬 수 있는 경사진 전도성 범프를 갖는 칩 및 그 제조방법을 제공하는 데 그 목적이 있다. Accordingly, the present invention has been made to solve the problems of the prior art as described above, and by simplifying the structure of the inclined conductive bumps, it is possible to more efficiently manufacture the inclined conductive bumps at the wafer level (state), thereby improving productivity. It is an object of the present invention to provide a chip having an inclined conductive bump and a method of manufacturing the same.

또한, 이 발명은 상기의 경사진 전도성 범프를 갖는 칩을 기판에 접합하여 구성하므로, 전기적 단락을 방지할 수 있을 뿐만 아니라 균일하고 높은 전기 전도도를 얻을 수 있는 전자부품 및 그 제조방법을 제공하는 데 다른 목적이 있다.
In addition, since the present invention is configured by bonding the chip having the inclined conductive bump to a substrate, it is possible to provide an electronic component and a method of manufacturing the same, which can not only prevent an electrical short circuit but also obtain a uniform and high electrical conductivity. There is another purpose.

이 발명의 경사진 전도성 범프를 갖는 칩의 제조방법은, 표면에 다수의 전극이 형성된 웨이퍼의 상면에 감광층을 코팅한 후 감광층에 다수의 경사진 구멍을 가공하되 전극이 형성된 부위에 경사진 구멍을 가공하는 제1 단계와, 감광층과 다수의 경사진 구멍의 표면에 금속층을 코팅하는 제2 단계와, 감광층이 상부로 노출되는 위치까지 금속층의 일부분을 기계적인 가공방법으로 제거해 웨이퍼의 상면에 서로 간에 전기적으로 절연되는 다수의 경사진 전도성 범프를 형성하는 제3 단계와, 감광층을 제거해 경사진 전도성 범프의 끝 부분을 웨이퍼의 상면으로 노출시키는 제4 단계, 및 절단선을 따라 웨이퍼를 절단함으로써 경사진 전도성 범프를 갖는 칩을 제조하는 제5 단계를 포함하는 것을 특징으로 한다.In the method of manufacturing a chip having an inclined conductive bump of the present invention, a photosensitive layer is coated on the top surface of a wafer having a plurality of electrodes formed thereon, and then a plurality of inclined holes are processed in the photosensitive layer, but the inclined portion is formed on the electrode. A first step of processing holes, a second step of coating a metal layer on the surface of the photosensitive layer and the plurality of inclined holes, and a portion of the metal layer removed by mechanical processing to a position where the photosensitive layer is exposed to the upper part of the wafer. A third step of forming a plurality of inclined conductive bumps electrically insulated from each other on the upper surface, a fourth step of removing the photosensitive layer to expose the end portion of the inclined conductive bump to the upper surface of the wafer, and a wafer along the cutting line And a fifth step of manufacturing the chip having the inclined conductive bumps by cutting a.

이 발명의 제4 단계에서는 감광층의 전체를 제거해 경사진 전도성 범프의 전체를 웨이퍼의 상면으로 노출시킬 수 있다.In the fourth step of the present invention, the entire photosensitive layer may be removed to expose the entire inclined conductive bump to the upper surface of the wafer.

이 발명의 제1 단계에서, 경사진 구멍은 감광층이 코팅된 웨이퍼를 일정 각도로 기울인 상태에서 자외선을 조사해 감광층을 경화시킴으로써 형성할 수 있다. In the first step of the present invention, the inclined hole may be formed by curing ultraviolet light by irradiating ultraviolet light in a state where the wafer on which the photosensitive layer is coated is inclined at a predetermined angle.

이 발명의 다수의 경사진 구멍은 전극이 형성되지 않는 부위에도 더 형성될 수 있다. A plurality of inclined holes of the present invention may be further formed in the portion where the electrode is not formed.

이 발명의 금속층의 일부분을 제거하는 기계적인 가공방법은, 그라인딩, 폴리싱 또는 화학적-기계적 폴리싱(Chemical Mechanical Polishing) 방법일 수 있다. The mechanical processing method for removing a part of the metal layer of the present invention may be a grinding, polishing or chemical mechanical polishing method.

이 발명의 금속층은 금, 은, 구리, 니켈, 주석 또는 이들의 합금 재질로 구성될 수 있다. The metal layer of the present invention may be made of gold, silver, copper, nickel, tin, or alloys thereof.

이 발명의 경사진 전도성 범프를 갖는 칩은, 표면에 1개 이상의 패드를 갖는 칩과, 패드의 상면에 1개 이상씩 형성되는 제1 경사진 전도성 범프를 포함하며, 제1 경사진 전도성 범프는 상부가 개방된 실린더 형태를 갖되, 그 끝 부분이 칩의 상면으로 노출되는 구조를 갖는 것을 특징으로 한다. A chip having an inclined conductive bump of the present invention includes a chip having at least one pad on its surface and a first inclined conductive bump formed on at least one top surface of the pad, wherein the first inclined conductive bump is The upper portion has an open cylindrical shape, the end portion of which is characterized by having a structure that is exposed to the upper surface of the chip.

이 발명은 패드 이외의 칩의 표면에 형성되는 다수의 제2 경사진 전도성 범프를 더 포함할 수 있다. The invention may further comprise a plurality of second inclined conductive bumps formed on the surface of the chip other than the pad.

이 발명의 제1, 제2 경사진 전도성 범프의 경사각은 칩의 표면에 대해 45도 이상일 수 있다. The inclination angle of the first and second inclined conductive bumps of this invention may be at least 45 degrees with respect to the surface of the chip.

이 발명의 제1, 제2 경사진 전도성 범프의 둘레에는 폴리머 층이 더 채워질 수 있다. The polymer layer may be further filled around the first and second inclined conductive bumps of the present invention.

이 발명의 제1, 제2 경사진 전도성 범프의 높이는 20㎛ 이내이고, 제1, 제2 경사진 전도성 범프의 단면 직경 또는 폭은 패드 사이 간격의 1/2 이내일 수 있다. The height of the first and second inclined conductive bumps of the present invention may be within 20 μm, and the cross-sectional diameter or width of the first and second inclined conductive bumps may be within one half of the spacing between the pads.

이 발명의 전자부품의 제조방법은, 상기와 같이 기재된 경사진 전도성 범프를 갖는 칩의 표면 중에서 제1 경사진 전도성 범프가 형성된 표면이나 기판의 표면 중에서 패드가 형성된 표면에 절연성 재질의 접착제를 도포하는 단계와, 제1 경사진 전도성 범프가 패드에 접촉하도록 위치시킨 상태에서 압력을 가해 제1 경사진 전도성 범프의 끝 부분을 휘어지게 변형시켜 패드에 접촉시킴과 더불어 열을 가해 접착제를 경화시켜 칩을 기판에 접합함으로써 전자부품을 제조하는 단계를 포함하는 것을 특징으로 한다. In the method for manufacturing an electronic component of the present invention, an adhesive of an insulating material is applied to a surface having a first inclined conductive bump formed on the surface of a chip having an inclined conductive bump described above or a surface having a pad formed on the surface of a substrate. And placing the first beveled conductive bump in contact with the pad, applying pressure to deform the tip of the first beveled conductive bump so as to contact the pad and applying heat to cure the adhesive to form a chip. And manufacturing the electronic component by bonding to the substrate.

이 발명의 전자부품은 상기와 같이 기재된 전자부품의 제조방법에 의해 제조되는 것을 특징으로 한다.
The electronic component of this invention is manufactured by the manufacturing method of the electronic component as described above.

이 발명은 경사진 전도성 범프의 구조를 단순화함에 따라 웨이퍼 레벨(상태)에서 전도성 범프를 보다 효율적으로 제조할 수 있으므로 생산성을 향상시키는 장점이 있다.This invention has the advantage of improving productivity since the conductive bumps can be more efficiently manufactured at the wafer level (state) by simplifying the structure of the inclined conductive bumps.

또한, 이 발명은 경사진 전도성 범프의 둘레에 채워지는 폴리머 층이 접합시에 추가의 탄성 복원력을 발생시킴에 따라 전도성 범프의 과도한 변형을 제한하여 전도성 범프가 파괴되는 것을 방지하는 장점이 있다. In addition, this invention has the advantage of preventing the breakage of the conductive bumps by limiting excessive deformation of the conductive bumps as the polymer layer filled around the inclined conductive bumps generates additional elastic restoring force upon bonding.

또한, 이 발명은 경사진 전도성 범프를 갖는 칩을 단지 기판에 접합하여 구성하므로, 전자부품의 접합과정에서 전기적 단락을 방지할 수 있을 뿐만 아니라 균일하고 높은 전기 전도도를 얻을 수 있는 장점이 있다.In addition, since the present invention is configured by only bonding a chip having an inclined conductive bump to a substrate, it is possible not only to prevent an electric short circuit during the bonding process of an electronic component, but also to obtain a uniform and high electrical conductivity.

또한, 이 발명은 경사진 전도성 범프의 끝 부분이 열압착 접합시 압력에 의해 휘어지고, 그로 인한 전도성 범프의 탄성 복원력에 의해 전도성 범프와 기판의 패드 사이에 접촉이 유지됨과 더불어 접촉 면적을 증가시켜 전기 저항을 감소시키는 장점이 있다.In addition, the present invention is the end of the inclined conductive bump is bent under pressure during thermocompression bonding, thereby increasing the contact area while maintaining contact between the conductive bump and the pad of the substrate by the elastic restoring force of the conductive bump There is an advantage of reducing the electrical resistance.

또한, 이 발명은 웨이퍼 레벨(상태)에서 한 번의 리소그래피와 에칭 및 기계적인 가공으로 전도성 범프를 가공하므로 가공비를 절감하는 장점이 있다.In addition, the present invention has the advantage of reducing the processing cost because the conductive bump is processed by one lithography, etching and mechanical processing at the wafer level (state).

또한, 이 발명은 웨이퍼의 전체 표면에 전도성 범프를 균일한 패턴으로 형성할 경우, 리소그래피에 사용되는 마스크를 칩의 패드 형상이나 분포와 무관하게 공통적으로 활용할 수 있으므로 원가를 절감할 수 있는 장점이 있다.In addition, when the conductive bumps are formed in a uniform pattern on the entire surface of the wafer, the mask used for lithography can be commonly used irrespective of the pad shape or distribution of the chip, thereby reducing the cost. .

또한, 이 발명은 전도성 범프를 칩의 패드 부위에 다수개 형성하고 패드 사이의 부위에 형성하지 않을 경우, 전도성 범프 간의 전기적 단락을 더 효율적으로 방지할 수 있는 장점이 있다.
In addition, the present invention has the advantage of preventing the electrical short between the conductive bumps more efficiently if a plurality of conductive bumps are formed in the pad portion of the chip and not formed in the portion between the pads.

도 1은 이 발명의 한 실시예에 따른 경사진 전도성 범프를 갖는 칩을 웨이퍼 레벨(상태)로부터 제조하는 과정을 나타낸 흐름도이고,
도 2는 도 1에 나타낸 방법에 의해 제조된 이 발명에 따른 경사진 전도성 범프를 갖는 칩의 개략도이고,
도 3a 및 도 3b는 도 2의 (a), (b)에 도시된 경사진 전도성 범프를 갖는 칩을 구비한 전자부품의 제조과정을 각각 도시한 개략도이며,
도 4는 도 3a의 제조과정에 의해 제조된 이 발명에 따른 전자부품의 개략도이다.1 is a flowchart illustrating a process of fabricating a chip having an inclined conductive bump from a wafer level according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a chip with inclined conductive bumps according to the invention produced by the method shown in FIG. 1,
3A and 3B are schematic views illustrating a manufacturing process of an electronic component having a chip having inclined conductive bumps illustrated in FIGS. 2A and 2B, respectively;
4 is a schematic diagram of an electronic component according to the present invention manufactured by the manufacturing process of FIG. 3A.

아래에서, 이 발명에 따른 경사진 전도성 범프를 갖는 칩 및 그 제조방법과, 칩을 구비한 전자부품 및 그 제조방법의 양호한 실시예를 첨부한 도면을 참조하여 상세히 설명한다. Hereinafter, a chip having an inclined conductive bump and a method of manufacturing the same according to the present invention, an electronic component having a chip, and a preferred embodiment of the method of manufacturing the same will be described in detail with reference to the accompanying drawings.

도 1은 이 발명의 한 실시예에 따른 경사진 전도성 범프를 갖는 칩을 웨이퍼 레벨(상태)로부터 제조하는 과정을 나타낸 흐름도이고, 도 2는 도 1에 나타낸 방법에 의해 제조된 이 발명에 따른 경사진 전도성 범프를 갖는 칩의 개략도이다.1 is a flow chart illustrating a process of fabricating a chip with inclined conductive bumps from wafer level (state) according to one embodiment of the invention, and FIG. Photo is a schematic view of a chip with conductive bumps.

도 1에 나타낸 바와 같이, 이 실시예에 따른 경사진 전도성 범프를 갖는 칩의 제조 과정은 다음과 같다. As shown in Fig. 1, the manufacturing process of the chip having the inclined conductive bump according to this embodiment is as follows.

제1 단계는 웨이퍼(100)에 경사진 전도성 범프에 해당하는 구멍을 가공하는 과정이다. 따라서, 제1 단계에서는 일정 간격으로 다수의 전극(101)이 형성된 웨이퍼(100)의 상면에 감광성 재질로 구성된 감광층(110)을 코팅한 후, 리소그래피와 에칭공정을 이용해 감광층(110)을 식각해 다수의 경사진 구멍(120) 패턴을 가공하되, 감광층(110)이 코팅된 웨이퍼(100)를 일정 각도로 기울인 상태에서 자외선을 조사해 감광층(110)을 경화시켜 경사진 구멍(120)을 가공한다. 이때, 다수의 경사진 구멍(120)은 전극(101)이 형성되거나 형성되지 않는 부위 및 그 경계라인에 각각 형성되도록 패턴 가공된다. 여기서, 경사진 구멍(120)은 원통형 또는 직육면체 등 다양한 형상으로 가공해 사용할 수 있다.The first step is to process holes corresponding to the inclined conductive bumps on the wafer 100. Therefore, in the first step, the photosensitive layer 110 formed of the photosensitive material is coated on the upper surface of the wafer 100 on which the plurality of electrodes 101 are formed at predetermined intervals, and then the photosensitive layer 110 is applied using a lithography and etching process. A plurality of inclined hole 120 patterns are processed by etching, and the photosensitive layer 110 is cured by irradiating ultraviolet rays in a state where the wafer 100 coated with the photosensitive layer 110 is inclined at a predetermined angle, thereby inclining the inclined hole 120. ). In this case, the plurality of inclined holes 120 are patterned to be formed at portions where the electrode 101 is not formed or at boundary lines thereof. Here, the inclined hole 120 can be processed into various shapes such as cylindrical or rectangular parallelepiped.

제2 단계는 경사진 구멍(120) 패턴에 금속층(130)을 코팅하는 과정이다. 따라서, 제2 단계에서는 증착공정 또는 무전해 도금공정을 이용해 감광층(110)과 다수의 경사진 구멍(120)의 표면에 금속층(130)을 코팅한다. 여기서, 경사진 구멍(120)은 코팅 조건에 따라 중공 실린더 또는 구멍의 내부가 채워진 솔리드 실린더 형태로 가공할 수 있다. 한편, 금속층(130)은 전기 전도도가 높은 금, 은, 구리, 니켈, 주석 등의 금속 또는 이들의 합금 재질을 사용하는 것이 바람직하다. The second step is a process of coating the metal layer 130 on the inclined hole 120 pattern. Therefore, in the second step, the metal layer 130 is coated on the surface of the photosensitive layer 110 and the plurality of inclined holes 120 using a deposition process or an electroless plating process. Here, the inclined hole 120 may be processed into a hollow cylinder or a solid cylinder in which the inside of the hole is filled according to coating conditions. In the meantime, the metal layer 130 may be formed of a metal such as gold, silver, copper, nickel, tin, or an alloy thereof, having high electrical conductivity.

제3 단계는 감광층(110)의 상부에 형성된 금속층(130)을 제거하는 과정이다. 따라서, 제3 단계에서는 감광층(110)이 상부로 노출되는 지점을 가공선(140)으로 하여, 가공선(140)의 상부에 위치하는 금속층(130)의 일부분을 기계적인 가공방법으로 제거한다. 여기에 사용되는 기계적인 가공방법으로는 그라인딩이나 폴리싱 또는 화학적-기계적 폴리싱(Chemical Mechanical Polishing) 방법을 사용할 수 있다. 이렇게 함으로써, 웨이퍼(100)의 상면에는 일정 간격을 두고 서로 간에 전기적으로 절연되는 다수의 경사진 전도성 범프(150)가 균일하게 형성된다.The third step is to remove the metal layer 130 formed on the photosensitive layer 110. Therefore, in the third step, a portion of the metal layer 130 positioned on the upper portion of the overhead line 140 is removed using a mechanical machining method using the point where the photosensitive layer 110 is exposed upward. As the mechanical processing method used here, grinding, polishing or chemical mechanical polishing (Chemical Mechanical Polishing) method can be used. By doing so, a plurality of inclined conductive bumps 150 electrically insulated from each other at regular intervals are formed on the upper surface of the wafer 100 uniformly.

제4 단계는 감광층(110)을 제거하여 경사진 전도성 범프(150)를 웨이퍼(100)의 상면으로 노출시키는 과정이다. 따라서, 제4 단계에서는 에칭공정을 이용해 감광층(110)을 제거하여 경사진 전도성 범프(150)를 웨이퍼(100)의 상면으로 노출시킨다. 이렇게 함으로써, 전극(101)을 비롯한 웨이퍼(100)의 상면에 다수의 경사진 전도성 범프(150)가 형성된다.The fourth step is a process of exposing the inclined conductive bump 150 to the top surface of the wafer 100 by removing the photosensitive layer 110. Therefore, in the fourth step, the photosensitive layer 110 is removed using an etching process to expose the inclined conductive bump 150 to the top surface of the wafer 100. In this way, a plurality of inclined conductive bumps 150 are formed on the top surface of the wafer 100 including the electrode 101.

제5 단계는 웨이퍼(100)를 절단하여 경사진 전도성 범프를 갖는 칩을 각각 제조하는 과정이다. 따라서, 제5 단계에서는 다이싱(dicing) 공정으로 절단선을 따라 웨이퍼(100)를 절단함으로써 도 2의 (a)와 같은 이 발명에 따른 경사진 전도성 범프를 갖는 칩을 각각 제조한다. The fifth step is a process of manufacturing the chips each having the inclined conductive bumps by cutting the wafer 100. Therefore, in the fifth step, each chip having an inclined conductive bump according to the present invention as shown in FIG. 2A is manufactured by cutting the wafer 100 along a cutting line by a dicing process.

한편, 제4 단계에서 에칭공정을 이용해 감광층(110)을 제거하여 경사진 전도성 범프(150)를 웨이퍼(100)의 상면으로 노출시킴에 있어서, 에칭 속도를 조절해 감광층(110)의 일부분을 남겨 폴리머 층을 형성할 수도 있다. 또한, 감광층(110)을 모두 제거한 후, 그 자리에 별도의 폴리머로 도포하여 폴리머 층을 형성할 수도 있다. 따라서, 폴리머 층을 갖는 웨이퍼를 상기 제5 단계에서와 같이 다이싱(dicing) 공정으로 절단선을 따라 절단할 경우에는, 도 2의 (b)와 같이 폴리머 층을 구비한 이 발명에 따른 경사진 전도성 범프를 갖는 칩이 각각 제조된다.Meanwhile, in the fourth step, the photosensitive layer 110 is removed using an etching process to expose the inclined conductive bumps 150 to the top surface of the wafer 100. It may be left to form a polymer layer. In addition, after removing all of the photosensitive layer 110, it may be applied by a separate polymer in place to form a polymer layer. Therefore, when the wafer having the polymer layer is cut along the cutting line by the dicing process as in the fifth step, the inclined according to the present invention having the polymer layer as shown in FIG. Each chip with conductive bumps is manufactured.

도 1에 나타낸 바와 같이, 이 실시예에 따른 경사진 전도성 범프를 갖는 칩의 제조 과정은, 웨이퍼 레벨(상태)에서 한 번의 리소그래피 공정과 에칭 공정을 통해 칩을 제조하기 때문에, 생산성이 높고 가공비가 저렴한 장점이 있다. As shown in Fig. 1, the manufacturing process of the chip having the inclined conductive bump according to this embodiment is high in productivity and high in processing cost because the chip is manufactured through one lithography process and etching process at the wafer level (state). There is an inexpensive advantage.

도 2의 (a)에 도시된 바와 같이, 이 발명에 따른 경사진 전도성 범프를 갖는 칩(200)은 그 표면에 적어도 1개 이상의 패드(210)가 형성되어 있다. 패드(210)의 상면에는 다수의 제1 경사진 전도성 범프(220)가 형성되어 있고, 패드(210) 이외의 패드(210)에 인접한 칩(200)의 표면에도 다수의 제2 경사진 전도성 범프(230)가 균일하게 분포되어 있다.As shown in (a) of FIG. 2, at least one pad 210 is formed on a surface of the chip 200 having an inclined conductive bump according to the present invention. A plurality of first inclined conductive bumps 220 are formed on an upper surface of the pad 210, and a plurality of second inclined conductive bumps are formed on a surface of the chip 200 adjacent to the pad 210 other than the pad 210. 230 is uniformly distributed.

다수의 제1 경사진 전도성 범프(220) 중에서 일부분은 패드(210) 내에 위치하고, 나머지 부분은 패드(210)의 표면과 칩(200)의 표면 간의 경계라인을 덮는 위치에 형성된다. 제1, 제2 경사진 전도성 범프(220, 230)는 일정 각도(θ)로 경사진 실린더 형상의 구조를 갖는다. A portion of the plurality of first beveled conductive bumps 220 is located in the pad 210, and the remaining portion is formed at a position covering a boundary line between the surface of the pad 210 and the surface of the chip 200. The first and second inclined conductive bumps 220 and 230 have a cylindrical structure inclined at a predetermined angle θ.

한편, 도 2의 (b)에 도시된 바와 같이, 이 발명에 따른 경사진 전도성 범프를 갖는 칩(200)은 제1, 제2 경사진 전도성 범프(220, 230)의 둘레에 폴리머 층(240)이 채워지되, 제1, 제2 경사진 전도성 범프(220, 230)가 외부로 노출될 수 있는 지점까지 채워진 구조를 가질 수도 있다. 여기서, 폴리머 층(240)은 접합시 제1, 제2 경사진 전도성 범프(220, 230)의 변형을 제한하고 제1, 제2 경사진 전도성 범프(220, 230)의 탄성 복원력을 증가시키는 역할을 한다.Meanwhile, as illustrated in FIG. 2B, the chip 200 having the inclined conductive bumps according to the present invention may have a polymer layer 240 around the first and second inclined conductive bumps 220 and 230. ) May be filled, but may have a structure filled up to a point where the first and second inclined conductive bumps 220 and 230 may be exposed to the outside. Here, the polymer layer 240 serves to limit the deformation of the first and second inclined conductive bumps 220 and 230 and to increase the elastic restoring force of the first and second inclined conductive bumps 220 and 230 during bonding. Do it.

이 실시예의 경사진 전도성 범프는 칩의 전체 표면에 균일한 패턴으로 형성되고, 칩의 패드에 다수의 전도성 범프가 형성된다. 이 실시예의 전도성 범프의 재질로는 전기 전도도가 높은 금, 은, 구리, 니켈, 주석 등의 금속 또는 금속 합금 재질을 사용하고, 전도성 범프의 높이는 20㎛ 이내로 가공하며, 전도성 범프의 단면 직경 또는 폭은 패드 사이 간격의 1/2 이내로 가공하는 것이 바람직하다. 한편, 전도성 범프의 경사각(θ)은 전도성 범프가 변형될 때에 인접한 전도성 범프와 전기적 단락이 발생하지 않는 범위 내에서 결정하되, 그 경사각(θ)을 45도 이상의 각도로 가공하는 것이 바람직하다.The inclined conductive bumps of this embodiment are formed in a uniform pattern on the entire surface of the chip, and a plurality of conductive bumps are formed on the pad of the chip. As the material of the conductive bumps of this embodiment, a metal or a metal alloy material such as gold, silver, copper, nickel, and tin having high electrical conductivity is used, and the height of the conductive bumps is processed to within 20 μm, and the cross-sectional diameter or width of the conductive bumps is used. It is desirable to work within 1/2 of the spacing between the pads. On the other hand, the inclination angle θ of the conductive bumps is determined within a range where no electrical short occurs with the adjacent conductive bumps when the conductive bumps are deformed, but the inclination angle θ is preferably processed at an angle of 45 degrees or more.

이 실시예에서는 경사진 전도성 범프를 칩의 표면에 균일한 패턴으로 형성한 것이다. 따라서, 전도성 범프의 패턴이 균일하면 리소그래피 공정에 사용되는 마스크를 1개만 제작하여 공통적으로 사용하면 되므로 생산비를 감소시킬 수 있는 장점이 있다. 한편, 이 실시예는 경사진 전도성 범프를 칩의 표면에 특정한 패턴으로 형성할 수 있다. 즉, 다수의 전도성 범프를 칩의 패드 부위에만 형성하고 패드 사이의 부위에는 형성하지 않을 수 있다. 이 경우에는 패드 사이에 전도성 범프가 존재하지 않는 부위가 형성되어 전기적 단락을 방지할 수 있는 장점이 있지만, 칩의 패드 형상에 따라 마스크를 제작해야 하고 정밀한 정렬 장비가 필요하기 때문에 생산비가 증가하는 단점이 있다.In this embodiment, the inclined conductive bumps are formed in a uniform pattern on the surface of the chip. Therefore, if the pattern of the conductive bumps is uniform, since only one mask used in the lithography process is manufactured and commonly used, there is an advantage of reducing the production cost. On the other hand, this embodiment can form inclined conductive bumps in a specific pattern on the surface of the chip. That is, a plurality of conductive bumps may be formed only at pad portions of the chip, but not at portions between the pads. In this case, there is an advantage of preventing the electrical short circuit due to the formation of a portion where no conductive bumps exist between the pads. However, the production cost increases because a mask must be manufactured according to the pad shape of the chip and precise alignment equipment is required. There is this.

도 3a 및 도 3b는 도 2의 (a), (b)에 도시된 경사진 전도성 범프를 갖는 칩을 구비한 전자부품의 제조과정을 각각 도시한 개략도이고, 도 4는 도 3a의 제조과정에 의해 제조된 이 발명에 따른 전자부품의 개략도이다.3A and 3B are schematic diagrams respectively illustrating a manufacturing process of an electronic component having a chip having an inclined conductive bump shown in FIGS. 2A and 2B, and FIG. 4 is a manufacturing process of FIG. 3A. Is a schematic diagram of an electronic component according to the present invention.

도 2 및 도 3a에 나타낸 바와 같이, 먼저 칩(200) 및/또는 기판(300)의 표면에 접착제(310)를 코팅한다. 이때, 접착제(310)는 칩(200)의 표면 중에서 다수의 경사진 제1, 제2 전도성 범프(220, 230)가 형성된 표면에 코팅하거나, 기판(300)의 표면 중에서 패드(320)가 형성된 표면에 코팅한다. 여기에 사용되는 접착제(310)는 절연성 재질로서 포토레지스트(photoresist) 계통의 접착제를 사용하는 것이 바람직하다. As shown in FIGS. 2 and 3A, first, an adhesive 310 is coated on the surface of the chip 200 and / or the substrate 300. In this case, the adhesive 310 is coated on a surface on which the plurality of inclined first and second conductive bumps 220 and 230 are formed on the surface of the chip 200, or the pad 320 is formed on the surface of the substrate 300. Coating on the surface. The adhesive 310 used herein is preferably a photoresist-based adhesive as an insulating material.

그런 다음, 칩(200)을 기판(300)의 상면에 위치시키고 압력을 가해, 칩(200)의 제1, 제2 경사진 전도성 범프(220, 230)를 기판(300)의 패드(320) 및 기판(300)의 표면에 밀착시킨 상태에서, 열을 가해 접착제(310)를 경화시킴으로써 칩(200)이 기판(300)에 접합된다.Then, the chip 200 is placed on the upper surface of the substrate 300 and pressurized to apply the first and second inclined conductive bumps 220 and 230 of the chip 200 to the pad 320 of the substrate 300. And the chip 200 is bonded to the substrate 300 by applying heat to cure the adhesive 310 while being in close contact with the surface of the substrate 300.

그러면, 칩(200)의 제1, 제2 경사진 전도성 범프(220, 230) 중에서 패드(320)와 접촉하는 제1, 제2 경사진 전도성 범프(220, 230)는 가해진 압력에 의해 기판(300)의 표면으로 돌출된 패드(320)와 밀착되어 변형되되, 변형된 제1 경사진 전도성 범프(220)가 전기적 통로 역할을 한다. 즉, 제1 경사진 전도성 범프(220)의 끝 부분이 변형되어 휘어지면서 전기적 연결부를 형성한다.Then, of the first and second inclined conductive bumps 220 and 230 of the chip 200, the first and second inclined conductive bumps 220 and 230 in contact with the pad 320 may be formed by the applied pressure. The pad 320 protrudes to the surface of the 300 and is deformed to be in close contact with the deformed first deformed conductive bump 220 to serve as an electrical path. That is, the ends of the first inclined conductive bumps 220 are deformed and bent to form electrical connections.

한편, 도 2의 (b)에 도시된 경사진 전도성 범프를 갖는 칩을 이용해 도 3b와 같이 전자부품을 제조함에 있어서도, 도 3a와 동일한 방법으로 제조하되, 제1, 제2 전도성 범프(220, 230)의 둘레에 폴리머 층(240)이 채워짐에 따라, 폴리머 층(240)에서 제1, 제2 경사진 전도성 범프(220, 230)가 과도하게 변형하는 것을 방지하고 탄성 복원력을 증가시키는 역할을 하게 된다. Meanwhile, in manufacturing an electronic component as shown in FIG. 3B by using a chip having an inclined conductive bump shown in FIG. 2B, the first and second conductive bumps 220, As the polymer layer 240 is filled around the 230, the polymer layer 240 serves to prevent the first and second inclined conductive bumps 220 and 230 from being excessively deformed and to increase elastic restoring force. Done.

이 실시예의 전자부품은 제1, 제2 경사진 전도성 범프(220, 230)의 경사진 방향으로 제1, 제2 경사진 전도성 범프(220, 230)의 끝 부분이 휘기 때문에 인접한 제1, 제2 경사진 전도성 범프(220, 230) 간의 단락을 방지할 수 있으며, 또한 변형된 제1, 제2 경사진 전도성 범프(220, 230)에 탄성 복원력이 발생하여 제1, 제2 경사진 전도성 범프(220, 230)와 기판(300)의 패드(320) 사이의 연결을 유지시키게 된다. 또한, 휘어진 제1, 제2 경사진 전도성 범프(220, 230)가 기판(300)의 패드(320)와 접촉하는 면적이 증가함에 따라 전기 저항을 감소시키고, 일정한 패턴의 제1, 제2 경사진 전도성 범프(220, 230)에 의해 균일한 전기 전도도를 얻게 된다. In the electronic component of this embodiment, the end portions of the first and second inclined conductive bumps 220 and 230 are bent in the inclined direction of the first and second inclined conductive bumps 220 and 230. A short circuit between the two inclined conductive bumps 220 and 230 may be prevented, and elastic restoring force may be generated in the deformed first and second inclined conductive bumps 220 and 230 so that the first and second inclined conductive bumps are formed. The connection between the 220 and 230 and the pad 320 of the substrate 300 is maintained. In addition, as the area where the curved first and second inclined conductive bumps 220 and 230 contact the pad 320 of the substrate 300 increases, the electrical resistance is reduced, and the first and second slopes having a predetermined pattern are reduced. Uniform electrical conductivity is obtained by the photoconductive bumps 220, 230.

상기와 같이 칩(200)을 기판(300)에 접합하면, 제1 경사진 전도성 범프(220)를 매개로 칩(200)의 패드(210)와 기판(300)의 패드(320)는 전기적으로 연결되지만, 그 이외의 부분은 절연성 재질의 접착제(310)에 의해 절연된다. 이렇게 함으로써 도 4와 같은 이 발명에 따른 전자부품(400)이 제조된다.When the chip 200 is bonded to the substrate 300 as described above, the pad 210 of the chip 200 and the pad 320 of the substrate 300 are electrically connected to each other via the first inclined conductive bump 220. Although connected, other portions are insulated by the adhesive 310 of insulating material. In this way, the electronic component 400 according to the present invention as shown in FIG. 4 is manufactured.

이상에서 이 발명의 경사진 전도성 범프를 갖는 칩 및 그 제조방법과, 칩을 구비한 전자부품 및 그 제조방법에 대한 기술사항을 첨부도면과 함께 서술하였지만 이는 이 발명의 가장 양호한 실시예를 예시적으로 설명한 것이지 이 발명을 한정하는 것은 아니다. In the above, the chip having the inclined conductive bump of the present invention and its manufacturing method, and the technical details of the electronic component having the chip and the manufacturing method thereof have been described together with the accompanying drawings, which is an exemplary embodiment of the present invention. It is described as an example, but not limiting the present invention.

또한, 이 기술분야의 통상의 지식을 가진 자이면 누구나 이 발명의 기술사상의 범주를 이탈하지 않고 첨부한 특허청구범위 내에서 다양한 변형 및 모방이 가능함은 명백한 사실이다.
In addition, it is obvious that any person skilled in the art can make various modifications and imitations within the scope of the appended claims without departing from the scope of the technical idea of the present invention.

200 : 칩 210 : 패드
220 : 제1 경사진 전도성 범프 230 : 제2 경사진 전도성 범프
240 : 폴리머 층200: chip 210: pad
220: first inclined conductive bump 230: second inclined conductive bump
240: polymer layer

Claims (13)

표면에 다수의 전극이 형성된 웨이퍼의 상면에 감광층을 코팅한 후 상기 감광층에 다수의 경사진 구멍을 가공하되 상기 전극이 형성된 부위에 상기 경사진 구멍을 가공하는 제1 단계와,
상기 감광층과 상기 다수의 경사진 구멍의 표면에 금속층을 코팅하는 제2 단계와,
상기 감광층이 상부로 노출되는 위치까지 상기 금속층의 일부분을 기계적인 가공방법으로 제거해 상기 웨이퍼의 상면에 서로 간에 전기적으로 절연되는 다수의 경사진 전도성 범프를 형성하는 제3 단계와,
상기 감광층을 제거해 상기 경사진 전도성 범프의 끝 부분을 상기 웨이퍼의 상면으로 노출시키는 제4 단계, 및
절단선을 따라 상기 웨이퍼를 절단함으로써 경사진 전도성 범프를 갖는 칩을 제조하는 제5 단계를 포함하는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩의 제조방법.A first step of coating a photosensitive layer on an upper surface of a wafer having a plurality of electrodes formed on a surface thereof, and processing a plurality of inclined holes in the photosensitive layer, but processing the inclined holes in a portion where the electrodes are formed;
Coating a metal layer on surfaces of the photosensitive layer and the plurality of inclined holes;
Removing a portion of the metal layer by a mechanical processing method to a position where the photosensitive layer is exposed to the upper part, and forming a plurality of inclined conductive bumps electrically insulated from each other on an upper surface of the wafer;
Removing the photosensitive layer to expose an end portion of the inclined conductive bump to an upper surface of the wafer, and
And a fifth step of manufacturing a chip having an inclined conductive bump by cutting the wafer along a cutting line. 청구항 1에 있어서,
상기 제4 단계에서, 상기 감광층의 전체를 제거해 상기 경사진 전도성 범프의 전체를 상기 웨이퍼의 상면으로 노출시키는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩의 제조방법.The method according to claim 1,
The method of claim 4, wherein the entire photosensitive layer is removed to expose the entire inclined conductive bump to an upper surface of the wafer. 청구항 1 또는 청구항 2에 있어서,
상기 제1 단계에서, 상기 경사진 구멍은 상기 감광층이 코팅된 상기 웨이퍼를 일정 각도로 기울인 상태에서 자외선을 조사해 상기 감광층을 경화시킴으로써 형성하는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩의 제조방법.The method according to claim 1 or 2,
In the first step, the inclined hole is formed by inclining the wafer on which the photosensitive layer is coated at a predetermined angle to irradiate ultraviolet rays to harden the photosensitive layer. Way. 청구항 1 또는 청구항 2에 있어서,
상기 다수의 경사진 구멍은 상기 전극이 형성되지 않는 부위에도 더 형성되는 것을 특징으로 경사진 전도성 범프를 갖는 칩의 제조방법.The method according to claim 1 or 2,
And the plurality of inclined holes are further formed in a portion where the electrode is not formed. 청구항 1 또는 청구항 2에 있어서,
상기 금속층의 일부분을 제거하는 기계적인 가공방법은, 그라인딩, 폴리싱 또는 화학적-기계적 폴리싱(Chemical Mechanical Polishing) 방법인 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩의 제조방법.The method according to claim 1 or 2,
The mechanical processing method for removing a portion of the metal layer is a grinding, polishing or chemical mechanical polishing (Chemical Mechanical Polishing) method of manufacturing a chip having an inclined conductive bumps. 청구항 1 또는 청구항 2에 있어서,
상기 금속층은 금, 은, 구리, 니켈, 주석 또는 이들의 합금 재질로 구성되는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩의 제조방법.The method according to claim 1 or 2,
The metal layer is a method of manufacturing a chip having an inclined conductive bump, characterized in that consisting of gold, silver, copper, nickel, tin or alloys thereof. 표면에 1개 이상의 패드를 갖는 칩과,
상기 패드의 상면에 1개 이상씩 형성되는 제1 경사진 전도성 범프를 포함하며,
상기 제1 경사진 전도성 범프는 상부가 개방된 실린더 형태를 갖되, 그 끝 부분이 상기 칩의 상면으로 노출되는 구조를 갖는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩.A chip having at least one pad on its surface,
At least one first inclined conductive bumps are formed on the upper surface of the pad,
The first inclined conductive bump has a cylindrical shape with an open top, the chip having a sloped conductive bump, characterized in that the end portion is exposed to the upper surface of the chip. 청구항 7에 있어서,
상기 패드 이외의 상기 칩의 표면에 형성되는 다수의 제2 경사진 전도성 범프를 더 포함하는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩.The method of claim 7,
And a plurality of second inclined conductive bumps formed on a surface of the chip other than the pad. 청구항 8에 있어서,
상기 제1, 제2 경사진 전도성 범프의 경사각은 상기 칩의 표면에 대해 45도 이상인 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩.The method according to claim 8,
And the inclination angle of the first and second inclined conductive bumps is 45 degrees or more with respect to the surface of the chip. 청구항 9에 있어서,
상기 제1, 제2 경사진 전도성 범프의 둘레에는 폴리머 층이 더 채워지는 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩.The method according to claim 9,
And a polymer layer further filled around the first and second inclined conductive bumps. 청구항 9에 있어서,
상기 제1, 제2 경사진 전도성 범프의 높이는 20㎛ 이내이고, 상기 제1, 제2 경사진 전도성 범프의 단면 직경 또는 폭은 상기 패드 사이 간격의 1/2 이내인 것을 특징으로 하는 경사진 전도성 범프를 갖는 칩. The method according to claim 9,
The height of the first and second inclined conductive bumps is within 20 μm, and the cross-sectional diameter or width of the first and second inclined conductive bumps is within one half of the spacing between the pads. Chip with bumps. 청구항 7 내지 청구항 11 중 어느 한 항에 기재된 경사진 전도성 범프를 갖는 칩의 표면 중에서 상기 제1 경사진 전도성 범프가 형성된 표면이나 기판의 표면 중에서 패드가 형성된 표면에 절연성 재질의 접착제를 도포하는 단계와,
상기 제1 경사진 전도성 범프가 상기 패드에 접촉하도록 위치시킨 상태에서 압력을 가해 상기 제1 경사진 전도성 범프의 끝 부분을 휘어지게 변형시켜 상기 패드에 접촉시킴과 더불어 열을 가해 상기 접착제를 경화시켜 상기 칩을 상기 기판에 접합함으로써 전자부품을 제조하는 단계를 포함하는 것을 특징으로 하는 전자부품의 제조방법.Applying an adhesive of an insulating material to the surface of the chip having the inclined conductive bump according to any one of claims 7 to 11 or to the surface of the substrate on which the pad is formed; ,
The pressure of the first inclined conductive bump is placed in contact with the pad to deform the tip of the first inclined conductive bump so as to be in contact with the pad and heat to cure the adhesive. Manufacturing the electronic component by bonding the chip to the substrate. 삭제delete
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US9947633B2 (en) * 2016-06-28 2018-04-17 Invensas Corporation Deformable conductive contacts
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