KR101128884B1

KR101128884B1 - Anti fuse of semiconductor device

Info

Publication number: KR101128884B1
Application number: KR1020090097238A
Authority: KR
Inventors: 김진하; 최득성
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-10-13
Filing date: 2009-10-13
Publication date: 2012-03-26
Also published as: KR20110040097A

Abstract

The antifuse of the semiconductor device according to the present invention includes an insulating film passing over an active region, a gate provided on the insulating film, a center contact plug provided in an area closest to the gate, and a center contact plug in the gate long axis direction. It includes a plurality of peripheral contact plugs spaced apart from the center contact plug, and arranged so as to sequentially increase the spaced distance from the gate as the distance from the center contact plug, so that the breakdown of the insulating film is made in the center portion of the active region, In the reliability evaluation, it is possible to prevent the sudden increase in resistance due to re-oxidation, thereby improving the reliability of the anti-fuse.

Anti-fuse, insulation film breakdown, active area

Description

Anti-fuse of semiconductor device

The present invention relates to an antifuse of a semiconductor device, and more particularly, to an antifuse which can reduce the formation of an oxide insulating film due to subsequent thermal stress.

A semiconductor device, in particular a memory device, is treated as a defective product because it fails to function as a memory if any one of many memory cells is defective at the time of manufacture. However, in spite of defects in only some memory cells in the memory, disposing of the entire memory device as defective is inefficient in terms of productivity. Accordingly, by replacing a defective memory cell using a redundancy cell previously manufactured in the memory device, the yield is improved and the cost is reduced by reviving the entire device.

The repair operation using the redundancy cell is to prepare a redundancy row and a redundancy column for each memory cell array in advance so that a defective memory cell having a defective memory cell exists. Replace rows or columns with redundancy rows or redundancy columns. For example, if a bad memory cell is found through a test after wafer processing is completed, a program operation for replacing an address of the bad memory cell with the address of the redundancy cell is performed in the internal circuit. Therefore, when an address signal corresponding to a bad line is input in actual use of the semiconductor memory device, the redundancy line is accessed instead of the bad line.

Typical repair operations use a lot of fuses. However, since a semiconductor device is repaired using a fuse, the repair is performed in a wafer state, and thus there is a limit that cannot be applied when it is found that a defective cell exists in a state in which a package is completed. Therefore, it is necessary to overcome these limitations. The antifuse method was developed to overcome the limitations of the fuse method.

Antifuse can be programmed for fault relief simply at the package level. In general, antifuse devices have opposite electrical characteristics as fuse devices. In other words, the anti-fuse is generally a resistive fuse device, which has a high resistance when not programmed and a low resistance after a program operation. Antifuse devices typically have a dielectric such as silicon dioxide (SiO2), silicon nitride, tantalum oxide or silicon dioxide-silicon nitride-silicon dioxide (ONO) sandwiched between two conductors. It is composed of very thin dielectric materials such as composites. The program operation of the antifuse is programmed in such a way as to break the dielectric between both conductors by applying a high voltage through the antifuse terminals for a sufficient time. Therefore, when the antifuse is programmed, the conductors at both ends of the antifuse are shorted so that the resistance becomes a small value. Thus, the antifuse's default state is an electrically open state and is electrically shorted when a high voltage is applied and programmed.

1 is a plan view illustrating an antifuse of a semiconductor device according to the prior art.

As shown in FIG. 1, an antifuse of a semiconductor device according to the related art includes a gate insulating film (not shown) and a gate formed on a semiconductor substrate 10 including an active region 12 defined as an isolation layer 14. A gate 16 formed on the insulating layer (not shown), contact plugs 18 provided on the active region 12 and spaced apart from the gate 16 at regular intervals, and connected to the upper portions of the contact plugs 18. The conductive wiring 20 is included. The antifuse is generally operated by breaking a gate insulating film (not shown) by applying a high voltage between the gate 16 and the contact plugs 18. At this time, a region where the gate insulating layer (not shown) is destroyed is randomly generated among the regions adjacent to the contact plugs 18. In particular, when the contact plug at the edge of the active region 12 of the contact plugs 18, that is, the gate insulating film provided at a position adjacent to the contact plug located in the region adjacent to the device isolation layer 14, is destroyed, In spite of being destroyed, it is re-oxidized at the interface between the semiconductor substrate 10 and the gate 16 in a subsequent reliability assessment (e.g., thermal stress or thermal cycle). There is a problem that causes a fail (fail).

In the anti-fuse of a semiconductor device, the present invention is intended to solve the problem of failing to accurately evaluate the failure in the reliability evaluation when the gate insulating layer adjacent to the contacts located at the edge of the active region is destroyed.

The anti-fuse of the semiconductor device of the present invention is a constant in the longitudinal direction of the gate around the center contact plug and the center contact plug provided in the insulating film passing over the active region, the gate provided on the insulating film and the region closest to the gate, and the center contact plug. And a plurality of peripheral contact plugs spaced apart from each other and arranged to sequentially increase the spaced distance from the gate as the distance from the center contact plug increases.

In this case, the center contact plug is connected to a central portion of the active region.

The center contact plug may be connected to a central portion of the source or drain region in the active region.

The peripheral contact plugs may be connected to the active area.

The insulating film and the gate may have the same width.

And a conductive wiring connected to the center contact plug and the plurality of peripheral contact plugs and spaced apart from the gate.

In addition, the center contact plug and the plurality of peripheral contact plugs are characterized in that the same size.

When the voltage is applied to the anti-fuse of the semiconductor device, the electric field applied between the center contact plug and the gate is the largest.

In addition, when a voltage is applied to the anti-fuse of the semiconductor device, an insulating film provided around the center contact plug is destroyed.

In addition, the center contact plug may be larger than a width of the plurality of peripheral contact plugs.

In this case, the widths of the plurality of peripheral contact plugs may be sequentially smaller than the widths of the center contact plugs as the widths of the plurality of peripheral contact plugs move away from the center contact axis direction.

In addition, the center of the center contact plug and the plurality of peripheral contact plugs may be located on a straight line parallel to the long axis direction of the gate.

The current is concentrated in the center contact plug.

In addition, the insulating film provided around the center contact plug is destroyed.

According to the present invention, the breakdown of the gate insulating film is performed in the center portion of the active region rather than in a random region, thereby preventing the sudden increase in resistance due to re-oxidation in the heat-related reliability evaluation. Provides the effect of improving the reliability of the.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described in detail.

FIG. 2A is a plan view illustrating an antifuse of a semiconductor device according to an exemplary embodiment of the present disclosure, FIG. 2B is a schematic view illustrating an E-field of an antifuse of a semiconductor device according to an embodiment of the present disclosure, and FIG. 3 is a plan view illustrating an antifuse of a semiconductor device according to a second exemplary embodiment of the present invention, and FIG. 3B is a schematic diagram showing current clouding of antifuse of the semiconductor device according to the second exemplary embodiment of the present invention.

As shown in FIG. 2A, an anti-fuse of a semiconductor device according to a first embodiment of the present invention may include a gate insulating film formed on a semiconductor substrate 100 including an active region 102 defined as an isolation layer 104. A gate 106 formed over the gate insulating film (not shown) and having the same width as the gate insulating film (not shown), and a contact plug formed over the active region 102 and closest to the gate 106 (not shown). 108a and contact plugs 108b which are spaced apart in the long axis direction of the gate 106 about the contact plug 108a and are spaced apart from the contact plug 108a so as to be spaced apart from the gate 106. 108c and 108d and the conductive wiring 110 connected to the contact plug 108. At this time, in the first embodiment of the present invention, the contact plugs 108b, 108c, and 108d are spaced apart from the contact plug 108a, but the number of the contact plugs 108 is not limited thereto. Can be reduced.

More specifically, the contact plug 108a may be spaced apart from the gate 106 by the closest distance 'a' and connected to the center portion of the active region 102, that is, the center portion of the source or drain of the active region. 108b is adjacent to the contact plug 108a but is spaced apart from the gate 106 by a 'b' (b> a), and the contact plug 108c is adjacent to the contact plug 108b but from the gate 106. Preferably it is spaced apart by 'c' (c> b> a), and contact plug 108d is adjacent to contact plug 108c but spaced apart from gate 106 by 'd' (d> c> b> a). It is preferable to be. Thus, the contact plug 108d is spaced farthest from the gate 106 and is located at the edge of the active region 102. When a high voltage is applied between the contact plug 108 and the gate 106 to operate the antifuse, the contact plug 108a is closest to the gate 106 and thus the lower portion of the gate 106 adjacent to the contact plug 108a. The gate insulating film (not shown) provided in the gate breaker is destroyed, and since the contact plug 108d is spaced farthest from the gate 106, the gate insulating film (not shown) provided under the gate 106 is not destroyed. Therefore, as in the prior art, it is possible to prevent the destruction of the gate insulating film at the edge of the active region 102, so that re-oxidation is induced at the edge of the active region 102 in the course of performing the reliability evaluation. Can be prevented. For a detailed description in this regard, refer to the description of the schematic diagram showing the E-field of FIG. 2B.

As shown in FIG. 2B, the electric field between the gate 106 and the closest contact plug 108a and the gate 106 is included in the E-field of the antifuse of the semiconductor device according to the first embodiment of the present invention. ′ And the electric field 'Eb' (Eb <Ea) between the contact plug 108a and the adjacent contact plug 108b and the gate 106, and the contact plug 108c and the gate (adjacent to the contact plug 108b). The electric field 'Ec' (Ec <Eb <Ea) between 106 and the electric field 'Ed (Ed <Ec <Eb <Ea) between the contact plug 108c and the neighboring contact plug 108d and the gate 106 are Include. As described above, the electric field Ea applied between the contact plug 108a and the gate 106 is the contact 108b, 108c, 108d at the same voltage because the contact plug 108a is closest to the gate 106. Greater than the electric fields Eb, Ec, and Ed between the gate and the gate 106, so that the breakdown of the gate insulating film (not shown) is concentrated to a region adjacent to the contact plug 108a, that is, the center of the active region 102 can do.

As shown in FIG. 3A, an antifuse of a semiconductor device according to a second embodiment of the present invention may include a gate insulating film formed on a semiconductor substrate 150 including an active region 152 defined as an isolation layer 154. A gate 156 formed on the gate insulating layer (not shown) and having the same width as the gate insulating layer (not shown), and formed on the active region 152, and the gate 156 of the contact plug 158. Contact plugs 158h closest to each other, and contact plugs 158i and 158j spaced apart from the contact plug 158h in the major axis direction of the gate 156 but smaller as they move away from the contact plug 158h. And a conductive wiring 160 connected to the contact plug 158. In this case, although the contact plugs 158i and 158j are spaced apart from the contact plug 158h in the second embodiment of the present invention, the number of the contact plugs 158 is not limited thereto and may be increased or decreased. have.

More specifically, the contact plug 158h is closest to the gate 156 but has a width 'h' and is connected to the center portion of the active region 102, that is, the center portion of the source or drain of the active region. 158i is preferably adjacent to the contact plug 158a and has a width of 'i' (i <h), and the contact plug 158j is adjacent to the contact plug 158i and has a width of 'j' (j <i < h), and the center of the contact plug 158 is preferably located in a straight line. Accordingly, the contact plug 158j has the smallest width j of the contact plugs 158 and is spaced farthest from the gate 156 and positioned at the edge of the active region 152. When a high voltage is applied between the contact plug 158 and the gate 156 to operate the antifuse, the contact plug 158h is closest to the gate 156 and the width of the contact plug 158 is the widest. The gate insulating layer (not shown) provided under the gate 106 adjacent to 158h is destroyed, and since the contact plug 158j is spaced farthest from the gate 156, the gate insulating layer provided under the gate 156 ( Not shown) is not destroyed. Therefore, as in the prior art, it is possible to prevent the destruction of the gate insulating film at the edge of the active region 152, thereby causing re-oxidation at the edge of the active region 152 in the course of performing reliability evaluation. Can be prevented. For a detailed description in this regard, refer to the description of the schematic diagram showing the current clouding of FIG. 3B.

As shown in FIG. 3B, the current clouding of the antifuse of the semiconductor device according to the second embodiment of the present invention includes the currents Ah, Ai, and Aj between the contact 158h and the gate 156. . Here, the current Ah represents the current between the contact plug 158h and the gate 156 and the contact plug 158h closest to each other, and the current Ai represents the gate 156 and the contact plug adjacent to the contact plug 158i. Current Aj represents a current between contact plug 158j and an adjacent gate 156 and contact plug 158h. That is, the current between the contact plug 158 and the gate 156 is concentrated to the contact plug 158h having the largest width at the center of the contact plug 158. Therefore, the breakdown of the gate insulating layer (not shown) may be induced to be concentrated in the region adjacent to the contact plug 158h, that is, the center portion of the active region 152.

The anti-fuse of the semiconductor device according to the present invention is to destroy the gate insulating film in order to prevent the occurrence of failure due to re-oxidation between the semiconductor substrate and the gate in subsequent reliability evaluation when the gate insulating film is destroyed at the edge of the active region. Provides a structure to concentrate the central portion of the active area. Therefore, the structure described above is not limited to the first and second embodiments, and may be changed to another structure as long as the structure in which the breakdown of the gate insulating film is concentrated in the center portion of the active region.

1 is a plan view showing an anti-fuse of a semiconductor device according to the prior art.

2A is a plan view illustrating an antifuse of a semiconductor device according to example embodiments of the inventive concepts.

2B is a schematic diagram showing an E-field of an antifuse of a semiconductor device according to one embodiment of the present invention.

3A is a plan view illustrating an antifuse of a semiconductor device according to a second exemplary embodiment of the present invention.

3B is a schematic diagram showing current clouding of antifuse of a semiconductor device in accordance with a second embodiment of the present invention.

Claims

An insulating film passing over the active region;

A gate provided on the insulating layer;

A center contact plug provided in an area closest to the gate; And

A plurality of peripheral contact plugs spaced apart from the center contact plug in the direction of the gate long axis with respect to the center contact plug, the plurality of peripheral contact plugs arranged to sequentially increase the distance from the center contact plug,

The anti-fuse of the semiconductor device, characterized in that when the voltage is applied, the insulating film provided around the center contact plug is destroyed.

Claim 2 has been abandoned due to the setting registration fee.

The method according to claim 1,

And the center contact plug is connected to a central portion of the active region.

Claim 3 was abandoned when the setup registration fee was paid.

The method according to claim 1,

And the center contact plug is connected to a center portion of a source or drain region in the active region.

Claim 4 was abandoned when the registration fee was paid.

The method according to claim 1,

And the peripheral contact plugs are connected to the active region.

Claim 5 was abandoned upon payment of a set-up fee.

The method according to claim 1,

And the insulating film and the gate have the same width.

Claim 6 was abandoned when the registration fee was paid.

The method according to claim 1,

Claim 7 was abandoned upon payment of a set-up fee.

The method according to claim 1,

And said center contact plug and said plurality of peripheral contact plugs have the same size.

Claim 8 was abandoned when the registration fee was paid.

The method according to claim 1,

When voltage is applied to the anti-fuse of the semiconductor device

And an electric field applied between the center contact plug and the gate is the largest.

delete

Claim 10 was abandoned upon payment of a setup registration fee.

The method according to claim 1,

The gate short axis width of the center contact plug is greater than the gate short axis width of the plurality of peripheral contact plugs.

Claim 11 was abandoned upon payment of a setup registration fee.

The method according to claim 10,

The width of the plurality of peripheral contact plugs

The anti-fuse of the semiconductor device characterized in that the further away from the center contact plug in the direction of the gate longitudinal axis around the center contact plug.

Claim 12 was abandoned upon payment of a registration fee.

The method according to claim 10,

The center of the center contact plug and the plurality of peripheral contact plugs are located on a straight line parallel to the long axis direction of the gate.

Claim 13 was abandoned upon payment of a registration fee.

Anti-fuse of the semiconductor device, characterized in that the current is concentrated in the center contact plug.

Claim 14 was abandoned when the registration fee was paid.

The method according to claim 10,

And an insulating film provided around the center contact plug is destroyed.