KR101079285B1 - Electrical fuse in semiconductor device and driving method thereof - Google Patents

Abstract

The present invention provides an electrical fuse of a semiconductor device and a method of driving the same which can improve the integration degree of the electrical fuse and prevent the deterioration of the operating characteristics of the electrical fuse due to the increase in the degree of integration. ; A plurality of main fuses composed of capacitors; A plurality of plugs connected between the gate electrode of the master fuse and each of the main fuses; And an electrical fuse including a conductive pattern connected to all the plugs.

Description

ELECTRICAL FUSE IN SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to an electrical fuse of a semiconductor device capable of implementing multi-bit and a driving method thereof.

In semiconductor devices, fuses are used in various ways for repairing defective cells, storing chip identifications, and circuit customization. For example, cells out of many cells of a memory device that are found to be bad cells may be replaced by redundant cells by fuses. Accordingly, it is possible to solve the problem of lowering yield due to defects in some cells.

The fuse may be classified into a laser blowing type and an electrical blowing type. In the case of the laser blowing type, a method of blowing a fuse line with a laser beam is used. However, when irradiating a laser beam to a specific fuse line, there is a fear that the fuse line or other elements around the specific fuse line is damaged.

On the other hand, in the case of the electric blowing type, a method of blowing a fuse current by applying a programming current to the fuse link and blowing the fuse by electromigration and joule heating is used. The electric blowing method can be used even after the package assembly of the semiconductor chip is completed. A fuse employing this method is called an electric fuse.

In general, a transistor is used as an electric fuse, and an electric fuse of a method of breaking a gate insulating layer of the transistor is cut.

1A to 1C are diagrams illustrating electrical fuses of a semiconductor device according to the prior art, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line X-X 'of FIG. 1A, and FIG. 1C is a view of FIG. 1A. A cross-sectional view taken along the line Y-Y 'shown in FIG.

As shown in FIGS. 1A to 1C, an electrical fuse according to the related art is formed on a substrate 11 so that the gate insulating film 13, the gate electrode 14, and the gate hard master film 15 are sequentially stacked. Pick-up of a ring structure formed on the gate 16 of the structure, the junction region 17 formed in the substrate 11 on both sides of the gate 16, and the substrate 11 and surrounding the gate 16 and the junction region 17. Region 18 is included. Here, the reference numeral '12' is an isolation layer.

The electrical fuse having the above-described structure generates a large potential difference between the gate 16 and the junction region 17 or the gate 16 and the substrate 11 to cause breakdown of the gate insulating film 13. Blow electrical fuses. Then, a predetermined bias is applied to the gate 16 to detect a current between the gate 16 and the junction region 17 or the gate 16 and the substrate 11 to determine whether the electrical fuse blows.

When repairing a defective cell using an electrical fuse according to the prior art, a semiconductor device requires a plurality of electrical fuses corresponding to each cell because one electrical fuse replaces one defective cell with a spare cell.

However, when a plurality of electrical fuses occupying a large area in one die (or chip) are provided, a problem arises in that the degree of integration of the semiconductor device is reduced. If the size of the electrical fuse is reduced to solve this problem, the operating characteristics of the electrical fuse are deteriorated, which causes a problem that the electrical fuse is not normally blown.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems of the prior art, and improves the degree of integration of an electrical fuse and at the same time prevents deterioration of operating characteristics of an electrical fuse due to an increase in the degree of integration. The purpose is to provide.

According to an aspect of the present invention, there is provided a master fuse comprising a transistor; A plurality of main fuses composed of capacitors; A plurality of plugs connected between the gate electrode of the master fuse and each of the main fuses; And an electrical fuse including a conductive pattern connected to all the plugs.

The main fuses may have a structure overlapping each other by being positioned on the master fuse. The master fuse and the main fuse may be connected in series, and the plurality of main fuses may have a structure connected in parallel.

The master fuse may include a gate formed on a substrate and having a gate insulating film and a gate electrode stacked thereon; A junction region formed in the substrate on both sides of the gate; And a pickup area formed on the substrate and spaced apart from the gate by a predetermined distance to surround the gate. In this case, the master fuse may include only one of the junction region and the pickup region.

The plug may include a first plug connecting the conductive pattern and the gate of the master fuse and a second plug connecting the conductive pattern and the lower electrode of the main fuse.

The main fuse may be composed of one capacitor or a plurality of capacitors connected in parallel. In this case, the capacitor preferably has a cylindrical shape or a concave shape.

In addition, the electrical fuse of the present invention may further include a conductive line connected to the conductive pattern and the upper electrodes of the plurality of main fuses, respectively.

According to another aspect of the present invention for achieving the above object is a master fuse consisting of a transistor; A plurality of main fuses composed of capacitors; A plurality of plugs connected between the gate electrode of the master fuse and each of the main fuses; And an electrical fuse including a conductive pattern connected to all of the plugs, and then sequentially blowing the plurality of main fuses after the master fuse is blown.

Blowing of the master fuse may be performed by applying a high voltage equal to or greater than a power supply voltage to the main fuse and the conductive pattern, and applying a low voltage equal to or less than a ground voltage to the substrate.

The main fuse may be blown by applying a high voltage equal to or greater than a power supply voltage to the conductive pattern and the substrate in a state in which the master fuse is blown, and applying a low voltage equal to or less than ground voltage to the main fuse to be blown. .

SUMMARY OF THE INVENTION The present invention is based on the above-mentioned problem solving means, by providing a multi-bit electrical fuse comprising a plurality of main fuses consisting of a master fuse and a capacitor of the transistor, thereby providing a degree of integration of the electrical fuse and the semiconductor device having an electrical fuse There is an effect that can improve the degree of integration.

In addition, the present invention has the effect of preventing the deterioration of the operating characteristics as the degree of integration of the electrical fuse increases.

1A is a plan view showing an electrical fuse of a semiconductor device according to the prior art.
1B is a cross-sectional view taken along line X-X 'of FIG. 1A showing an electrical fuse of a semiconductor device according to the prior art;
1C is a cross-sectional view of the Y-Y ′ cut line shown in FIG. 1A showing an electrical fuse of a semiconductor device according to the prior art.
2A is a plan view illustrating an electrical fuse of a semiconductor device according to an embodiment of the present invention.
FIG. 2B is a cross-sectional view taken along line X-X 'of FIG. 2A showing an electrical fuse of a semiconductor device according to one embodiment of the present invention; FIG.
FIG. 2C is a cross-sectional view illustrating the Y-Y ′ cut line illustrated in FIG. 2A of the electrical fuse of the semiconductor device according to the exemplary embodiment of the present inventive concept.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention to be described later is to provide an electrical fuse and a method of manufacturing the semiconductor device that can improve the degree of integration of the electrical fuse, multi-bit in the same area as the conventional single-bit electrical fuse (multi- bit) Provides an electric fuse and its driving method. According to the present invention, the electrical fuse includes a master fuse made of a transistor and a plurality of main fuses made of a capacitor.

Hereinafter, the technical concept of the present invention will be described in detail by exemplifying a 4-bit (logical information '00', 01 ',' 10 ', 11') electrical fuse. This is for convenience of description, and the technical idea of the present invention can provide a multi-bit or more multi-bit electric fuse by adjusting the number of main fuses connected to the master fuse.

2A to 2C are diagrams illustrating an electrical fuse of a semiconductor device according to an embodiment of the present invention. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line X-X 'of FIG. 2A. 2c is a cross-sectional view taken along the line Y-Y 'shown in FIG. 2a.

As shown in FIGS. 2A to 2C, an electrical fuse of a semiconductor device according to an embodiment of the present invention may include a master fuse 101 composed of transistors and first through third main fuses composed of capacitors. 102, 103, 104, a plurality of plugs 30 and all plugs electrically connecting between the gate electrode 24 of the master fuse 101 and the first to third main fuses 102, 103, 104 ( And a conductive pattern 29 connected to 30. In addition, the fourth conductive line connected to the first to third conductive lines 38, 39, 40 and the conductive pattern 29 connected to the upper electrodes 35 of the first to third main fuses 102, 103, and 104. It may further include (41).

Here, the first to third main fuses 102, 103, and 104 are positioned on the master fuse 101 to improve the integration degree of the electrical fuse and to implement the multi-bit electrical fuse within a limited area. It is preferable to have a structure in which the three main fuses 102, 103, 104 and the master fuse 101 overlap each other.

The master fuse 101 and the first to third main fuses 102, 103, and 104 are connected in series, and the first, second and third main fuses 102, 103, and 104 are connected in parallel to each other. It is desirable to have. This prevents the floating of the first to third main fuses 102, 103, and 104 through the blowing of the master fuse 101 and at the same time the number of the first to third main fuses 102, 103, and 104. This is to realize the multi-bit electric fuse having the desired number of bits by adjusting the.

The master fuse 101 made of a transistor is formed on a substrate 21 and has a gate 26 and a gate having a structure in which a gate insulating film 23, a gate electrode 24, and a gate hard master film 25 are sequentially stacked. 26) a junction region 27 formed on both sides of the substrate 21 and a pickup region 28 formed in a ring shape surrounding the gate 26 and spaced apart from the gate 26 by a predetermined distance. Include. At this time, the pick-up region 28 acts as a guard ring for the electrical fuse while simultaneously applying a bias to the substrate 21, and has the same conductivity type as the substrate 21, but doping impurities in the substrate 21. It is desirable to have an impurity doping concentration higher than the concentration.

The master fuse 101 may include a gate 26 and a junction region 27, or may include a gate 26 and a pickup region 28. That is, the master fuse 101 may include only one of the junction region 27 and the pickup region 28.

Here, when the master fuse 101 is composed of the gate 26 and the junction region 27 when the master fuse 101 is blown, the gate insulating film 23 formed in the region where the gate 26 and the junction region 27 overlap each other. When this is disrupted and composed of the gate 26 and the pickup region 28, the gate insulating film 23 formed in the region where the gate 26 and the substrate 21 overlap each other is destroyed. In each case, only the magnitude of the amount of current detected in the process of detecting the blowing of the master fuse 101 is different from each other. Therefore, the master fuse 101 may include only one of the junction region 27 and the pickup region 28, or may include all of them.

The first to third main fuses 102, 103, and 104 may have a structure in which the lower electrode 33, the dielectric layer 34, and the upper electrode 35 are sequentially stacked. In this case, in order to improve the degree of integration of the electrical fuse, the first to third main fuses 102, 103, and 104 are preferably in the form of a cylinder or a concave.

In addition, the first to third main fuses 102, 103, and 104 may be formed of one capacitor or a plurality of capacitors connected in parallel. In this case, when the first to third main fuses 102, 103, and 104 are configured as one capacitor, the first to third main fuses 102, 103, and 104 are advantageously improved. In the case of configuring a plurality of capacitors connected in parallel, it is advantageous to improve (or stabilize) the operating characteristics of the electrical fuse.

The plurality of plugs 30 electrically connecting between the gate electrode 24 of the master fuse 101 and the first to third main fuses 102, 103, and 104 may be formed based on the conductive pattern 29. 29 and the first plug 30A connecting the gate electrode 24 of the master fuse 101, the conductive pattern 29, and the first to third main fuses 102, 103, and 104. The second plug 30B is included. In this case, the second plug 30B is connected to the lower electrodes 33 of the first to third main fuses 102, 103, and 104.

Hereinafter, a method of driving an electrical fuse of a semiconductor device according to an embodiment of the present invention having the above-described structure will be described in detail. An electrical fuse of a semiconductor device according to an embodiment of the present invention includes one master fuse 101 and three first to third main fuses 102, 103, and 104, thereby providing 4-bit logic information '00'. , '01', '10' and '11' can be implemented.

First, referring to the blowing method of the master fuse 101, a high voltage (eg, a power supply voltage or higher) is applied to all of the first to fourth conductive lines 38, 39, 40, and 41, and the junction area 27 or the pickup is performed. A low voltage (eg below ground voltage) is applied to the area 28. At this time, a low voltage may be applied to both the junction region 27 and the pickup region 28.

Since the high voltage is applied to all of the first to fourth conductive lines 38, 39, 40, and 41, the first to third main fuses 102, 103, and 104 are formed of the upper electrode 35 and the lower electrode 33. Does not occur between the gate and the gate 26 and the junction region 27 and / or the gate 26 and the substrate of the master fuse 101 due to the high voltage applied through the fourth conductive line 41 There is a large potential difference between 21.

At this time, the gate 26 and the junction region 27 of the master fuse 101 and / or breakdown to the gate insulating film 23 due to a large potential difference generated between the gate 26 and the substrate 21. As a result, the gate 26, specifically, the gate electrode 24, the junction region 27, and / or the substrate 21 are electrically connected to each other and the master fuse 101 is blown.

Next, the blowing method of the first to third main fuses 102, 103, and 104 is illustrated by exemplifying the case of blowing the first main fuse 102, and the floating of the first main fuse 102 is performed. To prevent this, a low voltage is applied to the first conductive line 38 connected to the upper electrode 35 of the first main fuse 102 to be blown while the master fuse 101 is blown, and the second to High voltages are applied to the fourth conductive lines 39, 40, 41 and the substrate 21.

Since the high voltage is applied to the fourth conductive line 41 and the substrate 21, the high voltage is also applied to the conductive pattern 29, and the voltage difference between the first conductive line 38 and the conductive pattern 29 is high. That is, breakdown occurs by the dielectric layer 34 due to the voltage difference between the upper electrode 35 and the lower electrode 33 of the first main fuse 102, and thus the upper electrode 35 and the lower electrode 33 are formed. The first main fuse 102 is blown while being electrically connected.

Based on the blowing method of the above-described master fuse 101 and the first to third main fuses 102, 103, and 104, '00', the least significant bit, is a state in which only the master fuse 101 is blown, and '01 is a master fuse. (101) and the state blown the first main fuse 102, '10' is the state blown the master fuse 101, the first main fuse 102 and the second main fuse 103, '11' The master fuse 101 and the first to third main fuses 102, 103, and 104 may all be defined as a blown state to implement 4 bits using one electrical fuse.

As such, the electrical fuse according to an embodiment of the present invention includes a master fuse 101 composed of transistors and a plurality of main fuses composed of capacitors, so that the electrical fuse implements a mult bit, thereby forming a conventional electrical fuse. The same effect as implementing a plurality of electrical fuses in the area can be realized. Therefore, the degree of integration of the electrical fuse and the degree of integration of the semiconductor device including the electrical fuse can be effectively improved.

In addition, since the degree of integration of the electrical fuse can be increased without reducing the size of the electrical fuse, it is possible to prevent deterioration of operating characteristics due to the decrease in the size of the electrical fuse.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

21 substrate 22 device isolation film
23: gate insulating film 24: gate electrode
25: gate hard mask film 26: gate
27: junction area 28: pickup area
29: conductive pattern 30A: first plug
30B: second plug 30: plug
33 lower electrode 34 dielectric film
35: upper electrode 38: first conductive line
39: second conductive line 40: third conductive line
41: 4th Challenge Line 101: Master Fuse
102: first main fuse 103: second main fuse
104: the third main fuse

Claims (13)

A master fuse consisting of a transistor;
A plurality of main fuses composed of capacitors;
A plurality of plugs connected between the gate electrode of the master fuse and each of the main fuses; And
Conductive pattern connected to all the plugs
Electrical fuse of the semiconductor device comprising a.
Claim 2 has been abandoned due to the setting registration fee. The method of claim 1,
The plurality of main fuses are electrical fuses of the semiconductor device positioned on the master fuse and overlap each other.
Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1,
The master fuse and the main fuse is connected in series, a plurality of the main fuse is an electrical fuse of the semiconductor device connected in parallel.
Claim 4 was abandoned when the registration fee was paid. The method of claim 1,
The master fuse,
The gate electrode formed on the substrate;
A gate insulating film interposed between the substrate and the gate electrode;
A junction region formed on the substrate on both sides of the gate electrode; And
A pickup region formed on the substrate and spaced apart from the gate electrode by a predetermined interval to surround the gate electrode
Electrical fuse of the semiconductor device comprising a.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein
The master fuse
An electrical fuse of any one of the junction region and the pickup region.
Claim 6 was abandoned when the registration fee was paid. The method of claim 1,
The plug may include a first plug connecting the conductive pattern and the gate electrode of the master fuse and a second plug connecting the conductive pattern and the lower electrode of the main fuse. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1,
The main fuse is an electrical fuse of a semiconductor device composed of one capacitor.
Claim 8 was abandoned when the registration fee was paid. The method of claim 1,
The main fuse is an electrical fuse of a semiconductor device composed of a plurality of capacitors connected in parallel.
Claim 9 was abandoned upon payment of a set-up fee. The method according to claim 7 or 8,
The capacitor is an electrical fuse of the semiconductor device having a cylindrical or concave form.
Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 1,
And a conductive line connected to the conductive pattern and the upper electrodes of the plurality of main fuses, respectively.
A master fuse formed on the substrate and composed of a transistor; A plurality of main fuses composed of capacitors; A plurality of plugs connected between the gate electrode of the master fuse and each of the main fuses; And a plurality of main fuses are sequentially blown after the master fuse is first blown in an electrical fuse including a conductive pattern connected to all the plugs.
Claim 12 was abandoned upon payment of a registration fee. The method of claim 11,
Blowing of the master fuse is applied to the main fuse and the conductive pattern by applying a high voltage equal to or greater than a power supply voltage, and a low voltage below ground voltage to the substrate.
Claim 13 was abandoned upon payment of a registration fee. The method of claim 11,
The blowing of the main fuse is performed by applying a high voltage of more than a power supply voltage to the conductive pattern and the substrate while the master fuse is blown, and applying a low voltage of less than ground voltage to the main fuse to be blown. How to drive a fuse.

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