KR101096235B1

KR101096235B1 - Electrical fuse in semiconductor device

Info

Publication number: KR101096235B1
Application number: KR1020100021871A
Authority: KR
Inventors: 인성욱
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-03-11
Filing date: 2010-03-11
Publication date: 2011-12-22
Also published as: KR20110102714A

Abstract

The present invention relates to an electrical fuse of a semiconductor device, comprising: a gate formed on a substrate and having a plurality of open regions; First, second, and third impurity regions formed on the substrate on one side of the gate, on the substrate on the other side of the gate, and on a substrate under the open region and partially overlap with the gate, respectively; A first conductive line to which a portion of the third impurity region and the first impurity region are connected; And a second conductive line having a second conductive line connected to the remaining third impurity region and the second impurity region, and having a third impurity region to increase an area where the gate and the impurity region overlap. In this way, it is possible to stabilize the operating characteristics of the electrical fuse, thereby improving the reliability of the semiconductor device having the electrical fuse.

Description

ELECTRICAL FUSE IN SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacturing technology of semiconductor devices, and more particularly, to electrical fuses of semiconductor devices.

In semiconductor devices, fuses are used in various ways for repairing defective cells, storing chip identifications, and circuit customization. For example, among the numerous cells of the memory device, the cells found to be defective cells may be replaced by redundancy cells by the fuses. Accordingly, it is possible to solve the problem of lowering yield due to defects in some cells.

The fuse may be classified into a laser blowing type and an electrical blowing type. In the case of the laser blowing type, a method of blowing a fuse line with a laser beam is used. However, when irradiating a laser beam to a specific fuse line, there is a fear that the fuse line or other elements around the specific fuse line is damaged.

On the other hand, in the case of the electric blowing type, a method of blowing a fuse current by applying a programming current to the fuse link and blowing the fuse by electromigration and joule heating is used. The electric blowing method can be used even after the package assembly of the semiconductor chip is completed, and the fuse device employing the method is called an electrical fuse.

In general, a MOS transistor is used as an electrical fuse, and an electrical fuse of a method of breaking a gate insulating film of the MOS transistor is cut.

1A and 1B are diagrams illustrating electrical fuses of a semiconductor device according to the related art. FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A.

Referring to FIGS. 1A and 1B, an electrical fuse of a semiconductor device according to the related art will be described. A gate 14 formed on a substrate 11 and a gate 14 formed on both sides of the gate 14 may partially overlap the gate 14. And a plurality of second and third contact plugs formed on the second impurity regions 15 and 16 and the first contact plug 14A formed on the gate 14 and the first and second impurity regions 15 and 16. And first, second and third conductive lines 14B, 15B and 16B connected to 15A and 16A and the first, second and third contact plugs 14A, 15A and 16A, respectively. In this case, the gate 14 is a stacked structure in which the gate insulating film 12 and the gate electrode 13 are stacked.

An operation in which the electric fuse having the above-described structure is used for repairing a defective cell will be described as follows.

First, a high voltage (eg, a power supply voltage or higher) is applied to the gate 14 of the electrical fuse connected to the redundancy cell that reads the address value of the defective cell and replaces the defective cell, and the first and second impurity regions 15 and 16. A low voltage (eg, below ground voltage) is applied to generate a large potential difference between the gate 14 and the first and second impurity regions 15 and 16. The large potential difference between the gate 14 and the first and second impurity regions 15 and 16 causes a breakdown of the gate insulating film 12, resulting in the gate 14 and the first and second impurity regions 15. , The gate insulating film 12 in the region A where 16 overlaps with each other is destroyed.

The electric fuse in which the gate insulating film 12 is destroyed is a gate 14, specifically, the gate electrode 13 and the first and second impurity regions 15 and 16 are electrically connected to act as a resistor having a predetermined resistance value. do. At this time, the repair is performed in a manner of determining whether to replace the redundancy cell based on the resistance value of the blown electrical fuse.

Here, the gate insulating film 12 in the region where the gate 14 and the first and second impurity regions 15 and 16 overlap (hereinafter, referred to as the overlap region, A) must be destroyed, but it is not determined whether the electrical fuse is blown. A stable resistance value that can be judged can be obtained.

However, in the electric fuse according to the related art, the area of the overlap region A is different from the overlap region A such that the gate insulating film 12 in the region where the gate 14 and the substrate 11 overlap each other is destroyed. There is a problem. As such, when the resistance value of the electrical fuse in which the gate insulating film 12 in the overlapping region A is destroyed is referred to as a reference resistance value, the blown electrical fuse is generated when the gate insulating film 12 in the region other than the overlapping area A is destroyed. Since the resistance value of is increased than the reference resistance value, a problem arises in that the blown electrical fuse is recognized as an unblown electrical fuse.

In addition, in consideration of the above-mentioned problem, in setting the reference resistance value for determining whether the electrical fuse is blown, the variation is so large that it is difficult to stably set the reference resistance value for determining whether the electrical fuse is blown. There is this.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an electrical fuse of a semiconductor device capable of increasing an area where a gate and an impurity region overlap.

Another object of the present invention is to provide an electrical fuse of a semiconductor device in which reference resistance values can be easily set for determining whether the electrical fuse is blown.

According to an aspect of the present invention, a gate is formed on a substrate and has a plurality of open regions; First, second, and third impurity regions formed on the substrate on one side of the gate, on the substrate on the other side of the gate, and on a substrate under the open region and partially overlap with the gate, respectively; A first conductive line to which a portion of the third impurity region and the first impurity region are connected; And a second conductive line connected to the remaining third impurity region and the second impurity region.

The present invention may further include a spacer formed on sidewalls of the gate and sidewalls of the open region. At this time, the area of the open area preferably has the same or larger than the sum of twice the thickness of the spacer and the minimum area to be opened for ion implantation.

In addition, the present invention includes a plurality of first contact plugs formed on the first impurity region and connecting the first conductive line and the first impurity region; A plurality of second contact plugs connecting between the second conductive line formed on the second impurity region and the second impurity region; And a third contact plug formed in the third impurity region and connecting between the third impurity region and the first conductive line or the second conductive line.

Preferably, the gate includes an even number of the open regions, and a ratio of the number of the third impurity regions connected to the first conductive line and the number of the third impurity regions connected to the second conductive line is 5. It is preferable that it is: 5.

The open area may include a slit pattern extending in the width direction of the gate and a slit pattern extending in the longitudinal direction of the gate. In this case, the first and second conductive lines may have a '-' shape facing each other.

In addition, the open area may include a rectangular pattern and have a structure in which the rectangular pattern is arranged in a matrix form. In this case, the first and second conductive lines may have a rectangular shape or may have a '-' shape facing each other.

The gate may have a structure having a larger gate width than the gate length.

The first, second and third impurity regions may have the same conductivity type.

The present invention based on the above-described problem solving means has an effect of increasing the area where the gate and the impurity region overlap by having a third impurity region formed in the substrate under the open region and partially overlapping the gate.

Therefore, the present invention has an effect of increasing the probability that the gate insulating film is destroyed in the region where the gate and the impurity region overlap when blowing the electrical fuse. This means that the probability that the gate insulating film is destroyed in a region other than the region where the gate and the impurity region overlap is reduced, so that the reference resistance value for determining whether the electrical fuse is blown can be set more easily.

As a result, the present invention can increase the area where the gate and the impurity region overlap, thereby stabilizing the operating characteristics of the electrical fuse and improving the reliability of the semiconductor device having the electrical fuse.

1A is a plan view showing an electrical fuse of a semiconductor device according to the prior art.
FIG. 1B is a cross-sectional view taken along the line II ′ of FIG. 1A showing an electrical fuse of a semiconductor device according to the prior art. FIG.
2A is a plan view showing an electrical fuse of a semiconductor device according to the first embodiment of the present invention.
FIG. 2B is a cross-sectional view of the electric fuse of the semiconductor device according to the first embodiment of the present invention, taken along the line II ′ shown in FIG. 2A; FIG.
3 is a plan view showing an electrical fuse of a semiconductor device according to a second embodiment of the present invention.
4A and 4B are plan views illustrating electrical fuses of the semiconductor device according to the third embodiment of the present invention.
FIG. 5 is a plan view illustrating precautions when designing an open area in an electrical fuse of a semiconductor device according to the first to third embodiments of the present invention; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The present invention, which will be described later, may increase an overlap area between a gate and an impurity region (i.e., source and drain regions) in an electrical fuse of a semiconductor device using a MOS transistor, and may refer to a reference resistor for determining whether an electrical fuse is blown. Provided is an electrical fuse of a semiconductor device with easy setting of values.

Hereinafter, embodiments of the present invention will be described in detail with respect to methods for increasing the area where the gate and the impurity region overlap with each other within the same size (or area) as the electric fuse according to the prior art.

2A and 2B are diagrams illustrating an electrical fuse of a semiconductor device according to a first embodiment of the present invention. FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A. .

As shown in FIGS. 2A and 2B, the electrical fuse of the semiconductor device according to the first embodiment of the present invention is formed on the substrate 21 and has a gate 24 and a gate having a plurality of open regions 25. A spacer 31 formed on the sidewall of the substrate 24, a first impurity region 26A formed on the substrate 21 on one side of the gate 24 and partially overlapping the gate 24, and the substrate 21 on the other side of the gate 24. A second impurity region 26B formed in the portion of the substrate 24 and partially overlapping the gate 24, and a third impurity region 26C formed in the substrate 21 under the open region 25 and partially overlapping the gate 24, and the first impurity region 26B. A plurality of first contact plugs 27A formed on the impurity region 26A, a plurality of second contact plugs 27B formed on the second impurity region 26B, and a third formed on the third impurity region 26C The contact plug 27C, the fourth contact plug 27D formed on the gate 24, the first conductive line 28 connected to the plurality of first contact plugs 27A and some third contact plugs 27C, and a plurality of contact plugs 27C. Of Third conductive line connected to the second conductive line 29B and the fourth contact plug 27D connected to the second contact plug 27C and the remaining third contact plug 27C not connected to the first conductive line 28B. (30). Here, the open area 25 of the electrical fuse according to the first embodiment of the present invention is a slit pattern extending in the width direction of the gate 24.

The gate 24 may be a stacked structure in which the gate insulating layer 22 and the gate electrode 23 are sequentially stacked. The gate insulating layer 22 may include an oxide layer, for example, a silicon oxide layer, and the thickness of the gate insulating layer 22 may be adjusted in consideration of the size of the bias applied to the electrical fuse for blowing. The gate electrode 23 may include a single film made of a silicon film or a metal film, or a laminated film in which a silicon film and a metal film are stacked.

The spacer 31 formed on the sidewall of the gate 24 is also located on the sidewall of the open region 25 and may be any single film selected from the group consisting of an insulating material, for example, an oxide film, a nitride film, and an oxynitride film, or a stacked film in which they are stacked. have. In this case, the spacer formed on the sidewall of the open region 25 serves to electrically separate between the third contact plug 27C and the gate.

The first to third impurity regions 26A, 26B, and 26C serve as junction regions (ie, source and drain regions), and are preferably formed to have the same conductivity type as each other. The first to third impurity regions 26A, 26B, and 26C preferably have a conductivity type complementary to that of the substrate 21. For example, the substrate 21 is P-type when the first to third impurity regions 26A, 26B, and 26C are N-type, and the substrate is P-type when the first to third impurity regions 26A, 26B and 26C are P-type. It is preferable that 21 is N type.

At least two or more open regions 25 formed in the gate 24 are preferable. In addition, it is preferable that a plurality of open regions 25 are provided in an even number. This is because a part of the third impurity region 26C formed in the substrate 21 under the open region 25 is connected to the first impurity region 26A, and the remaining third impurity region 26C is the second impurity region 26B. In order to balance the two ends when different biases are applied to the first conductive line 28 and the second conductive line 29 between the operation. Therefore, the ratio of the number of the third impurity regions 26C connected to the first conductive line 28 and the number of the third impurity regions 26C connected to the second conductive line 29 is 5: 5 so that the ratio of the first and the third impurity regions 26C is 5: 5. It is preferable to arrange the second conductive lines 28 and 29. For example, the first conductive line 28 may have a 'b' shape, and the second conductive line 29 may have a 'a' shape. That is, the first and second conductive lines 28 and 29 may have a 'a' or 'b' shape facing each other.

In the electrical fuse according to the first embodiment of the present invention having the above-described structure, the gate 24 includes a plurality of open regions 25, and is formed in the substrate 21 under the open region 25 so that the gate 24 is provided. And the third impurity region 26C partially overlapping each other, it is possible to increase the area of the region where the gate 24 and the impurity region overlap. Specifically, in the case of the prior art illustrated in FIGS. 1A and 1B, the area of the gate 24 and the impurity region overlap with the area of the gate 24 is in the range of 4% to 6%, but the first aspect of the present invention. The electric fuse according to the embodiment has an area of 20% to 30% of the area where the gate 24 and the first to third impurity regions 26A, 26B, and 26C overlap with the area of the gate 24.

As such, as the area of the overlapping area of the gate 24 and the first to third impurity regions 26A, 26B, and 26C increases, the gate insulating film 22 of the overlapping area may be broken when the electric fuse is blown. You can increase the probability. This means that the probability that the gate insulating film 22 is destroyed in a region other than the region where the gate 24 and the impurity region overlap is reduced, so that the reference resistance value for determining whether the electrical fuse is blown is more easily set. Can be. Therefore, in using the electrical fuse, the present invention can further stabilize the operating characteristics of the electrical fuse, thereby improving the reliability of the semiconductor device including the same.

3 is a plan view illustrating an electrical fuse of a semiconductor device according to a second exemplary embodiment of the present invention. Here, the same reference numerals are used for the same components in the first embodiment of the present invention, and detailed description thereof will be omitted.

As shown in FIG. 3, the electrical fuse of the semiconductor device according to the second exemplary embodiment of the present invention has the same configuration as that of the electrical fuse according to the first exemplary embodiment of the present invention, and includes an open region formed in the gate 24. 25 is a slit pattern extending in the length direction of the gate 24. For reference, the spacer 31 formed on the sidewall of the gate 24 and the sidewall of the open region 25 is not shown in FIG. 3, but is not shown in order to clearly reveal a positional convention.

In general, an electric fuse using a MOS transistor has a larger width of the gate 24 than the length of the gate 24 in order to obtain operating characteristics (usually, the electric fuse has a gate length of '1'. When the open area 25 is formed in a slit pattern extending in the longitudinal direction of the gate 24, more open areas 25 can be formed in a limited area than in the first embodiment of the present invention. There is an advantage. As such, as more open regions 25 are formed in the limited area, the area where the gate 24 and the third impurity region 26C overlap may be increased.

Therefore, the electric fuse of the semiconductor device according to the second embodiment of the present invention has an area of an area where the gate 24 and the first to third impurity regions 26A, 26B, and 26C overlap with each other than the first embodiment of the present invention. Since it can increase the probability that the gate insulating film 22 in the region where they overlap, it can be further increased, and it is possible to more easily set the reference resistance value for determining whether the electrical fuse blows.

4A and 4B are plan views illustrating electrical fuses of the semiconductor device according to the third embodiment of the present invention. Here, the same reference numerals are used for the same components in the first embodiment of the present invention, and detailed description thereof will be omitted.

As shown in FIGS. 4A and 4B, the electrical fuse of the semiconductor device according to the third embodiment of the present invention has the same configuration as that of the electrical fuse according to the first embodiment of the present invention, but is formed in the gate 24. The open area 25 has a rectangular (or square) pattern and has a structure arranged in a matrix form. For reference, in FIGS. 4A and 4B, the spacer 31 formed on the sidewall of the gate 24 and the sidewall of the open region 25 is not shown, but the illustration is omitted for clarity.

In addition, as the open area 25 of the rectangular pattern is disposed in a matrix form, as shown in FIG. 4A, the first and second conductive lines 28 and 29 are rectangular in shape, or as shown in FIG. 4B. The first and second conductive lines 28 and 29 may be in the 'a' or 'b' shape facing each other. In this case, when the first and second conductive lines 28 and 29 have a rectangular shape, the difficulty of the design and manufacturing process may be reduced since the pattern is simple.

In general, an electric fuse using a MOS transistor has a larger width of the gate 24 than the length of the gate 24 in order to obtain operating characteristics (usually, the electric fuse has a gate length of '1'. 10) more open regions 25 can be formed in a limited area than in the first and second embodiments of the present invention when the open regions 25 are formed in a square pattern arranged in a matrix form. There is an advantage. As such, as more open regions 25 are formed in the limited area, the area in which the gate 24 and the third impurity region 26C overlap may be increased.

Therefore, in the electrical fuse of the semiconductor device according to the third embodiment of the present invention, the gate 24 and the first to third impurity regions 26A, 26B, and 26C overlap each other than the first and second embodiments of the present invention. Since the area of the region can be increased, it is possible to further increase the probability that the gate insulating film 22 in the region where they overlap is broken, and the reference resistance value for determining whether the electric fuse is blown can be set more easily. .

The electrical fuses of the semiconductor device according to the first to third embodiments of the present invention described above are formed in the substrate 21 under the open region 25 to stably stabilize the third impurity region 26C partially overlapping the gate 24. In order to form, the following matters should be observed in designing (or implementing) the open area 25. This will be described in detail with reference to FIG. 5.

FIG. 5 is a plan view illustrating precautions when designing an open area in an electrical fuse of a semiconductor device according to the first to third embodiments of the present invention.

S = (2 × T) + α

Here, 'S' is the area of the open area 25, 'T' is the thickness of the spacer 31, 'α' means the minimum area (Minmum open size for implantation) to be opened for ion implantation.

Specifically, the third impurity region 26C is formed by ion implanting impurities into the substrate 21 exposed through the open region 25 using the gate 24 and the spacer 31 as an ion implantation barrier. Therefore, in the process of forming the open area 25 by patterning the gate 24, the area of the open area 25 or the area of the substrate 21 exposed by the open area 25 is the sidewall of the open area 25. It is preferable to form an area having a size equal to or larger than the sum of the open areas for ion implantation sufficient to twice the thickness of the spacer 31 formed on the substrate.

The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

21 substrate 22 gate insulating film
23: gate electrode 24: gate
25: open area 26A: first impurity area
26B: second impurity region 26C: third impurity region
27A: 1st contact plug 27B: 2nd contact plug
27C: 3rd contact plug 27D: 4th contact plug
28: first conductive line 29: second conductive line
30: third conductive line 31: spacer

Claims

A gate formed on the substrate;
A plurality of open regions formed in the gate to expose the substrate;
First, second, and third impurity regions formed on the substrate on one side of the gate, on the substrate on the other side of the gate, and on a substrate under the open region and partially overlap with the gate, respectively;
A first conductive line to which a portion of the third impurity region and the first impurity region are connected; And
A second conductive line connecting the remaining third impurity region and the second impurity region
Electrical fuse of the semiconductor device comprising a.

Claim 2 has been abandoned due to the setting registration fee.

The method of claim 1,
And a spacer formed on sidewalls of the gate and sidewalls of the open region.

Claim 3 was abandoned when the setup registration fee was paid.

The method of claim 1,
The area of the region in which the gate and the first to third impurity regions overlap with the gate area ranges from 20% to 30%.

Claim 4 was abandoned when the registration fee was paid.

The method of claim 1,
A plurality of first contact plugs formed on the first impurity region and connecting the first conductive line and the first impurity region;
A plurality of second contact plugs connecting between the second conductive line formed on the second impurity region and the second impurity region; And
A third contact plug formed in the third impurity region and connecting between the third impurity region and the first conductive line or the second conductive line
Electrical fuse of the semiconductor device further comprising.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 1,
And the gate has an even number of open regions.

Claim 6 was abandoned when the registration fee was paid.

The method according to claim 1 or 5,
And the ratio of the number of the third impurity regions connected to the first conductive line and the number of the third impurity regions connected to the second conductive line is 5: 5.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 1,
And the open area is a slit pattern extending in the width direction of the gate.

Claim 8 was abandoned when the registration fee was paid.

The method of claim 1,
And the open area is a slit pattern extending in the longitudinal direction of the gate.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 1,
The open area includes a rectangular pattern, the electrical fuse of the semiconductor device having a structure in which the rectangular pattern is arranged in a matrix form.

Claim 10 was abandoned upon payment of a setup registration fee.

10. The method of claim 9,
The first and second conductive lines have an electric fuse of a rectangular shape.

Claim 11 was abandoned upon payment of a setup registration fee.

The method according to any one of claims 7 to 9,
And the second conductive line has a 'b' shape facing the first conductive line when the first conductive line has a 'b' shape.

Claim 12 was abandoned upon payment of a registration fee.

The method according to any one of claims 7 to 9,
The gate is an electrical fuse of a semiconductor device having a gate width that is greater than a gate length.

Claim 13 was abandoned upon payment of a registration fee.

The method of claim 1,
And the first, second and third impurity regions have the same conductivity type as each other.