KR101102974B1 - non-volatile memory cell and non-volatile memory - Google Patents

Abstract

The present invention relates to a nonvolatile memory cell structure and a nonvolatile memory for data storage such as an EEPROM.

A nonvolatile memory cell of the present invention includes a bit through line and a bit bar line to which a data read circuit and a data write circuit are connected; True Flash Morse with a source connected to ground; Bar flash morse source connected to ground voltage; A true selector MOS having a source connected to the drain of the true flash MOS, a word line selection signal applied to a gate, and a drain connected to the bit true line; A source is connected to the drain of the bar flash morse, a word line selection signal is applied to the gate, and a drain includes a bar selector morse connected to the bit bar line, and selected from the true flash morse or the bar flash morse. It is characterized by writing 1-bit data by injecting electric charges.

By implementing the nonvolatile memory according to the present invention in which two flash MOSs are allocated per bit, the leading margin can be extended to the threshold voltage swing width of the recording cell, and the flash MOS itself of the nonvolatile memory cell of the present invention. Since the differential amplifier is configured at the time of reading, the speed of the reading operation can be improved and the power consumption of the reading operation can be reduced as compared with the prior art through a separate amplifier stage.

Nonvolatile Memory, EEPROM, Flash Memory, Differential Amplification, Reading Margin

Description

Non-volatile memory cell and non-volatile memory

1 is a circuit diagram showing a nonvolatile memory cell structure according to the prior art;

2 is a circuit diagram illustrating a nonvolatile memory cell unit structure according to the present invention;

3 is a circuit diagram showing the structure of a nonvolatile memory according to the present invention;

The present invention relates to a nonvolatile memory cell structure such as an EEPROM, a flash memory, and the like, and a nonvolatile memory constructed using the same.

1 shows a circuit structure of a conventional EEPROM memory cell array. In the illustrated structure, one write flash morse is allocated to record one bit of data, and one reference morse for generating a reference voltage exists in a cell array composed of n write flash morses that share a specific address. do.

By comparing the threshold voltage of the recording flash morse to be read with the threshold voltage of the reference morse, when the threshold voltage of the recording flash morse is larger, the current passing through the recording flash morse becomes smaller, thereby being charged from the power supply voltage terminal. The charge further increases the NMOS transistor gate voltage on the left path of the sense amplifier. The gate voltage increase is amplified by the sense amplifier so that the sense amplifier output terminal has a high value, and the output DOUT of the output inverter connected to the sense amplifier output terminal has a low value. On the contrary, when the threshold voltage of the reference Morse is larger, the output DOUT of the output inverter has a high value through the same process.

At this time, the threshold voltage (Vth_write) of the recorded (set) recording cell, the threshold voltage (Vth_erase) of the erased (reset) recording flash MOS, the threshold voltage (Vth_ref) of the reference cell, and the voltage margin (ΔVth) In general, the relationship between is as shown in Equation 1, and in this case, the difference between the threshold voltage of the recording flash MOS and the threshold voltage of the reference cell is greatest.

Vth_ref = (Vth_erase + Vth_write) / 2

ΔVth = | Vth_erase-Vth_write | / 2

In the above equation, it can be seen that there is a problem inherent in that the reading margin of the memory cell according to the prior art cannot be extended beyond ΔVth.

The present invention has been made to solve the above problems, and an object thereof is to provide a memory cell capable of extending the leading margin to the threshold voltage swing width of the write flash morse.

It is another object of the present invention to provide a memory cell that performs a fast reading operation.

Another object of the present invention is to provide a memory cell capable of reducing power consumption during reading.

A nonvolatile memory cell of the present invention for achieving the above object includes a bit through line and a bit bar line to which a data read circuit and a data write circuit are connected; True Flash Morse with a source connected to ground; Bar flash morse source connected to ground voltage; A true selector MOS having a source connected to the drain of the true flash MOS, a word line selection signal applied to a gate, and a drain connected to the bit true line; A source is connected to the drain of the bar flash morse, a word line selection signal is applied to the gate, and a drain includes a bar selector morse connected to the bit bar line, and selected from the true flash morse or the bar flash morse. It is characterized by writing 1-bit data by injecting electric charges.

As described above, the present invention is not only characterized by assigning two flash morse to 1-bit data recording, but also has another feature that the flash morse functions as one of the sense amplifier components when reading recorded data. . The latter feature is implemented as a nonvolatile memory cell of the above structure and a read circuit therefor, which will be described in the following embodiments.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms or words used in the specification and claims should not be construed as having a conventional or dictionary meaning, and the inventors should properly explain the concept of terms in order to best explain their own invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

(Example)

2 shows a connection between a unit memory cell constituting the nonvolatile memory of the present embodiment, a sense amplifier structure, and a write block.

The nonvolatile memory of the present exemplary embodiment includes a bit true line BL and a bit bar line BBL to which a data lead circuit and a data write circuit are connected, a true flash MOS having a source connected to a ground voltage terminal, and a source. True select switch (ST) and cell select for connecting the bit flash line (BL) to the drain of the true flash morse (FT) by receiving the bar flash morse (FB) and the cell select signal (WL) connected to the ground voltage terminal. A nonvolatile memory cell (100) having a bar select switch (SB) for receiving a signal (WL) and connecting a drain of the bar flash morse (FB) and a bit bar line (BBL); And

A true sensing MOS LT having a source connected to a power supply voltage terminal VDD, a gate connected to a drain of a sensing bar LB, and a drain connected to a bit true line BL; A source is connected to the power supply voltage terminal (VDD), the gate is connected to the drain of the true sensing MOS (LT), the drain comprises a bar sensing MOS (LB) connected to the bit bar line (BBL) do.

The basic device for writing data in nonvolatile memory is Flash Morse, a type of MOS transistor with a double gate. The gate of the flash morse includes a control gate connected to the outside and a floating gate implemented as a dielectric to maintain charge. When a high potential is applied to the control gate while a potential in the conductive direction is applied to the drain and the source, charge is stably stored in the floating gate made of a dielectric material, which lowers the threshold voltage of the flash MOS. Writing of data is performed by storing charge in the floating gate, and reading of data is performed by detecting a threshold voltage of the flash MOS.

In this embodiment, the nonvolatile memory cell (unit cell) 100 for writing one bit data includes two flash MOSs FT and FB, and the threshold voltages of the two flash MOSs FT and FB. The data is read / written as the right rank of the data, and the bit line connected to the unit cell 100 also contains the data as the potential difference between the bit true line BL and the bit bar line BBL. Similarly, the lead line D-OUT, DB-OUT) and light lines (D-IN, DB-IN) are also paired to perform data transfer.

The nonvolatile memory may further include a true write select switch WST for receiving a write select signal WR_SEL and connecting a true write line D-IN to the bit true line BL; And a bar light select switch WSB configured to receive the write select signal WR_SEL and connect the bar light line DB-IN to the bit bar line BBL.

By turning on the true / bar light select switches WST and WSB, the bit true line BL and the bit bar line BBL are connected to a light driver (not shown). The write driver may be implemented to drive 1-bit data as a potential difference of a pair of lines.

Data writing is basically performed by erasing before writing the unit memory cell 100 of the structure to a state having a high threshold voltage, and then writing the input bit value. When writing 1-bit data, write charge is injected to only one selected from two flash MOSs FT and FB constituting the unit memory cell 100 to lower the threshold voltage, which is opposite to the D-IN and DB-IN terminals. It can be easily implemented by applying data.

In addition, the nonvolatile memory of the present embodiment includes: a true reading select switch RST for receiving a reading select signal RD_SEL and connecting a drain of the true sensing Morse LT to a bit true line BL; And a bar leading select switch RSB for receiving a leading select signal RD_SEL and connecting a drain of the bar sensing morse LB to a bit bar line BBL.

When writing data, a row is applied as the leading select signal RD_SEL to block the sensing pairs LT and LB and the bit line pairs BL and BBL, thereby operating the sensing pairs LT and LB. It is desirable to prevent miswriting by

On the other hand, when reading data, a high (turn-on value) is applied as the leading select signal RD_SEL to connect the sensing MOS pairs LT and LB to the bit line pairs BL and BBL. In addition, a high (turn-on value) is applied to the cell select signal WL at the time of read so that the flash MOS pairs FT and FB are connected to the bit line pairs BL and BBL.

That is, in the process of reading data written in the memory cell 100, low and high are input as the write select signals WR_SEL and WR_SELB to block the bit line pairs BL and BBL and the write driver (not shown). Next, a turn-on value (high) is applied as the read select signal RD_SEL and the cell select signal WL to connect the flash MOS pairs FT and FB to the sensing MOS pairs LT and LB.

Then, it can be seen that the flash MOS pairs FT and FB and the sensing MOS pairs LT and LB have a structure of a kind of sense amplifier performing differential amplification. The threshold voltage of the true flash Morse FT and the threshold voltage of the bar flash Morse FB become input signals of the sense amplifier, the drain voltage of the true sensing Morse LT, and the drain of the bar sensing Morse LB. The voltage becomes an output signal of the sense amplifier. Accordingly, a true output line D-OUT connected to a reading latch (not shown) is connected to a drain of the true sensing morse LT, and a bar output line DB-OUT connected to the reading latch is the bar sensing. It is preferable to be connected to the drain of the MOS (LB).

FIG. 3 illustrates a structure of a nonvolatile memory in which memory cell metrics 100, 101, 110, and 111 in which a plurality of unit memory cells are arranged. The illustrated nonvolatile memory has a two-dimensional address space consisting of a first address space and a second address space, and the nonvolatile memory cells 100, 101, 110, and 111 according to claim 1 for each address of the address space. Is assigned a memory cell matrix; A cell select line WL0 commonly connected to the gates of the true selectors Morse ST00 and ST01, ST10 and ST11 of the memory cells sharing the first address, and the gates of the bar selector Morse SB00 and SB01, SB10 and SB11. WL1); The bit true line BL which is commonly connected to the drains of the true selector Morse (ST00 and ST10, ST01 and ST11) of the memory cells sharing the second address; The bit bar line BBL commonly connected to a drain of a bar selector Morse SB00 and SB10 and SB01 and SB11 of memory cells sharing the second address; A true sensing MOS LT having a source connected to a power supply voltage terminal VDD, a gate connected to a drain of a sensing bar LB, and a drain connected to a bit true line BL; And a bar sensing morse LB having a source connected to a power supply voltage terminal VDD, a gate connected to a drain of the true sensing morse LT, and a drain connected to a bit bar line BBL.

In accessing the nonvolatile memory of the above structure, the unit memory cell to be accessed is made using a word line address (first address) and a bit line address (second address). The cell select signal WL having a high (turn-on value) is applied only to the word line selected by the word line address. For example, in the drawing, if only WL0 is applied high, flash cells FT00, FB00, FT01, and FB01 of the top row are connected to each bit line pair BL0 and BBL0, BL1, and BBL1 in each bit line pair. The connection of each bit line pair BL0 and BBL0, BL1 and BBL1 to a reading latch (not shown) or a write driver (not shown) may be performed according to the read select signal RD_SEL and the write select signal according to the read / write mode. WR_SEL).

The specification of the unit memory cells 100, 101, 110, and 111 by the bit line address is based on the data output line D-OUT0, the data output terminal circuit including the reading latch and the data input terminal circuit including the write driver. By selection of DB-OUT0, D-OUT1, DB-OUT1 and data input lines D-IN0, DB-IN0, D-IN1, DB-IN1.

Naturally, the nonvolatile memory device of FIG. 3 may include all of the elements of FIG. 2, and descriptions of overlapping elements will be omitted.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It goes without saying that various modifications and variations are possible within the scope of equivalence of the scope.

By implementing the nonvolatile memory according to the present invention in which two flash MOSs are allocated to one bit as described above, the reading margin can be extended to the threshold voltage swing width of the recording cell.

In addition, since the flash MOS itself of the nonvolatile memory cell of the present invention constitutes a differential amplifier during reading, it is possible to improve the speed of the reading operation and to reduce the power consumption in the reading operation, as compared with the conventional technology through a separate amplifier stage. There is also an effect.

Claims (8)

A bit true line and a bit bar line to which the data lead circuit and the data write circuit are connected; True Flash Morse and Bar Flash Morse, each gate connected to a common control line and each source connected to a ground voltage terminal; A true selector MOS having a source connected to the drain of the true flash MOS, a word line selection signal applied to a gate, and a drain connected to the bit true line; And A source is connected to the drain of the bar flash MOS, a word line select signal is applied to a gate, and a bar selector MOS is connected to the bit bar line. Including; 1-bit data is written by injecting electric charge into a selected one of the true flash morse or the bar flash morse, And the True Selector Morse and Bar Selector Morse are of the same type and connected to a common word line. A bit true line and a bit bar line to which the data lead circuit and the data light circuit are connected, True Flash Morse and Bar Flash Morse, each gate connected to a common control line, each source connected to a ground voltage terminal, A true select switch configured to receive a cell select signal and connect a drain of the true flash MOS and a bit true line; A nonvolatile memory cell having a bar select switch configured to receive a cell select signal and to connect a drain of the bar flash morse to a bit bar line; And A true sensing MOS having a source connected to a power supply voltage terminal, a gate connected to a drain of a sensing bar below, and a drain connected to a bit true line; A reading block having a bar sensing moth having a source connected to a power supply voltage terminal, a gate connected to a drain of the true sensing morse, and a drain connected to a bit bar line. Including; And the true selector switch and the bar selector switch are turned on in a reading operation and a writing operation. 3. The method of claim 2, A true output line is connected to the drain of the true sensing morse, And a bar output line connected to a drain of the bar sensing moss. The method of claim 2, wherein the reading block, A true leading select switch for receiving a leading select signal and connecting a drain of the true sensing morse to a bit true line; And A bar leading select switch for receiving a leading select signal and connecting a drain of the bar sensing morse to a bit bar line Non-volatile memory further comprising. 3. The method of claim 2, A true light select switch configured to receive a light select signal and connect a true writing line to the bit true line; And And a bar light select switch configured to receive a write select signal and to connect a true writing line to the bit bar line. A memory cell matrix having a two-dimensional address space consisting of a first address space and a second address space, wherein a nonvolatile memory cell according to claim 1 is assigned to each address of the address space; A cell select line commonly connected to a gate of a true selector Morse and a gate of a bar selector Morse of the memory cells sharing the first address; The bit true line commonly connected to a drain of a true selector MOS of memory cells sharing the second address; The bit bar line commonly connected to a drain of a bar selector morse of memory cells sharing the second address; A true sensing MOS having a source connected to a power supply voltage terminal, a gate connected to a drain of a bar sensing MOS, and a drain connected to a bit true line; Bar sensing MOS whose source is connected to the power supply voltage terminal, the gate is connected to the drain of the true sensing MOS, and the drain is connected to the bit bar line. Non-volatile memory comprising a. The method of claim 6, A true leading select switch for receiving a leading select signal and connecting a drain of the true sensing morse to a bit true line; And A bar leading select switch for receiving a leading select signal and connecting a drain of the bar sensing morse to a bit bar line Non-volatile memory further comprising. The method of claim 6, A true light select switch configured to receive a light select signal and connect a true writing line to the bit true line; And And a bar light select switch configured to receive a write select signal and to connect a true writing line to the bit bar line.

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