JP2004005999A - Non-volatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a NAND cell type EEPROM having a cell array for achieving high-speed random reading and a sense-amplifying circuit, without increasing a chip area. <P>SOLUTION: The NAND cell type EEPROM has a memory cell array where a memory cell unit is arranged in a matrix, where the memory cell unit comprises a first selection MOS transistor STD for allowing a NAND cell where a plurality of nonvolatile memory cell arrays are connected in series to make conductive a bit line; and a second selection MOS transistor STS for allowing the NAND cell to make conductive a source line. In the NAND cell type EEPROM, a first memory cell unit, where the threshold of STD is larger than that of STS and a second memory cell, where the threshold of STD is smaller than that of STS share a gate electrode in each STD and each STS, to compose a subarray. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device using electrically rewritable nonvolatile memory cells.
[0002]
[Prior art]
2. Description of the Related Art In recent years, a NAND cell type EEPROM has been proposed as one of nonvolatile semiconductor memory devices (EEPROMs) capable of electrically rewriting and achieving high integration. This NAND cell type EEPROM includes a plurality of memory cells having an n-channel FET MOS structure in which, for example, a floating gate as a charge storage layer and a control gate are stacked via an insulating film on the floating gate, and their sources and drains are connected. A series connection is made in such a manner that adjacent ones share the same, and this is connected as a unit to a bit line.
[0003]
The drain side of the NAND cell is connected to a bit line via a first selection MOS transistor having a first selection gate as a gate electrode, and the source side is a second selection MOS transistor having a second selection gate as a gate electrode. Is connected to the source line. The control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction. Normally, a set of memory cells connected to the control gate is called one page, and a set of pages sandwiched by a set of drain-side and source-side select MOS transistors is called one NAND block or simply one block. The memory cell array is usually formed in a p-type well formed on an n-type semiconductor substrate.
[0004]
The operation of the NAND cell type EEPROM is as follows. Data writing is performed sequentially from the memory cell farthest from the bit line. A boosted write voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential (about 10 V) is applied to the control gate and the first select gate of the other unselected memory cells. 0V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell. When data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold value moves in the positive direction. When the data is "1", the threshold does not change.
[0005]
Data erasure is performed almost simultaneously on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate. Thereby, in all the memory cells, the electrons of the floating gate are emitted to the well, and the threshold value moves in the negative direction.
[0006]
The data read operation is performed by setting the control gate of the selected memory cell to 0 V and setting the control gates of the other memory cells to the power supply voltage Vcc (for example, 3 V) to detect whether or not a current flows in the selected memory cell. Done. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current at the time of reading is small. Further, since the control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction, data for one page is simultaneously read out to the bit line.
[0007]
(Issue 1)
FIG. 30 shows a circuit example of a sense amplifier of a conventional NAND cell type EEPROM. Detection of the bit line potential by this sense amplifier is performed as follows. First, when an address is set and a read mode is set, the bit line precharge control signal PREB changes from Vcc to Vss, and the bit line BLj and the node N2 are charged to the power supply potential Vcc. Further, the sense amplifier SA is reset by setting the node N2 to Vcc and the node N1 to Vss. After the word line is selected, if the cell data is "0", the bit line potential is kept at Vcc, and if the cell data is "1", the bit line potential is discharged toward Vss. Then, after the bit line potential is determined, the bit line potential is transferred to the node N2.
[0008]
Next, SENB changes from Vcc to Vss, SEN changes from Vss to Vcc, and the clocked inverter INV1 is activated. If the potential of the node N2 is higher than the circuit threshold of the clocked inverter INV1, the node N1 is kept at Vss. If the potential of the node N2 is lower than the circuit threshold of the clocked inverter INV2, the node N1 becomes Vcc. , And the potential of the bit line BLj is detected. Thereafter, the clocked inverter INV2 is activated and the detected data is latched. When the column selection signal CSLj changes from Vss to Vcc, the latched data is output to I / O and I / O '.
[0009]
In this method, as described above, the cell data is detected depending on whether the potential of the floating bit line is higher or lower than the circuit threshold value of the clocked inverter. And changes depending on the state of the adjacent bit line. For example, when "0" data is written in the cell, no read current flows, and the potential of the bit line BLj should maintain the precharge potential Vcc. On the other hand, when "1" data is written in the cell connected to the adjacent bit line BLi and a read current is passed, the potential of the bit line BLi falls from Vcc to Vss. Then, the potential of the bit line BLj, which should hold Vcc, is dragged down by the potential of the adjacent bit line BLi, which drops from Vcc to Vss.
[0010]
Therefore, in order to correctly detect the bit line BLj as "0" data, the circuit threshold value of the clocked inverter INV1 is set lower in consideration of the change in the bit line potential due to the capacitive coupling between the bit lines. Must be set to In order to read the bit line BLi as "1" data, the potential of the bit line BLi must be reduced from Vcc to the circuit threshold of the clocked inverter INV1, and considering that the read current of the NAND cell is small. If the circuit threshold value of the clocked inverter INV1 is set lower, the time required to detect a bit line becomes longer.
[0011]
In a sense amplifier using a clocked inverter as shown in FIG. 30, it takes a long time to detect the bit line potential. This is exemplified below by using numerical values. Assuming that the capacity between adjacent bit lines occupies half of the total capacity of the bit lines, the bit line BLj that should keep Vcc is reduced to Vcc / 2 according to the adjacent bit line BLi. Assuming that the power supply voltage Vcc is, for example, 3V, BLj is reduced to 1.5V. Therefore, the circuit threshold value of the clocked inverter INV1 is set to, for example, 1.2 V with a margin. The cell current when the read current of the NAND cell is the smallest, that is, “1” is written in the selected cell and “0” is written in the non-selected cell is 1 μA. Further, assuming that the capacitance of the bit line is 3 pF, to discharge the potential of the bit line BLi to the circuit threshold value,
3 pF × (3-1.2) V / 1 μA = 5.4 μs
It will cost.
[0012]
As a method for solving the above problem, the input to the sense amplifier is made a pair of bit lines BLj and / BLj using a folded bit line system used in DRAM, and these are differentially operated to operate at high speed. May be read out. Taking the case of reading a cell connected to the bit line BLj as an example, the time for discharging the bit line is estimated. When the potential of the bit line / BLj is maintained at, for example, 1.5 V and the potential of the bit line BLj is precharged to 1.7 V, if the information of the cell connected to the bit line BLj is "0", the bit line BLj is changed to 1.7 V. If the bit line is kept at "1", the bit line should be discharged to 1.3V. Assuming that the cell current is 1 μA and the bit line capacitance is 3 pF, the time required to discharge the bit line is:
3 pF × (1.7-1.3) / 1 μA = 1.2 μs
And the reading speed is higher than in the conventional single-ended system.
[0013]
In the folded bit line system, when reading out a cell connected to the bit line BLj, the bit line / BLj must not be discharged. However, in the conventional NAND cell type EEPROM, the control gate of the memory cell and the first and second cells are not used. Since the selection gates are continuously arranged in the row direction, if "1" is written in both cells connected to the adjacent bit lines BLj and / BLj, the bit lines BLj and / BLj are simultaneously discharged. Will be done.
[0014]
As a method of not discharging the bit line / BLj when reading a cell connected to the bit line BLj, for example, the bit line BLj and the drain-side selection gate (or the source-side selection gate) of the bit line / BLj are operated at different timings. There is a method. For example, in order to operate the drain-side selection gate with the bit line BLj and the bit line / BLj at different timings, the control signal SGD1 for selecting the selection gate of the bit line BLj and the control signal SGD2 for selecting the bit line / BLj. Is required. Assuming that eight memory cells are connected in series between a bit line contact and a source line, in a conventional cell array, ten wirings (eight control gates and two selection gates) are arranged in the row direction per block. However, this method requires eleven wirings (eight control gates and three selection gates), so that the area of the cell array increases, resulting in a problem that the chip area increases.
[0015]
(Issue 2)
As described above, in the NAND cell type EEPROM, since the memory cells are connected in series, the cell current is small. It takes several μs to discharge the bit line and about 10 μs to perform random read. Data for one page is simultaneously detected and latched by the sense amplifier. The page read can be read in about 100 ns because only the latch data is read. For example, when reading one page of data with a page length of 256 bytes, one random read and 255 page reads are performed.
10 + 0.1 × 255-35 μs
It takes time. Therefore, when reading data over a plurality of pages, a random read operation of 10 μs is required in the page switching unit.
[0016]
As a method of reading the data of a plurality of pages in a page read cycle apparently without the random read operation at the time of page switching, for example, there is a method of dividing a memory cell array and a sense amplifier into two and performing random read and page read simultaneously. By performing a random read operation on one of the two divided memory cell arrays and performing a random read operation on the other, a plurality of memory cell arrays can be read while maintaining the page read timing without interposing a random read operation at a page switching point. Data across pages can be read.
[0017]
In the conventional memory cell array, in order to operate the memory cell array divided into two parts with the random read timing shifted, it is necessary to increase the number of peripheral circuits (such as row decoders) for transmitting a voltage to a word line. In particular, in the EEPROM, a transistor constituting a peripheral circuit (such as a row decoder) for transmitting a voltage to the word line has a large area because a high voltage of about 20 V is applied to the word line at the time of writing. Therefore, when this high-speed page read method is adopted in a conventional memory cell array, there is a problem that the chip area increases due to an increase in peripheral circuits (such as a row decoder) for transmitting a voltage to a word line.
[0018]
(Issue 3)
As the degree of integration increases and the distance between bit lines decreases, the capacitive coupling between bit lines increases. As a result, the potential of the bit line to be maintained in the “H; High” state at the time of reading drops from the “H” state by being dragged by the adjacent bit line discharging to the “L; Low” state. In order to reduce noise caused by the capacitive coupling between bit lines, a method (bit line shield) in which every other bit line is kept at a constant potential during reading has been proposed (Japanese Patent Laid-Open No. 4-276393). Since reading is performed on every other bit line in the bit line shield, data writing is also performed on every other bit line.
[0019]
In the conventional open bit line system or single-ended system using a cell array, adjacent bit lines share a select gate and a control gate, so that when reading cell data to one bit line, the adjacent bit lines The data is read out, resulting in discharge. Therefore, when using a method of keeping the bit line at a reference potential every other bit line (bit line shield) in order to reduce noise caused by capacitive coupling between bit lines, the reference potential must be set to 0V. As a result, when reading data written over a plurality of pages, for example, when reading data of a memory cell connected to an odd-numbered bit line after reading data of a memory cell connected to an even-numbered bit line, The even-numbered bit line read first discharges all the charges to 0V, and the odd-numbered bit line read second is precharged from 0V.
[0020]
That is, after reading the memory cell of the even-numbered bit line, at the time of page switching when reading the data of the odd-numbered bit line next, and after reading the memory cell of the odd-numbered bit line, It is necessary to discharge all the previously read bit lines and precharge all the next read bit lines from 0 V when switching the page when reading the data of the bit line. As described above, when the bit line shield is applied to the open bit line system and the single-ended system using the conventional cell array, there is a problem that reading requires a precharge time by switching pages and consumes a large amount of power.
[0021]
Next, a description will be given of a problem that occurs at the time of writing when the bit line shield is applied to an open bit line system or a single end system using a conventional memory cell array. When the bit line shield is applied as described above, writing is performed separately for the memory cells connected to the even-numbered bit lines and for the memory cells connected to the odd-numbered bit lines. Therefore, for example, when writing to a memory cell connected to an even-numbered bit line, writing is not performed to a memory cell connected to an odd-numbered bit line, so that an intermediate potential (10 V) is applied to the odd-numbered bit line. Degree). That is, at the time of writing, at least half of the bit lines must be charged to the intermediate potential.
[0022]
In the write operation, first, write is performed, and then verify read is performed to check whether the write has been sufficiently performed. Then, the additional writing is not performed on the sufficiently written cell, and the additional writing is performed only on the insufficiently written cell. In a conventional memory cell array, when a verify read is performed after writing a memory cell connected to an even-numbered bit line, the odd-numbered bit line is also discharged from the intermediate potential. Is written, the odd-numbered bit lines must be charged and discharged to an intermediate potential every write-verify read cycle, which causes a problem that the write time increases and the power consumption increases.
[0023]
As described in the above (Problem 1), the above (Problem 3) can be solved by changing the selection gate for controlling the selection MOS transistor by an adjacent bit line, but instead, the source and the bit line are interposed. One extra selection MOS transistor area is required for each NAND string, resulting in a problem that the chip area increases.
[0024]
[Problems to be solved by the invention]
(Issue 1)
As described above, the single-ended type sense amplifier used in the conventional nonvolatile semiconductor memory device has a problem that the read time is long. In addition, when a non-volatile semiconductor memory device implements a high-speed readout, that is, a folded bit line method used in a DRAM, the area of a cell array increases in a conventional nonvolatile semiconductor memory device. There is a problem that the chip area increases.
[0025]
(Issue 2)
As described above, in the conventional non-volatile semiconductor memory device, when reading data over a plurality of pages, random reading is required when switching word lines, so that there is a waste of time and a long reading time. There is. In order to solve this problem, a method has been proposed in which a memory cell array and a sense amplifier are divided into two and random read and page read are performed simultaneously. However, when this method is applied to a conventional nonvolatile semiconductor memory device, the chip area is reduced. There is a problem of increase.
[0026]
(Issue 3)
A bit line shield that keeps every other bit line at the reference potential when reading is applied to conventional open bit line and single-ended memory cell arrays in order to reduce noise caused by the coupling capacitance between bit lines. Then, since writing and reading are performed for every other bit line, it is necessary to charge and discharge the non-selected bit line to the intermediate potential (about 10 V) every write-verify read cycle. Further, when reading data over a plurality of pages, it is necessary to discharge a bit line to be shielded when switching pages and to precharge a bit line to be selected next. For this reason, there is a problem that power consumption is large at the time of writing and reading, and writing and reading are slow by the precharge time.
[0027]
The present invention has been made in view of the above circumstances, and has as its object to provide a nonvolatile semiconductor memory having a memory cell array and a sense amplifier circuit capable of high-speed random reading without increasing the chip area. It is to provide a device.
[0028]
Another object of the present invention is to provide a nonvolatile semiconductor device capable of performing a high-speed page read operation without increasing a chip area and eliminating a waste time generated when switching word lines.
[0029]
Still another object of the present invention is a problem that occurs when a bit line shield is applied to an open bit line system and a single-ended system using a conventional cell array, that is, data over a plurality of pages is read and written. An object of the present invention is to provide a semiconductor memory device capable of preventing an increase in power consumption and an increase in read / write time in such a case.
[0030]
[Means for Solving the Problems]
In order to solve the above problems, the present invention employs the following configuration.
[0031]
In one aspect of the present invention, a NAND cell unit in which a plurality of nonvolatile memory cells are connected in series and one end is connected to a bit line and the other end is connected to a source line, and a memory cell array including a plurality of the NAND cell units A read circuit for reading data stored in the NAND cell unit depending on whether or not the bit line is charged in advance and the NAND cell unit allows a current to flow from the bit line to the source line; and a read circuit connected to each bit line. A plurality of latch circuits for temporarily storing data read from the NAND cell unit; and a data output circuit for outputting the data of the latch circuit to the outside, and outputting the data of the latch circuit to the outside from the data output circuit. And reading data from the NAND cell unit. In the present nonvolatile semiconductor memory device, the following embodiments are preferable.
(1) The latch circuit further has a function of sensing a potential of a bit line.
[0032]
(2) A MOS transistor for controlling connection between the bit line and the latch circuit is provided between the bit line and the latch circuit.
[0033]
(3) The data of the plurality of latch circuits is divided into a plurality of times and output from the data output circuit to the outside.
[0034]
Further, according to one aspect of the present invention, in a nonvolatile semiconductor memory device, a nonvolatile memory portion including one or a plurality of nonvolatile memory cells, and the nonvolatile memory portion is electrically connected to a first common signal line. A first selection MOS transistor to be turned on, and a second selection MOS transistor that conducts the non-volatile memory section and the second common signal line and has a threshold different from that of the first selection MOS transistor. The memory cell unit has a memory cell array arranged in a matrix.
[0035]
Further, according to one aspect of the present invention, in a nonvolatile semiconductor memory device, a nonvolatile memory portion including one or a plurality of nonvolatile memory cells, and a first selection for making the nonvolatile memory portion conductive with a bit line. A memory cell unit composed of a MOS transistor and a second selection MOS transistor which conducts a source line to a nonvolatile memory portion and has a threshold different from that of the first selection MOS transistor is arranged in a matrix. And a memory cell array.
[0036]
Further, according to one aspect of the present invention, a nonvolatile memory unit including a plurality of nonvolatile memory cells, a first selection MOS transistor for making the nonvolatile memory unit conductive with a bit line, a nonvolatile memory unit and a source In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a line are arranged in a matrix, the first selection MOS transistor has a first threshold value. A first memory cell unit having Vth1 and a second selection MOS transistor having a second threshold value Vth2; and a first selection MOS transistor having a third threshold value Vth3 and a second selection MOS transistor. The second memory cell unit whose transistor has the fourth threshold value Vth4 is the same as that of the first selection MOS transistor. A gate array and a gate electrode of the second selection MOS transistor are shared as first and second selection gates, respectively, to form a sub-array, and the magnitude relationship between the first and third thresholds Vth1 and Vth3 and the second And the fourth threshold values Vth2 and Vth4 are opposite in magnitude relation.
[0037]
Further, according to one aspect of the present invention, a non-volatile memory unit including a plurality of non-volatile memory cells, a first selection MOS transistor for conducting the non-volatile memory unit to a bit line, and the non-volatile memory unit In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a source line are arranged in a matrix, the first selection MOS transistor is a first threshold. A first memory cell unit having a value Vth1 and a second selection MOS transistor having a second threshold Vth2, and a second selection MOS transistor having a third threshold Vth3 and a second selection MOS transistor The second memory cell unit in which the MOS transistor has the fourth threshold value Vth4 is connected to the first selection MOS transistor. Share to constitute a subarray of the gate electrode of the gate electrode and the second selecting MOS transistor as the first and second selection gates each,
The magnitude relationship between the first and third threshold values Vth1 and Vth3 is opposite to the magnitude relationship between the second and fourth threshold values Vth2 and Vth4, and the second threshold value and the 3 is characterized in that the threshold values are different.
[0038]
Further, according to one aspect of the present invention, a nonvolatile memory unit including a plurality of nonvolatile memory cells, a first selection MOS transistor for making the nonvolatile memory unit conductive with a bit line, a nonvolatile memory unit and a source In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a line are arranged in a matrix, the first selection MOS transistor has a first threshold value. A first memory cell unit having Vth1 and a second selection MOS transistor having a second threshold value Vth2; and a first selection MOS transistor having a third threshold value Vth3 and a second selection MOS transistor. The second memory cell unit whose transistor has the fourth threshold value Vth4 is the same as that of the first selection MOS transistor. A gate array and a gate electrode of the second selection MOS transistor are shared as first and second selection gates, respectively, to form a sub-array, and the magnitude relationship between the first and third thresholds Vth1 and Vth3 and the second And the magnitude relationship between the fourth threshold values Vth2 and Vth4 is opposite to that of the first and second memory cell units in the sub-array, and is stored in the nonvolatile memory unit in one of the memory cell units. A timing unit for page-reading the data stored in the non-volatile memory section in the other memory cell unit while randomly reading the stored data.
[0039]
Here, preferred embodiments of the present invention include the following.
[0040]
(1) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.
[0041]
(2) The first memory cell units and the second memory cell units are alternately arranged to form a sub-array.
[0042]
(3) When reading the nonvolatile memory section of the first memory cell unit, both the first and second selection MOS transistors of the first memory cell unit are turned on, and the first memory cell unit of the second memory cell unit is turned on. When one of the first and second selection MOS transistors of the first memory cell unit is turned off when one of the first and second selection MOS transistors is turned off and the nonvolatile memory section of the second memory cell unit is read out. A read select gate voltage is applied to the first and second select MOS transistors in the selected sub-array so that the first and second select MOS transistors in the selected sub-array are turned on and both the first and second select MOS transistors of the second memory cell unit are turned on. Is provided.
[0043]
(4) In (3), when data stored in the non-volatile memory portion in one of the first memory cell unit and the second memory cell unit in the sub-array is read out to the bit line And keeping the bit line connected to the other memory cell unit at the non-selected read bit line potential.
[0044]
(5) In (4), using the unselected read bit line potential as a reference potential, the first bit line potential connected to the first memory cell unit at the time of reading and the second memory cell unit are connected. Bit line voltage detection means for differentially detecting a potential difference between the second bit line potential and the second bit line potential is provided.
[0045]
(6) The nonvolatile memory section is composed of a plurality of electrically rewritable nonvolatile memory cells.
[0046]
(7) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of non-volatile memory cells are connected in series so that adjacent ones share a source and a drain. Construct a non-volatile memory unit.
[0047]
(8) A non-volatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or a plurality of non-volatile memory cells are connected in parallel so as to share a source and a drain. Construct a non-volatile memory unit.
[0048]
(9) Selecting the first, second, third and fourth threshold values by controlling the impurity concentration of the channel of the nonvolatile memory cell.
[0049]
(10) The first and second select MOS transistors are configured by stacking a charge storage layer and a select gate on a semiconductor layer.
[0050]
(11) The first selection MOS transistor and the second selection MOS transistor have different gate lengths.
[0051]
(12) When performing a write operation to the nonvolatile memory portion in one of the first memory cell unit and the second memory cell unit in the sub-array and a verify operation to check whether the write operation is sufficient or not. Alternatively, the bit line connected to the other memory cell unit is kept at a constant potential through write, write verify, rewrite, and write verify operations.
[0052]
(13) The memory cell array is composed of a first sub-memory cell array and a second sub-memory cell array, and each of these sub-memory cell arrays is composed of first and second memory cell units, respectively. The voltage applied to the gate of the first select MOS transistor is applied to the gate of the second MOS transistor of the second sub memory cell array, and the voltage applied to the gate of the second MOS transistor of the first sub memory cell array is Applying the voltage to the gate of the first MOS transistor of the second sub memory cell array;
[0053]
Further, according to one aspect of the present invention, a nonvolatile memory unit including a plurality of nonvolatile memory cells, a first selection MOS transistor for conducting the nonvolatile memory unit to a first common signal line, In a nonvolatile semiconductor memory device having a memory cell array in which a memory cell unit composed of a volatile memory unit and a second selection MOS transistor for conducting a second common signal line is arranged in a matrix, While reading or writing to a memory cell connected to one or more bit lines, among the remaining bit lines in the memory cell array, in a bit line group composed of a plurality of bit lines, It is characterized by having means for connecting / disconnecting between bit lines.
[0054]
Here, preferred embodiments of the present invention include the following.
[0055]
(1) The means for connecting and disconnecting between bit lines is a MOS transistor provided between bit lines.
[0056]
(2) The bit line group is composed of bit line pairs connected to the same sense amplifier circuit.
[0057]
(3) A plurality of bit lines are connected to the same sense amplifier circuit, and the sense amplifier circuit constitutes an open bit line type memory cell array provided between bit lines connected to the circuit.
[0058]
(4) In a memory cell array of the open bit line system, a first bit line pair and a second bit line pair form a shared sense amplifier system in which a sense amplifier is shared, and a memory cell connected to the first bit line pair is provided. Means for connecting between bit lines constituting a second bit line pair when reading or writing is performed.
[0059]
(5) The memory cell array includes a nonvolatile memory unit including one or a plurality of nonvolatile memory cells, a first selection MOS transistor for making the nonvolatile memory unit conductive with a first common signal line, A memory cell unit in which a nonvolatile memory section and a second common signal line are made conductive and a first selection MOS transistor and a second selection MOS transistor having a different threshold value are arranged in a matrix. It is.
[0060]
(6) a first memory cell unit having a first selection MOS transistor having a first threshold value Vth1 and a second selection MOS transistor having a second threshold value Vth2, and a first selection MOS transistor Have a third threshold value Vth3, the second selection MOS transistor has a fourth threshold value Vth4, and the second memory cell unit has a gate electrode of the first selection MOS transistor and a second selection MOS transistor. The sub-array is formed by sharing the gate electrodes of the MOS transistors as first and second selection gates, respectively, and the magnitude relationship between the first and third thresholds Vth1 and Vth3 and the second and fourth thresholds Vth2 , Vth4 have the opposite relationship.
[0061]
(7) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.
[0062]
(8) The first memory cell units and the second memory cell units are alternately arranged to form a sub-array.
[0063]
(9) In (4), in the subarray, the first memory cell unit is connected to the first bit line pair, and the second memory cell unit is connected to the second bit line pair.
[0064]
[Action]
According to the present invention, a conductive state and a non-conductive state can be generated among the select MOS transistors sharing one select gate, and by providing two such select gates, the same select gate can be obtained. A memory cell in a selected state and a memory cell in a non-selected state can be easily realized in a memory cell having a gate. Specifically, by changing the threshold values of the select gate on the source side and the select gate on the drain side, and changing the threshold value of the select gate in the adjacent memory cell, for example, the memory connected to the even-numbered bit line is changed. When reading a cell to a bit line, a memory cell connected to an odd-numbered bit line can be deselected. As a result, a folded bit line method can be realized without increasing the chip area, and high-speed random read can be performed.
[0065]
Also, according to the present invention, while one of the first memory cell unit and the second memory cell unit is read randomly while the other is page-read, the word line can be switched without increasing the chip area. It is possible to perform a high-speed page read operation without wasting time that occurs. Further, according to the present invention, since the precharge associated with the bit line shield or the like can be omitted, a problem that occurs when the bit line shield is applied to the open bit line method and the single-ended method using the conventional cell array, that is, An increase in power consumption when reading and writing data over a plurality of pages and an increase in reading and writing time can be reduced.
[0066]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0067]
(Example 1)
Hereinafter, an embodiment that solves (Problem 1) will be described.
[0068]
FIG. 1 is a block diagram showing an entire configuration of a NAND cell type EEPROM according to a first embodiment of the present invention. In the figure, 1 is a memory cell array, 2 is a sense amplifier and latch circuit as latch means for writing and reading data, 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, and 5 is a column decoder. An address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0069]
FIG. 2 is a diagram showing the configuration of a memory cell array, where BL and / BL are bit lines, WL is a word line, STD is a first selection MOS transistor connected to the drain side of a NAND cell, and STS is the source side of a NAND cell. SGD is a select gate for driving the select MOS transistor STD, SGS is a select gate for driving the select MOS transistor STS, SA is a sense amplifier, and TG is a sense amplifier SA and a bit line. A control signal for driving a gate for connecting BL is shown.
[0070]
As shown in FIG. 2, the sense amplifier SA receives an adjacent pair of bit lines BLj and / BLj as inputs. This is a folded bit line system used in DRAM. In order to realize the folded bit line system, it is necessary to prevent one bit line of a bit line pair from discharging when the other bit line is discharged. A difference is provided between the threshold values of the selection MOS transistors (for example, STS00 and STS10, STD00 and STD10 in FIG. 2) sharing the same selection gate, and different voltages are applied to the drain-side selection gate and the source-side selection gate. To achieve this.
[0071]
In FIG. 2, a select MOS transistor having a high threshold value Vt1 (eg, 2 V) is referred to as E-type, and a select MOS transistor having a low threshold value Vt2 (eg, 0.5 V) (Vt1> Vt2) is referred to as I-type. ing. The voltages applied to the gates (selection gates) of the two types of selection MOS transistors include a voltage Vsgh (for example, 3 V) that turns on both the I-type transistor and the E-type transistor (Vsgh> Vt1, Vt2), and an I-type transistor. Is turned on but the E-type transistor is turned off at a voltage Vsgl (for example, 1.5 V) (Vt1>Vsgl> Vt2).
[0072]
Here, the memory cell is an electrically rewritable nonvolatile memory cell in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate. Memory section). The I-type STS and the E-type STD are connected to the NAND cell to form a first memory cell unit. The E-type STS and the I-type STD are connected to the NAND cell to form the second memory cell unit. Of memory cell units, and the first and second memory cell units are alternately arranged. Further, a sub-array is constituted by a plurality of first and second memory cell units sharing a word line.
[0073]
With reference to FIG. 2, a method for applying a voltage to the selection gate will be specifically described. For example, when reading data from the memory cell MC000, the word lines WL00 and WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source-side select gate SGS0 is set to Vsgh, and the drain-side select gate SGD0 is set to Vsgl. SGS1 and SGD1 are set to 0V. In this case, the source-side selection MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off. Therefore, if the data of the memory cell MC000 is "1", the bit line BL0 is turned off. The bit line / BL0 does not discharge regardless of the data in the memory cell MC100.
[0074]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source-side select gate SGS0 is set to Vsgl, and the drain-side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, the drain-side selection MOS transistors STD00 and STD10 are both turned on. The source side select MOS transistor STS10 is turned on, so that the bit line / BL0 is discharged if the data of the memory cell MC100 is "1", but the select MOS transistor STS00 is turned off, so that the bit line BL0 is not discharged.
[0075]
The present invention is a selection MOS transistor connected to a bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 of FIG. 2). What is necessary is just to give a difference to the threshold value of STS11), and the way of setting the threshold value is arbitrary. For example, as shown in FIG. 3, the selection MOS transistor STD00 of the bit line BLj may be E-type, the STS00 may be I-type, the selection MOS transistor STD10 of the bit line / BLj may be I-type, and the STS10 may be E-type.
[0076]
In FIG. 2, the drain-side select MOS transistors of the cells connected to the bit line BLj are all I-type, and the source-side select MOS transistors are E-type. However, as shown in FIG. 4, for example, the bit line contacts are shared. In the two NAND blocks, one of the drain-side selection MOS transistors may be I-type and the other may be E-type. 2 to 4, alternately disposed bit lines BLj are simultaneously selected and read. For example, as shown in FIG. 5, the threshold value of the selection MOS transistor is set to select bit line BL0 as shown in FIG. In this case, the bit line / BL1 may be selected.
[0077]
In the present invention, not only this (Embodiment 1) but also all the embodiments up to (Embodiment 5) which will be described later, among the selection MOS transistors sharing one selection gate, the selection MOS transistors having a conduction state and the non-selection MOS transistors sharing a non-selection gate have a non-selection state. A conductive state can be generated, and by providing two such select gates, a memory cell in a selected state and a memory cell in a non-selected state can be easily selected from memory cells having the same select gate. I use what I can do.
[0078]
Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate have arbitrary characteristics. The drain-side select MOS transistor has two threshold values of Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to the drain-side select gate is Vsghd (Vsghd> Vtd1) and Vsgld (Vtd1>Vsgld> Vtd2). The source-side selection MOS transistor has two thresholds of Vts1 and Vts2 (Vts1> Vts2), and the voltages applied to the source-side selection gate are Vsghs (Vsghs> Vts1) and Vsgls ( Vts1>Vsgls> Vts2), and may not be Vtd1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, Vsgld = Vsgls as in the above embodiment.
[0079]
For example, the threshold voltage of the drain-side select MOS transistor is set to two types of 2 V and 0.5 V, and the threshold value of the source-side select MOS transistor is set to two types of 2.5 V and 1 V. The voltage applied may be Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the source side select gate may be Vsgh = 3V, Vsgl = 1.2V.
[0080]
If Vsgh is made larger than Vcc, the conductance of the select MOS transistor will increase (that is, the resistance will decrease), and the cell current flowing through the NAND cell row at the time of reading will increase. As a result, the bit line discharge time will be shortened. , Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0081]
The selection MOS transistors sharing one selection gate are all turned on. The voltage Vsgh of the selection gate is desirably equal to or lower than the power supply voltage Vcc. When Vsgh is larger than Vcc, a booster circuit is required in the chip, which leads to an increase in chip area.
[0082]
Further, the smaller threshold value Vt2 of the selection MOS transistor may be a negative threshold value (for example, -1 V). At the time of writing, 0 V is applied to the bit line connected to the cell to be written, and an intermediate potential (about 10 V) is applied to the bit line connected to the cell not to be written. The source-side select gate must be turned off so that no current flows. Therefore, when Vt2 is set to a negative threshold value of about -1 V, a negative voltage (for example, -1.5 V) that turns off the negative-threshold selection gate is applied to the source-side selection gate during writing. Just fine.
[0083]
The larger value Vt1 of the threshold values of the selection gates may be set to a voltage equal to or higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using a booster circuit inside the chip.
[0084]
Here, the operation when reading out the memory cell MC000 connected to the bit line BLj in FIG. 6 will be described with reference to the timing chart in FIG. The sense amplifier is formed by a CMOS flip-flop controlled by control signals SAN and SAP.
[0085]
First, the control signal TG changes from Vcc (for example, 3 V) to Vss, and the CMOS flip-flop FF is disconnected from the bit lines BLj and / BLj. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BLj is precharged to VA (eg, 1.7 V), and the bit line / BLj is precharged to VB (eg, 1.5 V) ( Time t1). When the precharge ends, φpA and φpB become Vss, and the bit lines BLj and / BLj enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the selection gate (time t2).
[0086]
When reading the memory cell MC000 in FIG. 6, WL00 is 0 V, WL01 to WL07 are 3 V, SGD0 is 3 V (Vsgh), and SGS0 is 1.5 V (Vsgl). When the data written in the memory cell MC000 is “0”, the cell current does not flow because the threshold value of the memory cell MC000 is positive, and the potential of the bit line BLj remains at 1.7 V. When the data is “1”, the cell current flows and the potential of the bit line BLj decreases to 1.5 V or less. Further, since the selection gate SGS0 is at 1.5 V, the selection transistor STS10 is turned off, and the bit line / BLj is not discharged regardless of the data written in the memory cell MC100, and is maintained at the precharge potential of 1.5 V. .
[0087]
Then, at time t3, SAP becomes 3 V and SAN becomes 0 V, the CMOS flip-flop FF is inactivated, and φE becomes 3 V at time t4, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / V. 2 (for example, 1.5 V). After TG becomes 3V at time t5 and the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BLj and / BLj is amplified. Thereafter, at time t7, the SAP changes from 3V to 0V, and the data is latched.
[0088]
That is, if “0” is written in the memory cell MC000, the node N1 becomes 3V and the node N2 becomes 0V. If "1" is written in MC000, the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSLj changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t8).
[0089]
Next, FIG. 10 shows a timing chart when the memory cell MC100 connected to the bit line / BLj in FIG. 6 is read. In this case, the bit line BLj is precharged to 1.5 V and the bit line / BLj is precharged to 1.7 V (time t1). The voltage applied to the control gate (word line) from the row decoder 3 when reading the cell data to the bit line is the same as that for reading the memory cell MC000, except that the voltage applied to the selection gate is 1.5 V for SGD0 and SGS0. Is 3V (time t2).
[0090]
When the data written in the memory cell MC100 is "0", the cell current does not flow because the threshold value of the memory cell MC100 is positive, and the potential of the bit line / BLj remains at 1.7V. When the data is "1", the cell current flows and the potential of the bit line / BLj decreases to 1.5 V or less. Further, since the selection gate SGD0 is 1.5V, the selection MOS transistor STD00 is turned off, and the bit line BLj is not discharged regardless of the data written in the memory cell MC000, and is maintained at the precharge potential 1.5V. . After that, the data read to the bit line / BLj is sensed and latched by the sense amplifier in the same manner as when reading the memory cell MC000, and is output to I / O and I / O '.
[0091]
The timing of the read operation is arbitrary. For example, at time t5, as shown in FIG. 9, the transfer gate connecting the bit line and the sense amplifier is turned on to transfer the potentials of the bit lines BLj and / BLj to the nodes N1 and N2, and then the transfer gate is turned off. . Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined during sensing and data latching.
[0092]
In the timing charts of FIGS. 8 to 10, during the sensing operation of the sense amplifier, first, SAN is set from 0 V to 3 V to turn on the N-channel transistor of the CMOS flip-flop FF, and then SAP is set from 3 V to 0 V, and then the CMOS flip-flop FF is turned on. Are turned on, but SAP may be changed from 3V to 0V almost simultaneously with changing SAN from 0V to 3V.
[0093]
When the data of the cell connected to the bit line BLj is sensed and latched by the sense amplifier, one of the potentials of the bit lines BLj and / BLj is 0 V and the other is Vcc (for example, 3 V). After the cell data of the bit line BLj is output from the sense amplifier to I / O, I / O ', if .phi.E is set to 3 V, the bit lines BLj and / BLj are connected (equalized), and the bit line BLj is not precharged. , / BLj become 1.5V. Thereafter, for example, when reading out the bit line / BLj, the bit line / BLj may be precharged to 1.7 V by setting φPB to 3 V and VB to 1.7 V. By connecting the bit lines BLj and / BLj after sensing the bit line BLj in this manner, the precharge time for the next read can be shortened and the power consumption required for the precharge can be reduced.
[0094]
As shown in FIG. 7, a circuit for performing verification after writing to the sense amplifier may be added.
[0095]
As a method of precharging a different potential to the bit line pair, a dummy cell may be provided as shown in FIG. 11, for example, in addition to the method of transferring the potentials VA and VB from the peripheral circuit as shown in FIG. In this case, the bit lines BLj and / BLj are precharged to the same potential VPR. The current flowing in the dummy cell is smaller than the worst read current of the cell. For example, a dummy NAND type cell connected in series may be a depletion type transistor, the channel length L may be increased, and the channel width W may be reduced.
[0096]
If the threshold value of the dummy selection MOS transistor is set as shown in FIG. 11, when data of a memory cell connected to bit line BLj is read to bit line BLj, bit line / BLj is discharged through the dummy cell and bit line / BLj is discharged. When reading data from the memory cell connected to / BLj, the bit line BLj is discharged through the dummy cell.
[0097]
The operation of this embodiment will be described by taking a case where the memory cell MC000 is read as an example. First, the precharge control signal PRE becomes 3 V, and the bit lines BLj and / BLj are precharged to a precharge potential VPR (for example, 1.7 V). Thereafter, the control gate line and the selection gate of the memory cell are selected, 0V is applied to the dummy word line DWL, and substantially the same voltage as the voltage applied to the selection gates SGS and SGD of the selection MOS transistor is applied to the dummy selection gates DSGS and DSGD. Is done.
[0098]
If "0" is written in the memory cell MC000, the bit line BLj does not discharge and keeps the precharge potential of 1.7 V. If "1" is written in MC000, the bit line BLj is discharged to, for example, 1.3V. When the bit line BLj in which "1" is written is discharged to 1.3 V, the bit line / BLj may be discharged to 1.5 V through the dummy cell. Thereafter, the operation of differentially amplifying the potential of the bit line pair by the sense amplifier is the same as in the embodiment of FIG.
[0099]
As a method of precharging a different potential to the bit line pair, the dummy cell may be constituted by one transistor and one capacitor as shown in FIG. First, the bit line precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to the same potential VPR. When the data of the memory cell MC000 is read out to the bit line BLj after the control signal PRE becomes 0V and the bit line is in a floating state, φPB becomes 3V and the capacitor C1 is charged. The bit line / BLj drops from the precharge potential VPR by the charge charged in the capacitor C1. This may be used as a reference potential for differentially amplifying the bit line pair.
[0100]
When reading data from the memory cell MC100 to the bit line / BLj, the capacitor C0 is charged when φPA becomes 3 V, and the bit line BLj falls from the precharge potential VPR. This bit line BLj may be set to the reference potential.
[0101]
In the embodiments of FIGS. 6 to 10, while discharging the bit line to which the memory cell to be read is connected, the other bit line (for example, the memory of FIG. 6) of the bit line pair connected to the sense amplifier is discharged. When reading the cell MC000, the bit line / BLj is in a floating state, and when reading the memory cell MC100, the bit line BLj) is in a floating state. However, while the bit line (for example, the bit line BLj) is precharged to 1.7 V and the data of the memory cell is thereafter read, the precharge control signal φPB is kept at 3 V, so that the reference bit line (for example, the bit line BLj) becomes The bit line / BLj) can be fixed at a reference potential of 1.5V.
[0102]
By maintaining the bit line / BLj at the reference potential in this manner, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. As in the case of the above-mentioned read, during the verify read after the write (described in detail in the fourth embodiment), the bit line is charged and discharged according to the data written in the cell, but the bit line / BLj which is not read is set to the reference potential. , Noise due to capacitive coupling between bit lines can be reduced.
[0103]
In order to reduce noise due to capacitive coupling between adjacent bit lines when sensing and latching data of a memory cell read to a bit line, a twisted bit line method proposed in a DRAM as shown in FIG. It may be. A twisted bit line system as shown in FIG. 14 may be used.
[0104]
The selection MOS transistor may be constituted by a cell having a selection gate and a floating gate as shown in FIG. In the case of this embodiment, the threshold value of the selection MOS transistor can be determined by injecting electrons into the floating gate of the selection MOS transistor before shipping the semiconductor memory device. The injection of electrons into the floating gate of the drain-side select MOS transistor (eg, STD00 in FIG. 15) may be performed by tunneling from the substrate.
[0105]
That is, the word lines WL00 to WL07 are at an intermediate potential (about 10V) or 0V, the selection gate SGD0 is at Vpp (about 20V), the selection gate SGD0 is at 0V, the bit line BL0 is at 0V, and the bit lines / BL0, BL1, and / BL1 are at an intermediate potential. The potential (about 10 V) may be set. Further, in order to determine the threshold value of the source-side selection MOS transistor, the selection gates SGD0, SGS0 and the word lines WL00 to WL07 are all set to "H" to turn on all the NAND cell columns, and Vpp or Vpp is applied to the bit line BL0. Hot electrons may be injected by applying 0 V to the intermediate potential and the bit lines / BL0, BL1, and / BL1.
[0106]
As described above, according to the present invention, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line method can be realized without increasing the chip area, and high-speed random read can be performed. Will be possible. As a method of changing the threshold value, changing the gate oxide film thickness of the selection MOS transistor, changing the concentration of the channel-doped impurity in the selection MOS transistor, and the like can be considered. Alternatively, the threshold value may be different depending on whether or not the select MOS transistor is channel-doped with impurities. The threshold value can also be changed by changing the channel length of the selection MOS transistor. That is, since the threshold value of a transistor having a short channel length is reduced due to the short channel effect, the transistor may be used as an I-type transistor.
[0107]
As a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of a peripheral circuit may be used without introducing a new manufacturing process. In any case, the threshold value of the selection MOS transistor may be made different, and if the threshold value is made different, a predetermined threshold value can be obtained by a substrate bias or the like.
[0108]
In the conventional NAND cell type EEPROM, 0 V is applied to the select gate on the source side of the write block. However, when the select MOS transistor on the source side is I-type and the threshold value Vt2 is about 0.1 V (or negative). In the case of a threshold value, the source-side select MOS transistor does not completely cut off, the cell current flows for example 0.1 μA, and the unwritten bit line is discharged from the intermediate potential (about 10 V).
[0109]
For example, if the bit lines are charged to an intermediate potential without writing to the memory cells connected to the 200 bit lines, the cell current will flow in total of 200 × 0.1 μA = 20 μA. In order to improve the cut-off characteristics of the I-type transistor, a voltage of, for example, about 0.5 V may be applied to the common source line at the time of writing. When 0.5 V is applied to the source, the potential difference between the source and the substrate becomes -0.5 V, and the threshold value of the I-type transistor increases due to the body bias effect. Therefore, 0 V is applied to the gate of the I-type transistor. The cut-off characteristic at the time of reading is improved, and the cell current at the time of reading can be reduced.
[0110]
In order to set the smaller one (I-type) of the thresholds of the selection gates to, for example, 0.5 V, a method of reducing the substrate concentration may be considered. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate expands, and as a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are reduced. However, there is a problem in that the connection and the dullness (punch through) occur. In order to increase the punch-through breakdown voltage of the I-type select MOS transistor, the channel length L of the I-type select MOS transistor may be increased.
[0111]
In the above embodiment, the NAND cell type EEPROM has been described. However, the nonvolatile semiconductor memory in which the drain side of the memory cell is connected to the bit line via the selection gate, and the source side of the memory cell is also connected to the source line via the selection gate. The present invention is effective for a device. For example, the present invention is also effective in an AND cell type EEPROM (H. Kume el al .; IEDM Tech. Dig., Dec. 1992, pp. 991-993) as shown in FIG. A NOR type EEPROM or a mask ROM having one memory cell between the gate and the source side select gate is also effective.
[0112]
(Example 2)
Hereinafter, an embodiment that solves (Problem 2) will be described.
[0113]
FIG. 17 is a block diagram showing a configuration of a NAND cell type EEPROM according to the present embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means, and the memory cell is divided into 1A and 1B because of the open bit line system. The memory cell arrays 1A and 1B are each divided into at least two predetermined units.
[0114]
In the present embodiment, it is assumed that one page has 256 bits, and the memory cell arrays 1A and 1B are divided into 1A1, 1A2 and 1B1, 1B2 in units of 128 bits. Reference numeral 2 denotes a sense amplifier circuit as latch means for writing and reading data, and is divided into at least two for each predetermined unit, similarly to the memory cell arrays 1A and 1B. In FIG. 17, the sense amplifier is divided into 2A and 2B. Reference numeral 3 denotes a row decoder for selecting a word line, 4 denotes a column decoder for selecting a bit line, 5 denotes an address buffer, 6 denotes an I / O sense amplifier, 7 denotes a data input / output buffer, and 8 denotes a substrate potential control circuit.
[0115]
The memory cell array 1A1 is shown in FIGS. 18 and 1B1, FIGS. 19 and 1A2 are shown in FIGS. 18 to 21, the threshold values of the selection MOS transistors in the memory cell array have two kinds of values as in the above (Embodiment 1). It is assumed that the threshold value of the selection MOS transistor denoted by E-type is 2 V, and the threshold value of the selection MOS transistor denoted by I-type is 0.5 V. Therefore, when both the E-type select MOS transistor and the I-type select MOS transistor are turned on, Vcc (for example, 3 V) is applied to the select gate, and when only the I-type is turned on, 1.V. 5 V is applied.
[0116]
When reading data from the memory cell array 1A1 to the bit lines BL0A to BL127A, the drain-side select gate SGD is set at 3V, and the source-side select gate SGS is set at 1.5V. On the other hand, when data of the memory cell array 1A2 is read to the bit lines BL128A to BL255A, the selection gate SGD on the drain side is set to 1.5V and the selection gate SGS on the source side is set to 3V. When simultaneously reading data from the memory cell arrays 1A1 and 1A2, both SGS and SGD may be set to 3V.
[0117]
The sense amplifier is a differential sense amplifier as in the folded bit line system of the first embodiment. FIG. 22 shows the sense amplifier 2A (SA1) connected to the memory cell arrays 1A1 and 1B1, and FIG. 23 shows the sense amplifier 2B (SA2) connected to the memory cell arrays 1A2 and 1B2.
[0118]
Here, taking the case of reading data written in two pages as an example, the read operation of the present embodiment will be described with reference to the timing charts of FIGS. First, on the first page, the sense amplifiers 2A (SA1) and 2B (SA2) operate simultaneously. The control signals TG1, TG2 change from 3V to 0V, and the CMOS flip-flops FF1, FF2 are disconnected from the bit lines BLjA, BLjB (j = 0, 1,..., 255).
[0119]
Next, the precharge signals φpA1, φpB1, φpA2, and φpB2 change from 0 V to 3 V, the bit line BLjA (j = 0, 1,..., 255) becomes 1.7 V, for example, and the bit line BLjB (j = 0, 1). ,..., 255) are precharged to, for example, 1.5V. When the precharge is completed, φpA1, φpB1, φpA2, and φpB2 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 255) enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate.
[0120]
18 and 19, WL00 is 0V, WL01 to WL07 are 3V, SGD0 is 3V, and SGS0 is 3V. When the data written to the memory cell selected by the word line WL00 is "0", the threshold value of the memory cell is positive, so that no cell current flows and the potential of the bit line BLjA remains at 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLjA decreases to 1.5 V or less. Further, the bit line BLjB is not discharged, and is kept at the precharge potential 1.5V.
[0121]
Thereafter, SAP1 and SAP2 become 3V, SAN1 and SAN2 become 0V, CMOS flip-flops FF1 and FF2 are inactivated, and φE1 and φE2 become 3V, thereby resetting CMOS flip-flops FF1 and FF2. After TG1 and TG2 become 3V and the bit lines and the sense amplifier are connected, SAN1 and SAN2 become 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 255) is amplified. You. Thereafter, SAP1 and SAN2 change from 0V to 3V, and the data is latched. Then, column selection signals CSLj (j = 0, 1,..., 255) are successively selected, and the data latched by the CMOS flip-flop is output to I / O, I / O ′ (page read).
[0122]
After the page read of the first half data (column addresses 0 to 127) of the first page, while the page read of the second half data of the first page, the first half data (bit line BLjA; j) of the row address of the second page = 0, 1,..., 127. This may be performed, for example, by detecting that the column address is 128.
[0123]
First, the precharge signals φpA1, φpB1, φpA2, and φpB2 change from 0V to 3V, the bit line BLjA (j = 0, 1,..., 127) becomes 1.7V and the bit lines BLjB (j = 0, 1,. 127) is precharged to 1.5V. When the precharge is completed, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 becomes 0V, WL00, WL02 to WL07 become 3V, SGD0 becomes 3V, and SGS0 becomes 1.5V.
[0124]
When the data written in the memory cell selected by the word line WL01 is "0", the cell current does not flow because the memory cell threshold is positive, and the bit line BLjA (j = 0, 1,..., 127) Remains at 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLjA (j = 0, 1,..., 127) drops to 1.5 V or less. The bit line BLjB (j = 0, 1,..., 127) is not discharged, and the precharge potential 1.5 V is maintained.
[0125]
Thereafter, SAP1 becomes 3V, SAN1 becomes 0V, the CMOS flip-flop FF1 is inactivated, and φE1 becomes 3V, thereby equalizing the CMOS flip-flop FF1. After TG1 becomes 3V and the bit line is connected to the sense amplifier, SAN1 becomes 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 127) is amplified. Thereafter, SAP1 and SAN2 change from 0V to 3V, and the data is latched by the sense amplifier 2A (SA1).
[0126]
At the point where the page read of the first page has advanced by 256 column addresses, the data of the next 128 pages of the second page has already been latched by the sense amplifier 2A (SA1), so there is no need to perform the random read operation. . During the page read from the sense amplifier 2A (SA1) to the second page column addresses 0 to 127, a random read operation is performed on the second half column addresses 128 to 255 of the second page. That is, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0 V, WL00 and WL02 to WL07 are 3 V, SGD0 is 1.5 V, and SGS0 is 3 V.
[0127]
When the data written in the memory cell selected by the word line WL01 is "0", the cell current does not flow because the memory cell threshold is positive, and the potential of the bit line BLjA remains at 1.7 V. When the data is "1", a cell current flows and the potential of the bit line BLjA (j = 128, 129,..., 255) drops to 1.5 V or less.
[0128]
Further, the bit line BLjB (j = 128, 129,..., 255) is not discharged, and is kept at the precharge potential 1.5V. Then, SAP2 becomes 3V, SAN2 becomes 0V, the CMOS flip-flop FF2 is inactivated, and φE2 becomes 3V, whereby the CMOS flip-flop FF2 is reset. Then, after TG2 becomes 3V and the bit line is connected to the sense amplifier, SAN2 becomes 0V to 3V and the potential difference between the bit lines BLjA and BLjB (j = 128, 129,..., 255) is amplified. Thereafter, SAP2 changes from 3V to 0V, and the data is latched by the sense amplifier 2B (SA2).
[0129]
When the page read of the second page has advanced by 128 column addresses, since the data of the second half 128 column addresses of the next second page has already been latched by the sense amplifier 2B (SA2), a random read operation is performed. It is possible to serially read the data of the second half column address of 128 columns without need.
[0130]
The present invention is not limited to the above embodiment. In the above embodiment, the memory cell is divided into two, but may be divided into, for example, four or an arbitrary number.
[0131]
The timing charts of FIGS. 24 and 25 are merely examples. In the timing charts of FIGS. 24 and 25, the data of the first page is read by the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) at the same time. However, as shown in the timing charts of FIGS. First, a random read of the memory cell corresponding to the first half column address of the first page is performed, and then the second half of the first page data is randomly read while the first half of the first page data is read. Good.
[0132]
Further, in FIGS. 24 and 25, bit lines are precharged simultaneously by random reading of the first half data of the second page and random reading of the second half data of the second page, but as shown in FIGS. The timing of precharging the bit lines may be changed between the case of random reading with 2A (SA1) and the case of random reading with sense amplifier 2B (SA2).
[0133]
Further, the division of the memory cell array need not be a physically continuous one as one division unit. For example, as shown in FIGS. 28 and 29, the bit lines connected to the sense amplifier SA1 and the bit lines connected to the sense amplifier SA2 may be arranged alternately. While the bit line connected to the sense amplifier SA1 is randomly read, the bit line connected to the sense amplifier SA2 can be grounded to 0 V. In this case, the distance between the bit lines connected to the sense amplifier SA1 is shown in FIGS. In the case of random read, noise can be reduced due to capacitive coupling between bit lines during random read.
[0134]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. In FIG. 31, the memory cell array connected to the bit line BLj (j = 0, 1,..., 255) may be the same as the memory cell array connected to the bit line BLjA (j = 0, 1,. Good.
[0135]
(Example 3)
Hereinafter, an embodiment that solves (Problem 3) will be described.
[0136]
In the conventional memory cell array, when a word line which is the row decoder 3 is selected at the time of reading and writing, all the memory cells disposed at the intersection of the selected word line and the bit line are selected. Therefore, one of the memory cells connected to the adjacent bit line cannot be selected and the other cannot be deselected.
[0137]
As described in the above (Embodiment 1) and (Embodiment 2), according to the present invention, the threshold values of the source side select MOS transistor and the drain side select MOS transistor of the NAND block are changed, By changing the voltage applied to the side select gate and the drain side select gate, one of the adjacent bit lines can be selected and the other bit line can be deselected. As a result, it is possible to shorten the precharge time and reduce power consumption by omitting the precharge to the bit line at the time of reading and writing.
[0138]
Therefore, in the present embodiment (Embodiment 3), an embodiment will be described in which the precharge time is shortened at the time of reading to reduce power consumption. An example in which the precharge time is shortened at the time of writing to reduce power consumption will be described in the next embodiment (Embodiment 4).
[0139]
FIG. 32 is a block diagram showing a configuration of a NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means, which is divided into two parts 1A and 1B by an open bit line system. In this embodiment, one page has 256 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch unit for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0140]
The memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) of FIG. 28 provided in the memory cell arrays 1A and 1B is not FIG. 22 but FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA and BLjB (j = 128, 129,..., 255) of FIG. 29 provided in the memory cell arrays 1A and 1B is not FIG. 23 but FIG. In the sense amplifiers SA1 and SA2 in FIGS. 33 and 34, a transistor for equalizing (making the same potential) between the bit lines BLjA and BLjB by the control signals φEQ1 and φEQ2 is added to the sense amplifiers SA1 and SA2 in FIGS. Have been.
[0141]
At the time of reading, every other bit line is kept at a reference potential in order to reduce noise due to capacitive coupling between bit lines (bit line shield). In this case, the write operation is first performed on, for example, a cell connected to the bit line BLjA (j = 0, 1,..., 127), and then connected to the bit line BLjA (j = 128, 129,..., 255). Write to the cell to be written. Here, the data (the first page data) written to the bit line BLjA (j = 0, 1,..., 127) is first read, and then the data is written to the bit line BLjA (j = 128, 129,. This embodiment will be described by taking as an example a case where written data (data of the second page) is read.
[0142]
When reading the data of the bit line BLjA (j = 0, 1,..., 127), the shielded bit line BLjA (j = 128, 129,..., 255) is kept at the reference potential (for example, 1.5 V). In the conventional memory cell array, adjacent bit lines are simultaneously selected and discharged, so that only 0 V can be applied to the shielded bit lines. The timing chart of FIG. 35 is divided into a case where the data of the first page is read to the bit line, a case where the data read to the bit line is sensed by the sense amplifier, and a case where the data of the second page is read to the bit line. This will be described with reference to FIG.
[0143]
<When reading data of the first page to the bit line>
When reading out a memory cell selected by the word line WL00 in the memory cell array of FIG. 28 and connected to the bit line BLjA (j = 0, 1,..., 127), first, the bit line BLjA (j = 0, 1,. , 127) to 1.7 V and the bit line BLjB (j = 128, 129,..., 255) to 1.5 V to shield the bit lines BLjA, BLjB (j = 128, 129,..., 255). Is precharged to a reference potential (for example, 1.5 V).
[0144]
After the bit line precharge, the control gate WL00 is set to 0V, the WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and the SGD0 is set to 3V. In this case, the selection MOS transistor on the source side of bit line BLjA (j = 0, 1,..., 127) turns on, but the selection MOS transistor on the source side of bit line BLjA (j = 128, 129,..., 255) Turns off. Therefore, the bit line BLjA (j = 0, 1,..., 127) is discharged if the data of the memory cell selected by the word line WL00 is “1”, but the bit line BLjA (j = 128, 129,. 255) does not discharge.
[0145]
When the bit line BLjA (j = 0, 1,..., 127) discharges, the potential of the bit line BLjA (j = 128, 129,..., 255) drops from the reference potential due to capacitive coupling between bit lines. While the line BLjA (j = 0, 1,..., 127) is discharging, for example, VA2 and VB2 are set to the reference potential of 1.5 V, and the control signals φPA2 and φPB2 are set to 3 V, so that the bit lines BLjA and BLjB ( .., 255) can be maintained at the reference potential at the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255).
[0146]
After the cell data is read to the bit line BLjA (j = 0, 1,..., 127), the control signals φPA2, φPB2 become 0 V, and the bit lines BLjB (j = 0, 1,. The bit lines BLjA and BLjB (j = 128, 129,..., 255) become floating.
[0147]
At the time of reading cell data to the bit line, equalization may be performed between the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) by setting the control signal φEQ2 to 3V, or the shielded bit line may be equalized. BLjA and BLjB (j = 128, 129,..., 255) may be independently connected (not equalized) and precharged to the reference potential of 1.5 V independently.
[0148]
<When amplifying and sensing the first page data read to the bit line>
After the potential of the bit line BLjA (j = 0, 1,..., 127) is determined by reflecting the data of the memory cell selected by the word line WL00, the potential of the bit line will be described in (Example 2). In the same manner as above, sensing is performed differentially. At this time, the bit lines BLjA and BLjB (j = 128, 129,..., 255) to be shielded are in a floating state, but are equalized by maintaining the control signal φEQ2 at 3 V to become the same potential (1.5 V). I have. By performing differential sensing, if the cell data read to the bit line BLjA (j = 0, 1,..., 127) is “0”, the bit line BLjA becomes 3 V and the bit line BLjB (j = 0, , 127) becomes 0V.
[0149]
Therefore, as shown in FIG. 36 (a), the bit line BLjA (j = 128, 129,..., 255) shielded by sensing has a capacitance between the bit line BLjA (j = 0, 1,..., 127). The potential rises from the reference potential by δ due to the coupling. On the other hand, the potential of the shielded bit line BLjB (j = 128, 129,..., 255) drops from the reference potential by −δ due to capacitive coupling with the bit line BLjB (j = 0, 1,..., 127). . However, since the shielding is equalized between the bit lines BLjA and BLjB (j = 128, 129,..., 255), the bit line capacitive coupling noise δ applied to the bit line BLjA and the bit line capacitive coupling noise applied to the bit line BLjB. −δ cancel each other, and as a result, the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are kept at the reference potential of 1.5V.
[0150]
Similarly, when the data read to the bit line BLjA (j = 0, 1,..., 127) is “1”, the bit line BLjA (j = 0, 1, 1) as shown in FIG. , 127) and BLjB (j = 0, 1,..., 127) can be connected (equalized) so that the shielded bit line can maintain the reference potential.
[0151]
<When reading the data of the second page>
As described above, after reading the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127), the bit lines BLjA, BLjB (j = 128, 129,..., 255) Have already been precharged to 1.5V. After the sensing operation, one of the bit lines BLjA (j = 0, 1,..., 127) and the bit line BLjB (j = 0, 1,. Therefore, when reading data to be connected to the bit line BLjA (j = 128, 129,..., 255) next, if φEQ1 is set to 3V (φE1 may be set to 3V), precharge is performed. The bit lines BLjA and BLjB (j = 0, 1,..., 127) to be shielded can be set to the reference potential of 1.5 V without performing the above operation.
[0152]
Therefore, after reading the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) for one page, the memory cell connected to the bit line BLjA (j = 128, 129,. In the second precharge, the bit line BLjA (128, 129,..., 255) to be read only needs to be changed from 1.5V to 1.7V.
[0153]
When reading is performed using the bit line shield as described above, the bit line to be shielded can be set to a reference potential other than 0 V by applying the memory cell array and the sense amplifier of the present invention. As a result, when data over a plurality of pages is read, precharge can be reduced, reading can be speeded up, and power consumption can be reduced.
[0154]
In this embodiment, the bit lines BLjA and BLjB are equalized by the control signals φEQ1 and φEQ2, but may be equalized by the control signals φE1 and φE2. 33 and 34, the node between the source and the drain of the two transistors selected by the control signal φE1 (φE2) is fixed at Vcc / 2 potential (for example, 1.5 V). When reading the cell data to the bit line, the bit lines to be shielded may be left floating as shown in FIGS. 33 and 34. However, when the bit line is sensed, the bit line to be shielded is set to the floating state, so that the terminal connected to this node is set to the floating state. There is a need.
[0155]
In this embodiment, after the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) is read, the memory cell connected to the bit line BLjA (j = 128, 129,. In this example, the bit line to be read has an arbitrary property. Any bit line may be used as long as the bit line connected to the sense amplifier SA2 is read after the bit line connected to the sense amplifier SA1 is read. Alternatively, the bit line connected to the sense amplifier SA1 may be read after the bit line connected to the sense amplifier SA2 is read.
[0156]
The present invention is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. FIGS. 37 and 38 show a memory cell array in the case of employing the shared sense amplifier system. FIG. 39 is a diagram showing a specific configuration of the sense amplifier SA3. After being connected to the bit line BLjA (j = 0, 1,..., 127) and reading the data of the memory cell selected by the word line WL00, it is connected to the bit line BLjA (j = 128, 129,..., 255). FIG. 40 is a timing chart when reading data from the memory cell selected by the word line WL00. The read operation is almost the same as that of the above-described embodiment having one sense amplifier per bit line.
[0157]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. The memory cell array connected to the bit line BLj in FIG. 31 may be the same as the memory cell array connected to the bit line BLjA in FIG.
[0158]
Further, in this embodiment, when the potential of the read bit line is sensed after the cell data is read to the bit line, the two bit lines to be shielded are connected (equalized) to the reference potential. I was keeping it. When sensing the potential of the bit line, the two bit lines to be shielded may not be equalized, and may be kept connected to the terminal for applying the reference potential. For example, when shielding the bit line connected to the sense amplifier shown in FIG. 23 or 33 (keeping it at the reference potential), φPA1 and φPB1 are set to 3 V, TG1 and TG2 are set to 0 V, and VA1 and VB1 are set to the reference potential (for example, 1. 5V).
[0159]
(Example 4)
An example for solving (Problem 3) will be described below from (Example 3).
[0160]
FIG. 32 is a block diagram showing a configuration of the NAND cell type EEPROM according to the present embodiment, similarly to (Embodiment 3). The memory cell array is the same as in the third embodiment. That is, the memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) in the memory cell arrays 1A, 1B may be either FIG. 22 or FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) in the memory cell arrays 1A, 1B may be either FIG. 23 or FIG.
[0161]
In the case where a bit line shield method in which every other bit line is kept at a reference potential at the time of reading in order to reduce the capacitance coupling between bit lines is performed, as described in (Embodiment 3), the writing operation is performed, for example, on the bit line BLjA (j = 0, 1,..., 127) and then write to the cells connected to the bit line BLjA (j = 128, 129,..., 255). In the write operation, first, write is performed, and then verify read is performed to check whether the write has been sufficiently performed. Then, the additional writing is not performed on the sufficiently written cells, and the additional writing is performed only on the insufficiently written cells. Here, the present embodiment will be described by taking as an example the case where the memory cell array 1A of FIG. 28 is connected to the bit line BLjA (j = 0, 1,..., 127) and the memory cell selected by the word line WL00 is written.
[0162]
FIG. 41 shows a write / write verify read operation excluding a data load operation of write data from the data input / output buffer 7 to the sense amplifier 2. Prior to writing, in the memory cell array, the control gates are all set to 0 V, and the p substrate (or p-type well and n substrate) on which the memory cells are formed is collectively erased with the high voltage Vpp (about 20 V). After the write data is latched from the data input / output buffer 7 to the CMOS flip-flop FF via the input / output lines I / O, I / O ', first, the control signals φPA1, φPA2, φPB1, φPB2 become 3V, and The bit line is reset.
[0163]
Thereafter, when the transfer gate control signals TGA1 and VSW connecting the bit lines BLjA (j = 0, 1,..., 127) to the sense amplifiers have an intermediate potential (about 10 V), the bit lines BLjA (j = 0, 1, 1) , 127) become an intermediate potential when it is "1" and 0 V when it is "0" according to the data. Since the bit line BLjA (j = 128, 129,..., 255) does not perform writing, it is charged to an intermediate potential from the terminal VA2. When the word line WL00 is selected by the row decoder 3, WL00 becomes Vpp, WL01 to WL07, SGD0 become an intermediate potential, and SGS0 becomes 0V.
[0164]
After a predetermined time (up to 20 μs), the control gate and the selection gate are reset to 0 V, the transfer gate control signal TGA1 becomes 0 V, and the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier are connected. Be separated. Thereafter, the control signal φPA1 becomes 3V, and the bit line BLjA (j = 0, 1,..., 127) is reset to 0V. VSW also becomes 3V. During this time, the bit line BLjA (j = 128, 129,..., 255) remains precharged to the intermediate potential.
[0165]
Next, a verify read operation is performed. First, φPA1 and φPB1 become 3V, the bit line BLjA (j = 0, 1,..., 127) is charged to 1.7V, and the bit line BLjB (j = 0, 1,..., 127) is charged to 1.5V. Thereafter, φPA1 and φPB1 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) are in a floating state. Next, for example, 0.5 V is applied to the control gate WL00, the word lines WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and the SGD0 is set to 3V. In normal reading, if the threshold value of the memory cell is 0 V or more, "0" is read, but in verify reading, "0" is not read unless the voltage is 0.5 V or more.
[0166]
After the bit line is discharged, the verify signal φAV becomes 3V, and when the bit line BLjA (j = 0, 1,..., 127) writes “1”, it is charged to about 3V. Here, the voltage level of the precharge performed by the verify signal may be 1.5 V or more of the precharge voltage of the bit line BLjB (j = 0, 1,..., 127). Thereafter, the equalizing signal φE becomes 3 V, and the sense amplifier is reset. Then, the transfer gate control signals TGA1 and TGB1 become 3 V, and the data of the bit line BLjA (j = 0, 1,..., 127) is read. The read data is latched by the sense amplifier and becomes data for the next rewrite.
[0167]
During the verify read, the bit line BLjA (j = 128, 129,..., 255) is not discharged, and maintains an intermediate potential, so that the bit line BLjA (j = 0, 1,. This reduces the coupling capacitance noise between bit lines.
[0168]
When the bit line BLjA (j = 0, 1,..., 127) is rewritten, the bit line BLjA (j = 128, 129,..., 255) has already been precharged to the intermediate potential, so there is no need to recharge. In addition, the charging time can be omitted. Further, the booster circuit that charges the intermediate potential consumes a large amount of power when boosting is started. Therefore, according to the present embodiment, power consumption during writing can be reduced.
[0169]
In this embodiment, during the verify read, the unselected bit lines BLjA (j = 128, 129,..., 255) are continuously charged to the intermediate potential. For example, by setting φPA2 to 0V, the unselected bit lines are set to the intermediate potential. May be in a floating state.
[0170]
This embodiment is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. FIGS. 37 and 38 show a memory cell array in the case of employing the shared sense amplifier system. FIG. 32 is a block diagram showing the configuration of the NAND cell type EEPROM in the case where the shared sense amplifier system is adopted, similarly to the third embodiment. FIG. 39 shows a sense amplifier SA3 when the shared sense amplifier system is adopted. The timing chart when the shared sense amplifier method is adopted is almost the same as FIG.
[0171]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. The memory cell array connected to the bit line BLj in FIG. 31 may be the same as the memory cell array connected to the bit line BLjA in FIG.
[0172]
The present invention can also be applied to a folded bit line system as shown in FIG. While writing is performed on a memory cell connected to one of the two bit lines (for example, BL0 in FIG. 42) connected to the sense amplifier, the other bit line BL1 sets the transfer gate control signal TG2 to 0 V and sets the terminal It is sufficient to keep charging from VB to the intermediate potential (about 10 V). Since the bit line BL1 is maintained at the intermediate potential during the verify read of the memory cell connected to the written bit line BL0, the verify read of the memory cell connected to the bit line BL0 cannot be performed differentially.
[0173]
However, for example, normal reading is performed differentially by the folded bit line method as described in (Embodiment 1), and during verify reading, as described in the section of [Prior Art], a single-ended type, that is, One of the two inverters constituting the flip-flop of the sense amplifier is made inactive, and as shown in FIG. 30, the read data is "0" depending on whether or not the potential of the bit line is higher than the circuit threshold of the inverter. It may be determined whether or not there is “1”.
[0174]
(Example 5)
In the present embodiment, SGD0 is applied to the drain-side select MOS transistors of half the memory cell units in one block selected by the row decoder 3 at the time of write verify read and normal read, and the source side is selected. When SGS0 is applied to the select MOS transistor, SGS0 is applied to the select MOS transistor on the drain side and SGD0 is applied to the select MOS transistor on the source side in the other half of the memory cell units.
[0175]
As a method of applying a voltage to the selection gate, for example, as shown in FIG. 43, a signal applied to a selection gate of a memory cell connected to bit lines BL0 to BL127 and a selection gate of a memory cell connected to bit lines BL128 to BL255 May be separately provided. Further, as shown in FIG. 44, the selection gate on the source side and the selection gate on the drain side may be exchanged in the middle of the memory cell array.
[0176]
43 and 44, for example, when reading out a memory cell selected by the word line WL00, if the selection gate SGS0 is set at 3V and SGD0 is set at 1.5V, it is connected to the bit line BLj (j; even number). The memory cell is read. In this case, among the unselected bit lines BLj (j; odd number) that are not read, the non-selected bit lines BLj (j = 1, 3, 5,..., 125, 127) have their source-side selection MOS transistors turned off, For the unselected bit lines BLj (j = 129, 131, 133,..., 253, 255), the drain-side selection MOS transistors are turned off. That is, half of the unselected bit lines are turned off by turning off the drain-side selection MOS transistors, and the remaining half of the unselected bit lines are turned off by turning off the source-side selection MOS transistors. Is stopped.
[0177]
On the other hand, when reading the memory cell connected to the bit line BLj (j; odd number) in FIGS. 43 and 44, the selection gate SGS0 may be set to 1.5V and the SGD0 may be set to 3V. In this case, among the unselected bit lines BLj (j; even number) that are not read, the drain-side selection MOS transistors of the unselected bit lines BLj (j = 0, 2, 4,..., 124, 126) are turned off, For the unselected bit lines BLj (j = 128, 130, 132,..., 252, 254), the source-side selection MOS transistors are turned off. That is, half of the unselected bit lines are turned off by turning off the drain-side selection MOS transistors, and the remaining half of the unselected bit lines are turned off by turning off the source-side selection MOS transistors. Is stopped.
[0178]
In this manner, when reading the odd-numbered bit lines or the even-numbered bit lines, the discharge of the bit lines is stopped by turning off the drain-side selection MOS transistors in half of the unselected bit lines. The discharge of the bit lines of the remaining half of the unselected bit lines is stopped by turning off the source side select MOS transistors. Therefore, the capacity of the entire non-selected bit line is the same when reading the odd-numbered bit line and when reading the even-numbered bit line, and when reading the bit line BLj (j; odd number), the bit line BLj (j ; Even), the precharge time and the read time can be the same.
[0179]
Here, the case of reading has been described, but even in the case of verify reading after writing, the capacity of the entire bit line is equal between the case of reading the odd-numbered bit line and the case of reading the even-numbered bit line.
[0180]
43 and 44 illustrate the folded bit line system as an example, the open bit line system described in (Embodiment 1) to (Embodiment 4) or the single-ended system may be used. Also, a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier may be used.
[0181]
(Example 6)
Next, another embodiment will be described. This embodiment is basically the same as the first embodiment, and differs from the first embodiment in that the type of the selection MOS transistor is changed.
[0182]
FIG. 45 is a diagram showing the configuration of the memory cell array in this embodiment. FIG. 2 is different from FIG. 2 in that a part of the I-type select MOS transistor is D-type.
[0183]
In FIG. 45, a selection MOS transistor having a high threshold Vt1 (for example, 2 V) is E-type, and a selection MOS transistor having a low threshold Vt2, Vt3 (for example, 0.5 V, -1 V) (Vt1>Vt2> Vt3). The transistors are described as I-type and D-type. The voltage applied to the selection gate is a voltage Vsgh (for example, 3 V) (Vsgh> Vt1, Vt2, Vt3) at which all of the I-type transistor, D-type and E-type transistors are turned on, and the I-type transistor is turned on. The voltage Vsgl1 (for example, 1.5 V) for turning off the E-type transistor (Vt1>Vsgl1> Vt2), and the voltage Vsgl2 (for example, 0 V) for turning off the E-type transistor while the D-type transistor turns on (Vt1> Vsgl2) > Vt3).
[0184]
A method for applying a voltage to the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00 and WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source-side select gate SGS0 is set to Vsgh, and the drain-side select gate SGD0 is set to Vsgl1. SGS1 and SGD1 are set to 0V. In this case, the source-side selection MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off, so that the bit line BL0 is discharged but the bit line / BL0 is not discharged. .
[0185]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl2, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, the drain-side selection MOS transistors STD00 and STD10 are both turned on. The source side select MOS transistor STS10 is turned on, so that the bit line / BL0 is discharged. However, since the select MOS transistor STS00 is turned off, the bit line BL0 is not discharged.
[0186]
The present invention is a selection MOS transistor connected to a bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 in FIG. 45). What is necessary is just to give a difference to the threshold value of STS11), and the way of setting the threshold value is arbitrary. In FIG. 45, the select MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type, and the select MOS transistors on the source side are E-type. For example, two NAND blocks sharing a bit line contact are used. One of the selection MOS transistors may be I-type and the other may be E-type.
[0187]
According to the present invention, of the select MOS transistors sharing one select gate, a conductive MOS transistor and a non-conductive MOS transistor can be generated, and by providing two such select gates, This utilizes the fact that a memory cell in a selected state and a memory cell in a non-selected state can be easily realized in memory cells having the same selection gate.
[0188]
As shown in FIG. 46, the selection MOS transistor connected to the drain side may be E-type or D-type, and the selection MOS transistor connected to the source side may be E-type or I-type. In this case, when selecting a memory cell (for example, MC000) in the memory cell unit 2, SGS0 may be set to Vsgh (for example, 3V), SGD0 may be set to Vsgl2 (for example, 0V), and SGD1 and SGS1 may be set to 0V. When selecting a memory cell (for example, MC100) in the memory cell unit 1, SGS0 may be set to Vsgl1 (for example, 1.5V), SGD0 may be set to Vsgh (for example, 3V), and SGS1 and SGD1 may be set to 0V.
[0189]
If Vsgh is made larger than Vcc, the conductance of the selection MOS transistor will increase (that is, the resistance will decrease), and the current flowing through the NAND cell row at the time of reading will increase, thereby shortening the bit line discharge time. Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0190]
The thresholds of the I-type selection MOS transistor and the D-type selection MOS transistor may both be negative thresholds (for example, -1 V and -2 V).
[0191]
The larger value Vt1 of the threshold values of the selection gates may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using a booster circuit inside the chip.
[0192]
Here, the operation when reading out the memory cell MC000 connected to the bit line BL1 in FIG. 48 will be described using the timing chart in FIG. The sense amplifier is formed by a CMOS flip-flop controlled by control signals SAN and SAP.
[0193]
First, the control signals φA and φB become Vss, and the CMOS flip-flop FF is disconnected from the bit lines BL0 and BL1. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), and the bit line BL1 is precharged to VB (eg, 1.7V) and the dummy bit line BL0 is precharged to VA (eg, 1.5V) (time). t1). When the precharge is completed, φpA and φpB become Vss, and the bit lines BL0 and BL1 enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the control gate (time t2).
[0194]
When reading the memory cell MC000 in FIG. 48, WL00 is 0V, WL01 to WL07 are 3V, SGD0 is 3V, and SGS0 is 1.5V. When the data written in the memory cell MC000 is “0”, the cell current does not flow because the threshold value of the memory cell MC000 is positive, and the potential of the bit line BL1 remains at 1.7 V. When the data is "1", a cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. Further, since the selection gate SGS0 is at 1.5V, the selection gate transistor STS10 is turned off, and the bit line BL0 is not discharged regardless of the data written in the memory cell MC100, and is maintained at the precharge potential of 1.5V. .
[0195]
Then, at time t3, SAP becomes 3V and SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2. (For example, 1.5 V). At time t5, φA and φB become 3V, and after the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BL0 and BL1 is amplified. Thereafter, at time t7, the SAP changes from 3V to 0V, and the data is latched. That is, if “0” is written in the memory cell MC000, the node N1 becomes 3V and the node N2 becomes 0V. If “1” is written in the memory cell MC000, the node N1 becomes 0V and the node N2 becomes 3V. Become. Thereafter, when the column selection signal CSL1 changes from 0V to 3V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t8).
[0196]
The timing of the read operation is arbitrary. For example, at time t5, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BL1 and BL2 to the nodes N1 and N2, and then the transfer gate may be turned off. Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined during sensing and data latching.
[0197]
At the time of the sense operation of the sense amplifier, first, SAN is changed from 0 V to 3 V to turn on the N-channel transistor of the CMOS flip-flop FF, and then SAP is changed from 3 V to 0 V to turn on the P-channel transistor of the CMOS flip-flop FF. However, SAP may be changed from 3V to 0V at the same time as SAN is changed from 0V to 3V.
[0198]
In the above embodiment, while discharging the bit line connected to the memory cell to be read, the other dummy bit line of the bit line pair connected to the sense amplifier (for example, the memory cell MC000 in FIG. 48 is read) In this case, the bit line BL0 is in a floating state, and when the memory cell MC100 is read, the bit line BL1) is in a floating state. However, even when the bit line BL1 is precharged and the data of the memory cell MC000 is subsequently read, the precharge control signal φpA is kept at 3V to fix the reference dummy bit line BL0 to the reference potential 1.5V. You can also.
[0199]
By keeping the dummy bit line at the reference potential in this manner, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. Also, as in the case of the above-mentioned read, during the verify read after the write, the bit line is charged and discharged according to the data written to the cell. However, if the dummy bit line not to be read is kept at the reference potential, the bit line is caused by the capacitive coupling between the bit lines. Noise can be reduced.
[0200]
<Write>
A write operation of the present embodiment, for example, a write procedure for writing to the memory cell MC000 in FIG. 48 will be described below.
[0201]
The selection gate SGD0, the control gates WL01 to WL07 are set at the intermediate potential Vm (about 10 V), the WL00 is set at Vpp (about 20 V), and the bit line BL0 is charged from VA to Vm8 (about 8 V). When "1" is written to the memory cell MC000, Vm8 is applied from the flip-flop FF, and when "0" is written, 0 V is applied to the bit line BL1. Then, electrons are not injected into the floating gate of the memory cell MC100 where no writing is performed and the memory cell MC000 where “1” writing is performed, and electrons are injected from the channel into the floating gate of the memory cell MC000 where “0” writing is performed. Is done.
[0202]
After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation ends.
[0203]
When writing to the MC000 of the memory cell array as shown in FIG. 45, a voltage (for example, −3 V) that turns off the D-type selection MOS transistor STS10 may be applied to the selection gate SGS0.
[0204]
After the end of the write, a write verify operation is performed to check whether the write has been performed sufficiently.
[0205]
First, φA and φB become Vcc, precharge signals φpB and φpA become Vcc, and the bit line BL1 is precharged to, for example, 1.7V and the (dummy) bit line BL0 is precharged to, for example, 1.5V.
[0206]
When the precharge ends, φpA and φpB become Vss, and the bit lines BL1 and BL0 enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate. The control gate WL00 has a verify voltage (for example, 0.5V), WL01 to WL07 have Vcc (for example, 3V), SGS0 has 1.5V, and SGD0 has 3V. When "0" is sufficiently written in the memory cell MC000, the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit line BL1 remains at 1.7 V. When "1" write or "0" write is insufficient, a cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. During this time, the dummy bit line BL0 may be floating, or φpA may be fixed to 1.5 V by setting it to Vcc. If the dummy bit line is maintained at a constant voltage, the capacitance coupling noise between the bit lines during bit line discharge can be significantly reduced.
[0207]
After the bit line discharge, the verify signal φBV becomes 3V, and when the data written to the memory cell MC000 is “1”, the bit line BL1 is charged to about 3V. Here, the voltage level of the charge performed by the verify signal only needs to be 1.5 V or more of the precharge voltage of the dummy bit line BL0.
[0208]
Thereafter, SAP becomes 3V, SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). become. Thereafter, φA and φB become 3V, and after the bit line and the sense amplifier are connected, SAN becomes 0V to 3V and SAP becomes 3V to 0V, the potential difference between the bit line BL1 and the dummy bit line BL0 is amplified, and the potential difference is increased. The write data is latched by the sense amplifier.
[0209]
Thus, according to the present embodiment, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line can be increased without increasing the chip area, as in the first embodiment. The method can be realized, and high-speed random reading can be performed. As a method of changing the threshold value, various methods described in the first embodiment can be adopted.
[0210]
【The invention's effect】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0211]
(Example 1)
Hereinafter, an embodiment that solves (Problem 1) will be described.
[0212]
FIG. 1 is a block diagram showing an entire configuration of a NAND cell type EEPROM according to a first embodiment of the present invention. In the figure, 1 is a memory cell array, 2 is a sense amplifier and latch circuit as latch means for writing and reading data, 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, and 5 is a column decoder. An address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0213]
FIG. 2 is a diagram showing the configuration of a memory cell array, where BL and / BL are bit lines, WL is a word line, STD is a first selection MOS transistor connected to the drain side of a NAND cell, and STS is the source side of a NAND cell. SGD is a select gate for driving the select MOS transistor STD, SGS is a select gate for driving the select MOS transistor STS, SA is a sense amplifier, and TG is a sense amplifier SA and a bit line. A control signal for driving a gate for connecting BL is shown.
[0214]
As shown in FIG. 2, the sense amplifier SA receives an adjacent pair of bit lines BLj and / BLj as inputs. This is a folded bit line system used in DRAM. In order to realize the folded bit line system, it is necessary to prevent one bit line of a bit line pair from discharging when the other bit line is discharged. A difference is provided between the threshold values of the selection MOS transistors (for example, STS00 and STS10, STD00 and STD10 in FIG. 2) sharing the same selection gate, and different voltages are applied to the drain-side selection gate and the source-side selection gate. To achieve this.
[0215]
In FIG. 2, a select MOS transistor having a high threshold value Vt1 (eg, 2 V) is referred to as E-type, and a select MOS transistor having a low threshold value Vt2 (eg, 0.5 V) (Vt1> Vt2) is referred to as I-type. ing. The voltages applied to the gates (selection gates) of the two types of selection MOS transistors include a voltage Vsgh (for example, 3 V) that turns on both the I-type transistor and the E-type transistor (Vsgh> Vt1, Vt2), and an I-type transistor. Is turned on but the E-type transistor is turned off at a voltage Vsgl (for example, 1.5 V) (Vt1>Vsgl> Vt2).
[0216]
Here, the memory cell is an electrically rewritable nonvolatile memory cell in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate. Memory section). The I-type STS and the E-type STD are connected to the NAND cell to form a first memory cell unit. The E-type STS and the I-type STD are connected to the NAND cell to form the second memory cell unit. Of memory cell units, and the first and second memory cell units are alternately arranged. Further, a sub-array is constituted by a plurality of first and second memory cell units sharing a word line.
[0219]
With reference to FIG. 2, a method for applying a voltage to the selection gate will be specifically described. For example, when reading data from the memory cell MC000, the word lines WL00 and WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source-side select gate SGS0 is set to Vsgh, and the drain-side select gate SGD0 is set to Vsgl. SGS1 and SGD1 are set to 0V. In this case, the source-side selection MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off. Therefore, if the data of the memory cell MC000 is "1", the bit line BL0 is turned off. The bit line / BL0 does not discharge regardless of the data in the memory cell MC100.
[0218]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source-side select gate SGS0 is set to Vsgl, and the drain-side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, the drain-side selection MOS transistors STD00 and STD10 are both turned on. The source side select MOS transistor STS10 is turned on, so that the bit line / BL0 is discharged if the data of the memory cell MC100 is "1", but the select MOS transistor STS00 is turned off, so that the bit line BL0 is not discharged.
[0219]
The present invention is a selection MOS transistor connected to a bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 of FIG. 2). What is necessary is just to give a difference to the threshold value of STS11), and the way of setting the threshold value is arbitrary. For example, as shown in FIG. 3, the selection MOS transistor STD00 of the bit line BLj may be E-type, the STS00 may be I-type, the selection MOS transistor STD10 of the bit line / BLj may be I-type, and the STS10 may be E-type.
[0220]
In FIG. 2, the drain-side select MOS transistors of the cells connected to the bit line BLj are all I-type, and the source-side select MOS transistors are E-type. However, as shown in FIG. 4, for example, the bit line contacts are shared. In the two NAND blocks, one of the drain-side selection MOS transistors may be I-type and the other may be E-type. 2 to 4, alternately disposed bit lines BLj are simultaneously selected and read. For example, as shown in FIG. 5, the threshold value of the selection MOS transistor is set to select bit line BL0 as shown in FIG. In this case, the bit line / BL1 may be selected.
[0221]
In the present invention, not only this (Embodiment 1) but also all the embodiments up to (Embodiment 5) which will be described later, among the selection MOS transistors sharing one selection gate, the selection MOS transistors having a conduction state and the non-selection MOS transistors sharing a non-selection gate have a non-selection state. A conductive state can be generated, and by providing two such select gates, a memory cell in a selected state and a memory cell in a non-selected state can be easily selected from memory cells having the same select gate. I use what I can do.
[0222]
Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate have arbitrary characteristics. The drain-side select MOS transistor has two threshold values of Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to the drain-side select gate is Vsghd (Vsghd> Vtd1) and Vsgld (Vtd1>Vsgld> Vtd2). The source-side selection MOS transistor has two thresholds of Vts1 and Vts2 (Vts1> Vts2), and the voltages applied to the source-side selection gate are Vsghs (Vsghs> Vts1) and Vsgls ( Vts1>Vsgls> Vts2), and may not be Vtd1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, Vsgld = Vsgls as in the above embodiment.
[0223]
For example, the threshold voltage of the drain-side select MOS transistor is set to two types of 2 V and 0.5 V, and the threshold value of the source-side select MOS transistor is set to two types of 2.5 V and 1 V. The voltage applied may be Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the source side select gate may be Vsgh = 3V, Vsgl = 1.2V.
[0224]
If Vsgh is made larger than Vcc, the conductance of the select MOS transistor will increase (that is, the resistance will decrease), and the cell current flowing through the NAND cell row at the time of reading will increase. As a result, the bit line discharge time will be shortened. , Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0225]
The selection MOS transistors sharing one selection gate are all turned on. The voltage Vsgh of the selection gate is desirably equal to or lower than the power supply voltage Vcc. When Vsgh is larger than Vcc, a booster circuit is required in the chip, which leads to an increase in chip area.
[0226]
Further, the smaller threshold value Vt2 of the selection MOS transistor may be a negative threshold value (for example, -1 V). At the time of writing, 0 V is applied to the bit line connected to the cell to be written, and an intermediate potential (about 10 V) is applied to the bit line connected to the cell not to be written. The source-side select gate must be turned off so that no current flows. Therefore, when Vt2 is set to a negative threshold value of about -1 V, a negative voltage (for example, -1.5 V) that turns off the negative-threshold selection gate is applied to the source-side selection gate during writing. Just fine.
[0227]
The larger value Vt1 of the threshold values of the selection gates may be set to a voltage equal to or higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using a booster circuit inside the chip.
[0228]
Here, the operation when reading out the memory cell MC000 connected to the bit line BLj in FIG. 6 will be described with reference to the timing chart in FIG. The sense amplifier is formed by a CMOS flip-flop controlled by control signals SAN and SAP.
[0229]
First, the control signal TG changes from Vcc (for example, 3 V) to Vss, and the CMOS flip-flop FF is disconnected from the bit lines BLj and / BLj. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BLj is precharged to VA (eg, 1.7 V), and the bit line / BLj is precharged to VB (eg, 1.5 V) ( Time t1). When the precharge ends, φpA and φpB become Vss, and the bit lines BLj and / BLj enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the selection gate (time t2).
[0230]
When reading the memory cell MC000 in FIG. 6, WL00 is 0 V, WL01 to WL07 are 3 V, SGD0 is 3 V (Vsgh), and SGS0 is 1.5 V (Vsgl). When the data written in the memory cell MC000 is “0”, the cell current does not flow because the threshold value of the memory cell MC000 is positive, and the potential of the bit line BLj remains at 1.7 V. When the data is “1”, the cell current flows and the potential of the bit line BLj decreases to 1.5 V or less. Further, since the selection gate SGS0 is at 1.5 V, the selection transistor STS10 is turned off, and the bit line / BLj is not discharged regardless of the data written in the memory cell MC100, and is maintained at the precharge potential of 1.5 V. .
[0231]
Then, at time t3, SAP becomes 3 V and SAN becomes 0 V, the CMOS flip-flop FF is inactivated, and φE becomes 3 V at time t4, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / V. 2 (for example, 1.5 V). After TG becomes 3V at time t5 and the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BLj and / BLj is amplified. Thereafter, at time t7, the SAP changes from 3V to 0V, and the data is latched.
[0232]
That is, if “0” is written in the memory cell MC000, the node N1 becomes 3V and the node N2 becomes 0V. If "1" is written in MC000, the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSLj changes from 0 V to 3 V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t8).
[0233]
Next, FIG. 10 shows a timing chart when the memory cell MC100 connected to the bit line / BLj in FIG. 6 is read. In this case, the bit line BLj is precharged to 1.5 V and the bit line / BLj is precharged to 1.7 V (time t1). The voltage applied to the control gate (word line) from the row decoder 3 when reading the cell data to the bit line is the same as that for reading the memory cell MC000, except that the voltage applied to the selection gate is 1.5 V for SGD0 and SGS0. Is 3V (time t2).
[0234]
When the data written in the memory cell MC100 is "0", the cell current does not flow because the threshold value of the memory cell MC100 is positive, and the potential of the bit line / BLj remains at 1.7V. When the data is "1", the cell current flows and the potential of the bit line / BLj decreases to 1.5 V or less. Further, since the selection gate SGD0 is 1.5V, the selection MOS transistor STD00 is turned off, and the bit line BLj is not discharged regardless of the data written in the memory cell MC000, and is maintained at the precharge potential 1.5V. . After that, the data read to the bit line / BLj is sensed and latched by the sense amplifier in the same manner as when reading the memory cell MC000, and is output to I / O and I / O '.
[0235]
The timing of the read operation is arbitrary. For example, at time t5, as shown in FIG. 9, the transfer gate connecting the bit line and the sense amplifier is turned on to transfer the potentials of the bit lines BLj and / BLj to the nodes N1 and N2, and then the transfer gate is turned off. . Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined during sensing and data latching.
[0236]
In the timing charts of FIGS. 8 to 10, during the sensing operation of the sense amplifier, first, SAN is set from 0 V to 3 V to turn on the N-channel transistor of the CMOS flip-flop FF, and then SAP is set from 3 V to 0 V, and then the CMOS flip-flop FF is turned on. Are turned on, but SAP may be changed from 3V to 0V almost simultaneously with changing SAN from 0V to 3V.
[0237]
When the data of the cell connected to the bit line BLj is sensed and latched by the sense amplifier, one of the potentials of the bit lines BLj and / BLj is 0 V and the other is Vcc (for example, 3 V). After the cell data of the bit line BLj is output from the sense amplifier to I / O, I / O ', if .phi.E is set to 3 V, the bit lines BLj and / BLj are connected (equalized), and the bit line BLj is not precharged. , / BLj become 1.5V. Thereafter, for example, when reading out the bit line / BLj, the bit line / BLj may be precharged to 1.7 V by setting φPB to 3 V and VB to 1.7 V. By connecting the bit lines BLj and / BLj after sensing the bit line BLj in this manner, the precharge time for the next read can be shortened and the power consumption required for the precharge can be reduced.
[0238]
As shown in FIG. 7, a circuit for performing verification after writing to the sense amplifier may be added.
[0239]
As a method of precharging a different potential to the bit line pair, a dummy cell may be provided as shown in FIG. 11, for example, in addition to the method of transferring the potentials VA and VB from the peripheral circuit as shown in FIG. In this case, the bit lines BLj and / BLj are precharged to the same potential VPR. The current flowing in the dummy cell is smaller than the worst read current of the cell. For example, a dummy NAND type cell connected in series may be a depletion type transistor, the channel length L may be increased, and the channel width W may be reduced.
[0240]
If the threshold value of the dummy selection MOS transistor is set as shown in FIG. 11, when data of a memory cell connected to bit line BLj is read to bit line BLj, bit line / BLj is discharged through the dummy cell and bit line / BLj is discharged. When reading data from the memory cell connected to / BLj, the bit line BLj is discharged through the dummy cell.
[0241]
The operation of this embodiment will be described by taking a case where the memory cell MC000 is read as an example. First, the precharge control signal PRE becomes 3 V, and the bit lines BLj and / BLj are precharged to a precharge potential VPR (for example, 1.7 V). Thereafter, the control gate line and the selection gate of the memory cell are selected, 0V is applied to the dummy word line DWL, and substantially the same voltage as the voltage applied to the selection gates SGS and SGD of the selection MOS transistor is applied to the dummy selection gates DSGS and DSGD. Is done.
[0242]
If "0" is written in the memory cell MC000, the bit line BLj does not discharge and keeps the precharge potential of 1.7 V. If "1" is written in MC000, the bit line BLj is discharged to, for example, 1.3V. When the bit line BLj in which "1" is written is discharged to 1.3 V, the bit line / BLj may be discharged to 1.5 V through the dummy cell. Thereafter, the operation of differentially amplifying the potential of the bit line pair by the sense amplifier is the same as in the embodiment of FIG.
[0243]
As a method of precharging a different potential to the bit line pair, the dummy cell may be constituted by one transistor and one capacitor as shown in FIG. First, the bit line precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to the same potential VPR. When the data of the memory cell MC000 is read out to the bit line BLj after the control signal PRE becomes 0V and the bit line is in a floating state, φPB becomes 3V and the capacitor C1 is charged. The bit line / BLj drops from the precharge potential VPR by the charge charged in the capacitor C1. This may be used as a reference potential for differentially amplifying the bit line pair.
[0244]
When reading data from the memory cell MC100 to the bit line / BLj, the capacitor C0 is charged when φPA becomes 3 V, and the bit line BLj falls from the precharge potential VPR. This bit line BLj may be set to the reference potential.
[0245]
In the embodiments of FIGS. 6 to 10, while discharging the bit line to which the memory cell to be read is connected, the other bit line (for example, the memory of FIG. 6) of the bit line pair connected to the sense amplifier is discharged. When reading the cell MC000, the bit line / BLj is in a floating state, and when reading the memory cell MC100, the bit line BLj) is in a floating state. However, while the bit line (for example, the bit line BLj) is precharged to 1.7 V and the data of the memory cell is thereafter read, the precharge control signal φPB is kept at 3 V, so that the reference bit line (for example, the bit line BLj) becomes The bit line / BLj) can be fixed at a reference potential of 1.5V.
[0246]
By maintaining the bit line / BLj at the reference potential in this manner, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. As in the case of the above-mentioned read, during the verify read after the write (described in detail in the fourth embodiment), the bit line is charged and discharged according to the data written in the cell, but the bit line / BLj which is not read is set to the reference potential. , Noise due to capacitive coupling between bit lines can be reduced.
[0247]
In order to reduce noise due to capacitive coupling between adjacent bit lines when sensing and latching data of a memory cell read to a bit line, a twisted bit line method proposed in a DRAM as shown in FIG. It may be. A twisted bit line system as shown in FIG. 14 may be used.
[0248]
The selection MOS transistor may be constituted by a cell having a selection gate and a floating gate as shown in FIG. In the case of this embodiment, the threshold value of the selection MOS transistor can be determined by injecting electrons into the floating gate of the selection MOS transistor before shipping the semiconductor memory device. The injection of electrons into the floating gate of the drain-side select MOS transistor (eg, STD00 in FIG. 15) may be performed by tunneling from the substrate.
[0249]
That is, the word lines WL00 to WL07 are at an intermediate potential (about 10V) or 0V, the selection gate SGD0 is at Vpp (about 20V), the selection gate SGD0 is at 0V, the bit line BL0 is at 0V, and the bit lines / BL0, BL1, and / BL1 are at an intermediate potential. The potential (about 10 V) may be set. Further, in order to determine the threshold value of the source-side selection MOS transistor, the selection gates SGD0, SGS0 and the word lines WL00 to WL07 are all set to "H" to turn on all the NAND cell columns, and Vpp or Vpp is applied to the bit line BL0. Hot electrons may be injected by applying 0 V to the intermediate potential and the bit lines / BL0, BL1, and / BL1.
[0250]
As described above, according to the present invention, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line method can be realized without increasing the chip area, and high-speed random read can be performed. Will be possible. As a method of changing the threshold value, changing the gate oxide film thickness of the selection MOS transistor, changing the concentration of the channel-doped impurity in the selection MOS transistor, and the like can be considered. Alternatively, the threshold value may be different depending on whether or not the select MOS transistor is channel-doped with impurities. The threshold value can also be changed by changing the channel length of the selection MOS transistor. That is, since the threshold value of a transistor having a short channel length is reduced due to the short channel effect, the transistor may be used as an I-type transistor.
[0251]
As a method of changing the gate oxide film thickness and the impurity concentration of the channel, another manufacturing process such as channel doping of a peripheral circuit may be used without introducing a new manufacturing process. In any case, the threshold value of the selection MOS transistor may be made different, and if the threshold value is made different, a predetermined threshold value can be obtained by a substrate bias or the like.
[0252]
In the conventional NAND cell type EEPROM, 0 V is applied to the select gate on the source side of the write block. However, when the select MOS transistor on the source side is I-type and the threshold value Vt2 is about 0.1 V (or negative). In the case of a threshold value, the source-side select MOS transistor does not completely cut off, the cell current flows for example 0.1 μA, and the unwritten bit line is discharged from the intermediate potential (about 10 V).
[0253]
For example, if the bit lines are charged to an intermediate potential without writing to the memory cells connected to the 200 bit lines, the cell current will flow in total of 200 × 0.1 μA = 20 μA. In order to improve the cut-off characteristics of the I-type transistor, a voltage of, for example, about 0.5 V may be applied to the common source line at the time of writing. When 0.5 V is applied to the source, the potential difference between the source and the substrate becomes -0.5 V, and the threshold value of the I-type transistor increases due to the body bias effect. Therefore, 0 V is applied to the gate of the I-type transistor. The cut-off characteristic at the time of reading is improved, and the cell current at the time of reading can be reduced.
[0254]
In order to set the smaller one (I-type) of the thresholds of the selection gates to, for example, 0.5 V, a method of reducing the substrate concentration may be considered. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate expands, and as a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are reduced. However, there is a problem in that the connection and the dullness (punch through) occur. In order to increase the punch-through breakdown voltage of the I-type select MOS transistor, the channel length L of the I-type select MOS transistor may be increased.
[0255]
In the above embodiment, the NAND cell type EEPROM has been described. However, the nonvolatile semiconductor memory in which the drain side of the memory cell is connected to the bit line via the selection gate, and the source side of the memory cell is also connected to the source line via the selection gate. The present invention is effective for a device. For example, the present invention is also effective in an AND cell type EEPROM (H. Kume el al .; IEDM Tech. Dig., Dec. 1992, pp. 991-993) as shown in FIG. A NOR type EEPROM or a mask ROM having one memory cell between the gate and the source side select gate is also effective.
[0256]
(Example 2)
Hereinafter, an embodiment that solves (Problem 2) will be described.
[0257]
FIG. 17 is a block diagram showing a configuration of a NAND cell type EEPROM according to the present embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means, and the memory cell is divided into 1A and 1B because of the open bit line system. The memory cell arrays 1A and 1B are each divided into at least two predetermined units.
[0258]
In the present embodiment, it is assumed that one page has 256 bits, and the memory cell arrays 1A and 1B are divided into 1A1, 1A2 and 1B1, 1B2 in units of 128 bits. Reference numeral 2 denotes a sense amplifier circuit as latch means for writing and reading data, and is divided into at least two for each predetermined unit, similarly to the memory cell arrays 1A and 1B. In FIG. 17, the sense amplifier is divided into 2A and 2B. Reference numeral 3 denotes a row decoder for selecting a word line, 4 denotes a column decoder for selecting a bit line, 5 denotes an address buffer, 6 denotes an I / O sense amplifier, 7 denotes a data input / output buffer, and 8 denotes a substrate potential control circuit.
[0259]
The memory cell array 1A1 is shown in FIGS. 18 and 1B1, FIGS. 19 and 1A2 are shown in FIGS. 18 to 21, the threshold values of the selection MOS transistors in the memory cell array have two kinds of values as in the above (Embodiment 1). It is assumed that the threshold value of the selection MOS transistor denoted by E-type is 2 V, and the threshold value of the selection MOS transistor denoted by I-type is 0.5 V. Therefore, when both the E-type select MOS transistor and the I-type select MOS transistor are turned on, Vcc (for example, 3 V) is applied to the select gate, and when only the I-type is turned on, 1.V. 5 V is applied.
[0260]
When reading data from the memory cell array 1A1 to the bit lines BL0A to BL127A, the drain-side select gate SGD is set at 3V, and the source-side select gate SGS is set at 1.5V. On the other hand, when data of the memory cell array 1A2 is read to the bit lines BL128A to BL255A, the selection gate SGD on the drain side is set to 1.5V and the selection gate SGS on the source side is set to 3V. When simultaneously reading data from the memory cell arrays 1A1 and 1A2, both SGS and SGD may be set to 3V.
[0261]
The sense amplifier is a differential sense amplifier as in the folded bit line system of the first embodiment. FIG. 22 shows the sense amplifier 2A (SA1) connected to the memory cell arrays 1A1 and 1B1, and FIG. 23 shows the sense amplifier 2B (SA2) connected to the memory cell arrays 1A2 and 1B2.
[0262]
Here, taking the case of reading data written in two pages as an example, the read operation of the present embodiment will be described with reference to the timing charts of FIGS. First, on the first page, the sense amplifiers 2A (SA1) and 2B (SA2) operate simultaneously. The control signals TG1, TG2 change from 3V to 0V, and the CMOS flip-flops FF1, FF2 are disconnected from the bit lines BLjA, BLjB (j = 0, 1,..., 255).
[0263]
Next, the precharge signals φpA1, φpB1, φpA2, and φpB2 change from 0 V to 3 V, the bit line BLjA (j = 0, 1,..., 255) becomes 1.7 V, for example, and the bit line BLjB (j = 0, 1). ,..., 255) are precharged to, for example, 1.5V. When the precharge is completed, φpA1, φpB1, φpA2, and φpB2 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 255) enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate.
[0264]
18 and 19, WL00 is 0V, WL01 to WL07 are 3V, SGD0 is 3V, and SGS0 is 3V. When the data written to the memory cell selected by the word line WL00 is "0", the threshold value of the memory cell is positive, so that no cell current flows and the potential of the bit line BLjA remains at 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLjA decreases to 1.5 V or less. Further, the bit line BLjB is not discharged, and is kept at the precharge potential 1.5V.
[0265]
Thereafter, SAP1 and SAP2 become 3V, SAN1 and SAN2 become 0V, CMOS flip-flops FF1 and FF2 are inactivated, and φE1 and φE2 become 3V, thereby resetting CMOS flip-flops FF1 and FF2. After TG1 and TG2 become 3V and the bit lines and the sense amplifier are connected, SAN1 and SAN2 become 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 255) is amplified. You. Thereafter, SAP1 and SAN2 change from 0V to 3V, and the data is latched. Then, column selection signals CSLj (j = 0, 1,..., 255) are successively selected, and the data latched by the CMOS flip-flop is output to I / O, I / O ′ (page read).
[0266]
After the page read of the first half data (column addresses 0 to 127) of the first page, while the page read of the second half data of the first page, the first half data (bit line BLjA; j) of the row address of the second page = 0, 1,..., 127. This may be performed, for example, by detecting that the column address is 128.
[0267]
First, the precharge signals φpA1, φpB1, φpA2, and φpB2 change from 0V to 3V, the bit line BLjA (j = 0, 1,..., 127) becomes 1.7V and the bit lines BLjB (j = 0, 1,. 127) is precharged to 1.5V. When the precharge is completed, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 becomes 0V, WL00, WL02 to WL07 become 3V, SGD0 becomes 3V, and SGS0 becomes 1.5V.
[0268]
When the data written in the memory cell selected by the word line WL01 is "0", the cell current does not flow because the memory cell threshold is positive, and the bit line BLjA (j = 0, 1,..., 127) Remains at 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLjA (j = 0, 1,..., 127) drops to 1.5 V or less. The bit line BLjB (j = 0, 1,..., 127) is not discharged, and the precharge potential 1.5 V is maintained.
[0269]
Thereafter, SAP1 becomes 3V, SAN1 becomes 0V, the CMOS flip-flop FF1 is inactivated, and φE1 becomes 3V, thereby equalizing the CMOS flip-flop FF1. After TG1 becomes 3V and the bit line is connected to the sense amplifier, SAN1 becomes 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 127) is amplified. Thereafter, SAP1 and SAN2 change from 0V to 3V, and the data is latched by the sense amplifier 2A (SA1).
[0270]
At the point where the page read of the first page has advanced by 256 column addresses, the data of the next 128 pages of the second page has already been latched by the sense amplifier 2A (SA1), so there is no need to perform the random read operation. . During the page read from the sense amplifier 2A (SA1) to the second page column addresses 0 to 127, a random read operation is performed on the second half column addresses 128 to 255 of the second page. That is, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0 V, WL00 and WL02 to WL07 are 3 V, SGD0 is 1.5 V, and SGS0 is 3 V.
[0271]
When the data written in the memory cell selected by the word line WL01 is "0", the cell current does not flow because the memory cell threshold is positive, and the potential of the bit line BLjA remains at 1.7 V. When the data is "1", a cell current flows and the potential of the bit line BLjA (j = 128, 129,..., 255) drops to 1.5 V or less.
[0272]
Further, the bit line BLjB (j = 128, 129,..., 255) is not discharged, and is kept at the precharge potential 1.5V. Then, SAP2 becomes 3V, SAN2 becomes 0V, the CMOS flip-flop FF2 is inactivated, and φE2 becomes 3V, whereby the CMOS flip-flop FF2 is reset. Then, after TG2 becomes 3V and the bit line is connected to the sense amplifier, SAN2 becomes 0V to 3V and the potential difference between the bit lines BLjA and BLjB (j = 128, 129,..., 255) is amplified. Thereafter, SAP2 changes from 3V to 0V, and the data is latched by the sense amplifier 2B (SA2).
[0273]
When the page read of the second page has advanced by 128 column addresses, since the data of the second half 128 column addresses of the next second page has already been latched by the sense amplifier 2B (SA2), a random read operation is performed. It is possible to serially read the data of the second half column address of 128 columns without need.
[0274]
The present invention is not limited to the above embodiment. In the above embodiment, the memory cell is divided into two, but may be divided into, for example, four or an arbitrary number.
[0275]
The timing charts of FIGS. 24 and 25 are merely examples. In the timing charts of FIGS. 24 and 25, the data of the first page is read by the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) at the same time. However, as shown in the timing charts of FIGS. First, a random read of the memory cell corresponding to the first half column address of the first page is performed, and then the second half of the first page data is randomly read while the first half of the first page data is read. Good.
[0276]
Further, in FIGS. 24 and 25, bit lines are precharged simultaneously by random reading of the first half data of the second page and random reading of the second half data of the second page, but as shown in FIGS. The timing of precharging the bit lines may be changed between the case of random reading with 2A (SA1) and the case of random reading with sense amplifier 2B (SA2).
[0277]
Further, the division of the memory cell array need not be a physically continuous one as one division unit. For example, as shown in FIGS. 28 and 29, the bit lines connected to the sense amplifier SA1 and the bit lines connected to the sense amplifier SA2 may be arranged alternately. While the bit line connected to the sense amplifier SA1 is randomly read, the bit line connected to the sense amplifier SA2 can be grounded to 0 V. In this case, the distance between the bit lines connected to the sense amplifier SA1 is shown in FIGS. In the case of random read, noise can be reduced due to capacitive coupling between bit lines during random read.
[0278]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. In FIG. 31, the memory cell array connected to the bit line BLj (j = 0, 1,..., 255) may be the same as the memory cell array connected to the bit line BLjA (j = 0, 1,. Good.
[0279]
(Example 3)
Hereinafter, an embodiment that solves (Problem 3) will be described.
[0280]
In the conventional memory cell array, when a word line which is the row decoder 3 is selected at the time of reading and writing, all the memory cells disposed at the intersection of the selected word line and the bit line are selected. Therefore, one of the memory cells connected to the adjacent bit line cannot be selected and the other cannot be deselected.
[0281]
As described in the above (Embodiment 1) and (Embodiment 2), according to the present invention, the threshold values of the source side select MOS transistor and the drain side select MOS transistor of the NAND block are changed, By changing the voltage applied to the side select gate and the drain side select gate, one of the adjacent bit lines can be selected and the other bit line can be deselected. As a result, it is possible to shorten the precharge time and reduce power consumption by omitting the precharge to the bit line at the time of reading and writing.
[0282]
Therefore, in the present embodiment (Embodiment 3), an embodiment will be described in which the precharge time is shortened at the time of reading to reduce power consumption. An example in which the precharge time is shortened at the time of writing to reduce power consumption will be described in the next embodiment (Embodiment 4).
[0283]
FIG. 32 is a block diagram showing a configuration of a NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means, which is divided into two parts 1A and 1B by an open bit line system. In this embodiment, one page has 256 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch unit for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0284]
The memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) of FIG. 28 provided in the memory cell arrays 1A and 1B is not FIG. 22 but FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA and BLjB (j = 128, 129,..., 255) of FIG. 29 provided in the memory cell arrays 1A and 1B is not FIG. 23 but FIG. In the sense amplifiers SA1 and SA2 in FIGS. 33 and 34, a transistor for equalizing (making the same potential) between the bit lines BLjA and BLjB by the control signals φEQ1 and φEQ2 is added to the sense amplifiers SA1 and SA2 in FIGS. Have been.
[0285]
At the time of reading, every other bit line is kept at a reference potential in order to reduce noise due to capacitive coupling between bit lines (bit line shield). In this case, the write operation is first performed on, for example, a cell connected to the bit line BLjA (j = 0, 1,..., 127), and then connected to the bit line BLjA (j = 128, 129,..., 255). Write to the cell to be written. Here, the data (the first page data) written to the bit line BLjA (j = 0, 1,..., 127) is first read, and then the data is written to the bit line BLjA (j = 128, 129,. This embodiment will be described by taking as an example a case where written data (data of the second page) is read.
[0286]
When reading the data of the bit line BLjA (j = 0, 1,..., 127), the shielded bit line BLjA (j = 128, 129,..., 255) is kept at the reference potential (for example, 1.5 V). In the conventional memory cell array, adjacent bit lines are simultaneously selected and discharged, so that only 0 V can be applied to the shielded bit lines. The timing chart of FIG. 35 is divided into a case where the data of the first page is read to the bit line, a case where the data read to the bit line is sensed by the sense amplifier, and a case where the data of the second page is read to the bit line. This will be described with reference to FIG.
[0287]
<When reading data of the first page to the bit line>
When reading out a memory cell selected by the word line WL00 in the memory cell array of FIG. 28 and connected to the bit line BLjA (j = 0, 1,..., 127), first, the bit line BLjA (j = 0, 1,. , 127) to 1.7 V and the bit line BLjB (j = 128, 129,..., 255) to 1.5 V to shield the bit lines BLjA, BLjB (j = 128, 129,..., 255). Is precharged to a reference potential (for example, 1.5 V).
[0288]
After the bit line precharge, the control gate WL00 is set to 0V, the WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and the SGD0 is set to 3V. In this case, the selection MOS transistor on the source side of bit line BLjA (j = 0, 1,..., 127) turns on, but the selection MOS transistor on the source side of bit line BLjA (j = 128, 129,..., 255) Turns off. Therefore, the bit line BLjA (j = 0, 1,..., 127) is discharged if the data of the memory cell selected by the word line WL00 is “1”, but the bit line BLjA (j = 128, 129,. 255) does not discharge.
[0289]
When the bit line BLjA (j = 0, 1,..., 127) discharges, the potential of the bit line BLjA (j = 128, 129,..., 255) drops from the reference potential due to capacitive coupling between bit lines. While the line BLjA (j = 0, 1,..., 127) is discharging, for example, VA2 and VB2 are set to the reference potential of 1.5 V, and the control signals φPA2 and φPB2 are set to 3 V, so that the bit lines BLjA and BLjB ( .., 255) can be maintained at the reference potential at the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255).
[0290]
After the cell data is read to the bit line BLjA (j = 0, 1,..., 127), the control signals φPA2, φPB2 become 0 V, and the bit lines BLjB (j = 0, 1,. The bit lines BLjA and BLjB (j = 128, 129,..., 255) become floating.
[0291]
At the time of reading cell data to the bit line, equalization may be performed between the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) by setting the control signal φEQ2 to 3V, or the shielded bit line may be equalized. BLjA and BLjB (j = 128, 129,..., 255) may be independently connected (not equalized) and precharged to the reference potential of 1.5 V independently.
[0292]
<When amplifying and sensing the first page data read to the bit line>
After the potential of the bit line BLjA (j = 0, 1,..., 127) is determined by reflecting the data of the memory cell selected by the word line WL00, the potential of the bit line will be described in (Example 2). In the same manner as above, sensing is performed differentially. At this time, the bit lines BLjA and BLjB (j = 128, 129,..., 255) to be shielded are in a floating state, but are equalized by maintaining the control signal φEQ2 at 3 V to become the same potential (1.5 V). I have. By performing differential sensing, if the cell data read to the bit line BLjA (j = 0, 1,..., 127) is “0”, the bit line BLjA becomes 3 V and the bit line BLjB (j = 0, , 127) becomes 0V.
[0293]
Therefore, as shown in FIG. 36 (a), the bit line BLjA (j = 128, 129,..., 255) shielded by sensing has a capacitance between the bit line BLjA (j = 0, 1,..., 127). The potential rises from the reference potential by δ due to the coupling. On the other hand, the potential of the shielded bit line BLjB (j = 128, 129,..., 255) drops from the reference potential by −δ due to capacitive coupling with the bit line BLjB (j = 0, 1,..., 127). . However, since the shielding is equalized between the bit lines BLjA and BLjB (j = 128, 129,..., 255), the bit line capacitive coupling noise δ applied to the bit line BLjA and the bit line capacitive coupling noise applied to the bit line BLjB. −δ cancel each other, and as a result, the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are kept at the reference potential of 1.5V.
[0294]
Similarly, when the data read to the bit line BLjA (j = 0, 1,..., 127) is “1”, the bit line BLjA (j = 0, 1, 1) as shown in FIG. , 127) and BLjB (j = 0, 1,..., 127) can be connected (equalized) so that the shielded bit line can maintain the reference potential.
[0295]
<When reading the data of the second page>
As described above, after reading the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127), the bit lines BLjA, BLjB (j = 128, 129,..., 255) Have already been precharged to 1.5V. After the sensing operation, one of the bit lines BLjA (j = 0, 1,..., 127) and the bit line BLjB (j = 0, 1,. Therefore, when reading data to be connected to the bit line BLjA (j = 128, 129,..., 255) next, if φEQ1 is set to 3V (φE1 may be set to 3V), precharge is performed. The bit lines BLjA and BLjB (j = 0, 1,..., 127) to be shielded can be set to the reference potential of 1.5 V without performing the above operation.
[0296]
Therefore, after reading the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) for one page, the memory cell connected to the bit line BLjA (j = 128, 129,. In the second precharge, the bit line BLjA (128, 129,..., 255) to be read only needs to be changed from 1.5V to 1.7V.
[0297]
When reading is performed using the bit line shield as described above, the bit line to be shielded can be set to a reference potential other than 0 V by applying the memory cell array and the sense amplifier of the present invention. As a result, when data over a plurality of pages is read, precharge can be reduced, reading can be speeded up, and power consumption can be reduced.
[0298]
In this embodiment, the bit lines BLjA and BLjB are equalized by the control signals φEQ1 and φEQ2, but may be equalized by the control signals φE1 and φE2. 33 and 34, the node between the source and the drain of the two transistors selected by the control signal φE1 (φE2) is fixed at Vcc / 2 potential (for example, 1.5 V). When reading the cell data to the bit line, the bit lines to be shielded may be left floating as shown in FIGS. 33 and 34. However, when the bit line is sensed, the bit line to be shielded is set to the floating state, so that the terminal connected to this node is set to the floating state. There is a need.
[0299]
In this embodiment, after the data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) is read, the memory cell connected to the bit line BLjA (j = 128, 129,. In this example, the bit line to be read has an arbitrary property. Any bit line may be used as long as the bit line connected to the sense amplifier SA2 is read after the bit line connected to the sense amplifier SA1 is read. Alternatively, the bit line connected to the sense amplifier SA1 may be read after the bit line connected to the sense amplifier SA2 is read.
[0300]
The present invention is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. FIGS. 37 and 38 show a memory cell array in the case of employing the shared sense amplifier system. FIG. 39 is a diagram showing a specific configuration of the sense amplifier SA3. After being connected to the bit line BLjA (j = 0, 1,..., 127) and reading the data of the memory cell selected by the word line WL00, it is connected to the bit line BLjA (j = 128, 129,..., 255). FIG. 40 is a timing chart when reading data from the memory cell selected by the word line WL00. The read operation is almost the same as that of the above-described embodiment having one sense amplifier per bit line.
[0301]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. The memory cell array connected to the bit line BLj in FIG. 31 may be the same as the memory cell array connected to the bit line BLjA in FIG.
[0302]
Further, in this embodiment, when the potential of the read bit line is sensed after the cell data is read to the bit line, the two bit lines to be shielded are connected (equalized) to the reference potential. I was keeping it. When sensing the potential of the bit line, the two bit lines to be shielded may not be equalized, and may be kept connected to the terminal for applying the reference potential. For example, when shielding the bit line connected to the sense amplifier shown in FIG. 23 or 33 (keeping it at the reference potential), φPA1 and φPB1 are set to 3 V, TG1 and TG2 are set to 0 V, and VA1 and VB1 are set to the reference potential (for example, 1. 5V).
[0303]
(Example 4)
An example for solving (Problem 3) will be described below from (Example 3).
[0304]
FIG. 32 is a block diagram showing a configuration of the NAND cell type EEPROM according to the present embodiment, similarly to (Embodiment 3). The memory cell array is the same as in the third embodiment. That is, the memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) in the memory cell arrays 1A, 1B may be either FIG. 22 or FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) in the memory cell arrays 1A, 1B may be either FIG. 23 or FIG.
[0305]
In the case where a bit line shield method in which every other bit line is kept at a reference potential at the time of reading in order to reduce the capacitance coupling between bit lines is performed, as described in (Embodiment 3), the writing operation is performed, for example, on the bit line BLjA (j = 0, 1,..., 127) and then write to the cells connected to the bit line BLjA (j = 128, 129,..., 255). In the write operation, first, write is performed, and then verify read is performed to check whether the write has been sufficiently performed. Then, the additional writing is not performed on the sufficiently written cells, and the additional writing is performed only on the insufficiently written cells. Here, the present embodiment will be described by taking as an example the case where the memory cell array 1A of FIG. 28 is connected to the bit line BLjA (j = 0, 1,..., 127) and the memory cell selected by the word line WL00 is written.
[0306]
FIG. 41 shows a write / write verify read operation excluding a data load operation of write data from the data input / output buffer 7 to the sense amplifier 2. Prior to writing, in the memory cell array, the control gates are all set to 0 V, and the p substrate (or p-type well and n substrate) on which the memory cells are formed is collectively erased with the high voltage Vpp (about 20 V). After the write data is latched from the data input / output buffer 7 to the CMOS flip-flop FF via the input / output lines I / O, I / O ', first, the control signals φPA1, φPA2, φPB1, φPB2 become 3V, and The bit line is reset.
[0307]
Thereafter, when the transfer gate control signals TGA1 and VSW connecting the bit lines BLjA (j = 0, 1,..., 127) to the sense amplifiers have an intermediate potential (about 10 V), the bit lines BLjA (j = 0, 1, 1) , 127) become an intermediate potential when it is "1" and 0 V when it is "0" according to the data. Since the bit line BLjA (j = 128, 129,..., 255) does not perform writing, it is charged to an intermediate potential from the terminal VA2. When the word line WL00 is selected by the row decoder 3, WL00 becomes Vpp, WL01 to WL07, SGD0 become an intermediate potential, and SGS0 becomes 0V.
[0308]
After a predetermined time (up to 20 μs), the control gate and the selection gate are reset to 0 V, the transfer gate control signal TGA1 becomes 0 V, and the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier are connected. Be separated. Thereafter, the control signal φPA1 becomes 3V, and the bit line BLjA (j = 0, 1,..., 127) is reset to 0V. VSW also becomes 3V. During this time, the bit line BLjA (j = 128, 129,..., 255) remains precharged to the intermediate potential.
[0309]
Next, a verify read operation is performed. First, φPA1 and φPB1 become 3V, the bit line BLjA (j = 0, 1,..., 127) is charged to 1.7V, and the bit line BLjB (j = 0, 1,..., 127) is charged to 1.5V. Thereafter, φPA1 and φPB1 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) are in a floating state. Next, for example, 0.5 V is applied to the control gate WL00, the word lines WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and the SGD0 is set to 3V. In normal reading, if the threshold value of the memory cell is 0 V or more, "0" is read, but in verify reading, "0" is not read unless the voltage is 0.5 V or more.
[0310]
After the bit line is discharged, the verify signal φAV becomes 3V, and when the bit line BLjA (j = 0, 1,..., 127) writes “1”, it is charged to about 3V. Here, the voltage level of the precharge performed by the verify signal may be 1.5 V or more of the precharge voltage of the bit line BLjB (j = 0, 1,..., 127). Thereafter, the equalizing signal φE becomes 3 V, and the sense amplifier is reset. Then, the transfer gate control signals TGA1 and TGB1 become 3 V, and the data of the bit line BLjA (j = 0, 1,..., 127) is read. The read data is latched by the sense amplifier and becomes data for the next rewrite.
[0311]
During the verify read, the bit line BLjA (j = 128, 129,..., 255) is not discharged, and maintains an intermediate potential, so that the bit line BLjA (j = 0, 1,. This reduces the coupling capacitance noise between bit lines.
[0312]
When the bit line BLjA (j = 0, 1,..., 127) is rewritten, the bit line BLjA (j = 128, 129,..., 255) has already been precharged to the intermediate potential, so there is no need to recharge. In addition, the charging time can be omitted. Further, the booster circuit that charges the intermediate potential consumes a large amount of power when boosting is started. Therefore, according to the present embodiment, power consumption during writing can be reduced.
[0313]
In this embodiment, during the verify read, the unselected bit lines BLjA (j = 128, 129,..., 255) are continuously charged to the intermediate potential. For example, by setting φPA2 to 0V, the unselected bit lines are set to the intermediate potential. May be in a floating state.
[0314]
This embodiment is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. FIGS. 37 and 38 show a memory cell array in the case of employing the shared sense amplifier system. FIG. 32 is a block diagram showing the configuration of the NAND cell type EEPROM in the case where the shared sense amplifier system is adopted, similarly to the third embodiment. FIG. 39 shows a sense amplifier SA3 when the shared sense amplifier system is adopted. The timing chart when the shared sense amplifier method is adopted is almost the same as FIG.
[0315]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be employed. The memory cell array connected to the bit line BLj in FIG. 31 may be the same as the memory cell array connected to the bit line BLjA in FIG.
[0316]
The present invention can also be applied to a folded bit line system as shown in FIG. While writing is performed on a memory cell connected to one of the two bit lines (for example, BL0 in FIG. 42) connected to the sense amplifier, the other bit line BL1 sets the transfer gate control signal TG2 to 0 V and sets the terminal It is sufficient to keep charging from VB to the intermediate potential (about 10 V). Since the bit line BL1 is maintained at the intermediate potential during the verify read of the memory cell connected to the written bit line BL0, the verify read of the memory cell connected to the bit line BL0 cannot be performed differentially.
[0317]
However, for example, normal reading is performed differentially by the folded bit line method as described in (Embodiment 1), and during verify reading, as described in the section of [Prior Art], a single-ended type, that is, One of the two inverters constituting the flip-flop of the sense amplifier is made inactive, and as shown in FIG. 30, the read data is "0" depending on whether or not the potential of the bit line is higher than the circuit threshold of the inverter. It may be determined whether or not there is “1”.
[0318]
(Example 5)
In the present embodiment, SGD0 is applied to the drain-side select MOS transistors of half the memory cell units in one block selected by the row decoder 3 at the time of write verify read and normal read, and the source side is selected. When SGS0 is applied to the select MOS transistor, SGS0 is applied to the select MOS transistor on the drain side and SGD0 is applied to the select MOS transistor on the source side in the other half of the memory cell units.
[0319]
As a method of applying a voltage to the selection gate, for example, as shown in FIG. 43, a signal applied to a selection gate of a memory cell connected to bit lines BL0 to BL127 and a selection gate of a memory cell connected to bit lines BL128 to BL255 May be separately provided. Further, as shown in FIG. 44, the selection gate on the source side and the selection gate on the drain side may be exchanged in the middle of the memory cell array.
[0320]
43 and 44, for example, when reading out a memory cell selected by the word line WL00, if the selection gate SGS0 is set at 3V and SGD0 is set at 1.5V, it is connected to the bit line BLj (j; even number). The memory cell is read. In this case, among the unselected bit lines BLj (j; odd number) that are not read, the non-selected bit lines BLj (j = 1, 3, 5,..., 125, 127) have their source-side selection MOS transistors turned off, For the unselected bit lines BLj (j = 129, 131, 133,..., 253, 255), the drain-side selection MOS transistors are turned off. That is, half of the unselected bit lines are turned off by turning off the drain-side selection MOS transistors, and the remaining half of the unselected bit lines are turned off by turning off the source-side selection MOS transistors. Is stopped.
[0321]
On the other hand, when reading the memory cell connected to the bit line BLj (j; odd number) in FIGS. 43 and 44, the selection gate SGS0 may be set to 1.5V and the SGD0 may be set to 3V. In this case, among the unselected bit lines BLj (j; even number) that are not read, the drain-side selection MOS transistors of the unselected bit lines BLj (j = 0, 2, 4,..., 124, 126) are turned off, For the unselected bit lines BLj (j = 128, 130, 132,..., 252, 254), the source-side selection MOS transistors are turned off. That is, half of the unselected bit lines are turned off by turning off the drain-side selection MOS transistors, and the remaining half of the unselected bit lines are turned off by turning off the source-side selection MOS transistors. Is stopped.
[0322]
In this manner, when reading the odd-numbered bit lines or the even-numbered bit lines, the discharge of the bit lines is stopped by turning off the drain-side selection MOS transistors in half of the unselected bit lines. The discharge of the bit lines of the remaining half of the unselected bit lines is stopped by turning off the source side select MOS transistors. Therefore, the capacity of the entire non-selected bit line is the same when reading the odd-numbered bit line and when reading the even-numbered bit line, and when reading the bit line BLj (j; odd number), the bit line BLj (j ; Even), the precharge time and the read time can be the same.
[0323]
Here, the case of reading has been described, but even in the case of verify reading after writing, the capacity of the entire bit line is equal between the case of reading the odd-numbered bit line and the case of reading the even-numbered bit line.
[0324]
43 and 44 illustrate the folded bit line system as an example, the open bit line system described in (Embodiment 1) to (Embodiment 4) or the single-ended system may be used. Also, a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier may be used.
[0325]
(Example 6)
Next, another embodiment will be described. This embodiment is basically the same as the first embodiment, and differs from the first embodiment in that the type of the selection MOS transistor is changed.
[0326]
FIG. 45 is a diagram showing the configuration of the memory cell array in this embodiment. FIG. 2 is different from FIG. 2 in that a part of the I-type select MOS transistor is D-type.
[0327]
In FIG. 45, a selection MOS transistor having a high threshold Vt1 (for example, 2 V) is E-type, and a selection MOS transistor having a low threshold Vt2, Vt3 (for example, 0.5 V, -1 V) (Vt1>Vt2> Vt3). The transistors are described as I-type and D-type. The voltage applied to the selection gate is a voltage Vsgh (for example, 3 V) (Vsgh> Vt1, Vt2, Vt3) at which all of the I-type transistor, D-type and E-type transistors are turned on, and the I-type transistor is turned on. The voltage Vsgl1 (for example, 1.5 V) for turning off the E-type transistor (Vt1>Vsgl1> Vt2), and the voltage Vsgl2 (for example, 0 V) for turning off the E-type transistor while the D-type transistor turns on (Vt1> Vsgl2) > Vt3).
[0328]
A method for applying a voltage to the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00 and WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source-side select gate SGS0 is set to Vsgh, and the drain-side select gate SGD0 is set to Vsgl1. SGS1 and SGD1 are set to 0V. In this case, the source-side selection MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off, so that the bit line BL0 is discharged but the bit line / BL0 is not discharged. .
[0329]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl2, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, the drain-side selection MOS transistors STD00 and STD10 are both turned on. The source side select MOS transistor STS10 is turned on, so that the bit line / BL0 is discharged. However, since the select MOS transistor STS00 is turned off, the bit line BL0 is not discharged.
[0330]
The present invention is a selection MOS transistor connected to a bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 in FIG. 45). What is necessary is just to give a difference to the threshold value of STS11), and the way of setting the threshold value is arbitrary. In FIG. 45, the select MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type, and the select MOS transistors on the source side are E-type. For example, two NAND blocks sharing a bit line contact are used. One of the selection MOS transistors may be I-type and the other may be E-type.
[0331]
According to the present invention, of the select MOS transistors sharing one select gate, a conductive MOS transistor and a non-conductive MOS transistor can be generated, and by providing two such select gates, This utilizes the fact that a memory cell in a selected state and a memory cell in a non-selected state can be easily realized in memory cells having the same selection gate.
[0332]
As shown in FIG. 46, the selection MOS transistor connected to the drain side may be E-type or D-type, and the selection MOS transistor connected to the source side may be E-type or I-type. In this case, when selecting a memory cell (for example, MC000) in the memory cell unit 2, SGS0 may be set to Vsgh (for example, 3V), SGD0 may be set to Vsgl2 (for example, 0V), and SGD1 and SGS1 may be set to 0V. When selecting a memory cell (for example, MC100) in the memory cell unit 1, SGS0 may be set to Vsgl1 (for example, 1.5V), SGD0 may be set to Vsgh (for example, 3V), and SGS1 and SGD1 may be set to 0V.
[0333]
If Vsgh is made larger than Vcc, the conductance of the selection MOS transistor will increase (that is, the resistance will decrease), and the current flowing through the NAND cell row at the time of reading will increase, thereby shortening the bit line discharge time. Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0334]
The thresholds of the I-type selection MOS transistor and the D-type selection MOS transistor may both be negative thresholds (for example, -1 V and -2 V).
[0335]
The larger value Vt1 of the threshold values of the selection gates may be set to a voltage higher than the power supply voltage Vcc (for example, 3.5 V). In this case, in order to turn on the selection MOS transistor having the threshold value of Vt1 at the time of reading or verify reading, for example, 4 V may be applied to the selection gate using a booster circuit inside the chip.
[0336]
Here, the operation when reading out the memory cell MC000 connected to the bit line BL1 in FIG. 48 will be described using the timing chart in FIG. The sense amplifier is formed by a CMOS flip-flop controlled by control signals SAN and SAP.
[0337]
First, the control signals φA and φB become Vss, and the CMOS flip-flop FF is disconnected from the bit lines BL0 and BL1. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), and the bit line BL1 is precharged to VB (eg, 1.7V) and the dummy bit line BL0 is precharged to VA (eg, 1.5V) (time). t1). When the precharge is completed, φpA and φpB become Vss, and the bit lines BL0 and BL1 enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the control gate (time t2).
[0338]
When reading the memory cell MC000 in FIG. 48, WL00 is 0V, WL01 to WL07 are 3V, SGD0 is 3V, and SGS0 is 1.5V. When the data written in the memory cell MC000 is “0”, the cell current does not flow because the threshold value of the memory cell MC000 is positive, and the potential of the bit line BL1 remains at 1.7 V. When the data is "1", a cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. Further, since the selection gate SGS0 is at 1.5V, the selection gate transistor STS10 is turned off, and the bit line BL0 is not discharged regardless of the data written in the memory cell MC100, and is maintained at the precharge potential of 1.5V. .
[0339]
Then, at time t3, SAP becomes 3V and SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2. (For example, 1.5 V). At time t5, φA and φB become 3V, and after the bit line and the sense amplifier are connected (time t6), SAN becomes 0V to 3V and the potential difference between the bit lines BL0 and BL1 is amplified. Thereafter, at time t7, the SAP changes from 3V to 0V, and the data is latched. That is, if “0” is written in the memory cell MC000, the node N1 becomes 3V and the node N2 becomes 0V. If “1” is written in the memory cell MC000, the node N1 becomes 0V and the node N2 becomes 3V. Become. Thereafter, when the column selection signal CSL1 changes from 0V to 3V, the data latched by the CMOS flip-flop is output to I / O and I / O '(time t8).
[0340]
The timing of the read operation is arbitrary. For example, at time t5, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BL1 and BL2 to the nodes N1 and N2, and then the transfer gate may be turned off. Therefore, since the load capacitance of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined during sensing and data latching.
[0341]
At the time of the sense operation of the sense amplifier, first, SAN is changed from 0 V to 3 V to turn on the N-channel transistor of the CMOS flip-flop FF, and then SAP is changed from 3 V to 0 V to turn on the P-channel transistor of the CMOS flip-flop FF. However, SAP may be changed from 3V to 0V at the same time as SAN is changed from 0V to 3V.
[0342]
In the above embodiment, while discharging the bit line connected to the memory cell to be read, the other dummy bit line of the bit line pair connected to the sense amplifier (for example, the memory cell MC000 in FIG. 48 is read) In this case, the bit line BL0 is in a floating state, and when the memory cell MC100 is read, the bit line BL1) is in a floating state. However, even when the bit line BL1 is precharged and the data of the memory cell MC000 is subsequently read, the precharge control signal φpA is kept at 3V to fix the reference dummy bit line BL0 to the reference potential 1.5V. You can also.
[0343]
By keeping the dummy bit line at the reference potential in this manner, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. Also, as in the case of the above-mentioned read, during the verify read after the write, the bit line is charged and discharged according to the data written to the cell. However, if the dummy bit line not to be read is kept at the reference potential, the bit line is caused by the capacitive coupling between the bit lines. Noise can be reduced.
[0344]
<Write>
A write operation of the present embodiment, for example, a write procedure for writing to the memory cell MC000 in FIG. 48 will be described below.
[0345]
The selection gate SGD0, the control gates WL01 to WL07 are set at the intermediate potential Vm (about 10 V), the WL00 is set at Vpp (about 20 V), and the bit line BL0 is charged from VA to Vm8 (about 8 V). When "1" is written to the memory cell MC000, Vm8 is applied from the flip-flop FF, and when "0" is written, 0 V is applied to the bit line BL1. Then, electrons are not injected into the floating gate of the memory cell MC100 where no writing is performed and the memory cell MC000 where “1” writing is performed, and electrons are injected from the channel into the floating gate of the memory cell MC000 where “0” writing is performed. Is done.
[0346]
After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation ends.
[0347]
When writing to the MC000 of the memory cell array as shown in FIG. 45, a voltage (for example, −3 V) that turns off the D-type selection MOS transistor STS10 may be applied to the selection gate SGS0.
[0348]
After the end of the write, a write verify operation is performed to check whether the write has been performed sufficiently.
[0349]
First, φA and φB become Vcc, precharge signals φpB and φpA become Vcc, and the bit line BL1 is precharged to, for example, 1.7V and the (dummy) bit line BL0 is precharged to, for example, 1.5V.
[0350]
When the precharge ends, φpA and φpB become Vss, and the bit lines BL1 and BL0 enter a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate. The control gate WL00 has a verify voltage (for example, 0.5V), WL01 to WL07 have Vcc (for example, 3V), SGS0 has 1.5V, and SGD0 has 3V. When "0" is sufficiently written in the memory cell MC000, the cell current does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit line BL1 remains at 1.7 V. When "1" write or "0" write is insufficient, a cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. During this time, the dummy bit line BL0 may be floating, or φpA may be fixed to 1.5 V by setting it to Vcc. If the dummy bit line is maintained at a constant voltage, the capacitance coupling noise between the bit lines during bit line discharge can be significantly reduced.
[0351]
After the bit line discharge, the verify signal φBV becomes 3V, and when the data written to the memory cell MC000 is “1”, the bit line BL1 is charged to about 3V. Here, the voltage level of the charge performed by the verify signal only needs to be 1.5 V or more of the precharge voltage of the dummy bit line BL0.
[0352]
Thereafter, SAP becomes 3V, SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V, the CMOS flip-flop FF is equalized, and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). become. Thereafter, φA and φB become 3V, and after the bit line and the sense amplifier are connected, SAN becomes 0V to 3V and SAP becomes 3V to 0V, the potential difference between the bit line BL1 and the dummy bit line BL0 is amplified, and the potential difference is increased. The write data is latched by the sense amplifier.
[0353]
Thus, according to the present embodiment, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line can be increased without increasing the chip area, as in the first embodiment. The method can be realized, and high-speed random reading can be performed. As a method of changing the threshold value, various methods described in the first embodiment can be adopted.
[Brief description of the drawings]
FIG. 1 is a diagram showing an entire configuration of a NAND cell type EEPROM according to a first embodiment.
FIG. 2 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 3 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 4 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 5 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 6 is a diagram illustrating a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 7 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 8 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 9 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 10 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 11 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 12 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 13 is a diagram showing a configuration of a twisted bit line system.
FIG. 14 is a diagram showing a configuration of a twisted bit line system.
FIG. 15 is a diagram showing a configuration of a memory cell array in which a selection MOS transistor has a selection gate and a floating gate.
FIG. 16 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 17 is a diagram showing an entire configuration of a NAND cell type EEPROM according to a second embodiment.
FIG. 18 is a diagram showing a configuration of a memory cell array according to the second embodiment.
FIG. 19 is a diagram showing a configuration of a memory cell array in a second embodiment.
FIG. 20 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 21 is a diagram showing a configuration of a memory cell array according to the second embodiment.
FIG. 22 is a diagram showing a configuration of a sense amplifier circuit according to the second embodiment.
FIG. 23 is a diagram showing a configuration of a sense amplifier circuit according to the second embodiment.
FIG. 24 is a timing chart for explaining a data read operation in the second embodiment.
FIG. 25 is a timing chart for explaining a data read operation in the second embodiment.
FIG. 26 is a timing chart for explaining a data read operation in the second embodiment.
FIG. 27 is a timing chart for explaining a data read operation in the second embodiment.
FIG. 28 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 29 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 30 illustrates a configuration of an inverter type sense amplifier circuit.
FIG. 31 is a diagram showing a configuration of a single-ended memory cell array and a sense amplifier.
FIG. 32 is a diagram showing an entire configuration of a NAND cell type EEPROM according to a third embodiment.
FIG. 33 is a diagram showing a configuration of a sense amplifier circuit according to the third embodiment.
FIG. 34 is a diagram showing a configuration of a sense amplifier circuit according to the third embodiment.
FIG. 35 is a timing chart for explaining a data read operation in the third embodiment.
FIG. 36 is a diagram showing the influence of noise on adjacent bit lines due to capacitive coupling between bit lines when amplifying a bit line potential.
FIG. 37 is a diagram showing a configuration of a memory cell array of a shared sense amplifier system.
FIG. 38 is a diagram showing a configuration of a memory cell array of a shared sense amplifier system.
FIG. 39 is a diagram showing a configuration of a sense amplifier circuit of a shared sense amplifier system.
FIG. 40 is a timing chart for explaining a data read operation in the third embodiment.
FIG. 41 is a timing chart for explaining a data write operation in the fourth embodiment.
FIG. 42 is a diagram showing a configuration of a folded bit line type sense amplifier circuit in a fourth embodiment.
FIG. 43 is a diagram showing a configuration of a memory cell array in a fifth embodiment.
FIG. 44 is a diagram showing a configuration of a memory cell array in the fifth embodiment.
FIG. 45 is a diagram showing a configuration of a memory cell array in a sixth embodiment.
FIG. 46 is a diagram showing a configuration of a memory cell array in a sixth embodiment.
FIG. 47 is a timing chart for explaining a data read operation in the sixth embodiment.
FIG. 48 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to a sixth embodiment.
[Explanation of symbols]
1, 1A, 1B, 1A1, 1A2, 1B1, 1B2 ... memory cell array
2, 2A, 2B: sense amplifier and latch circuit
3, 3A, 3B ... row decoder
4: Column decoder
5 ... Address buffer
6 I / O sense amplifier
7 Data input / output buffer
8. Substrate potential control circuit
BL: bit line
WL: Word line
STD: First selection MOS transistor
STS: second selection MOS transistor
SGD: First selection gate
SGS: Second selection gate

Claims (4)

A NAND cell unit in which a plurality of nonvolatile memory cells are connected in series and one end is connected to a bit line and the other end is connected to a source line;
A memory cell array composed of a plurality of the NAND cell units;
A readout circuit for precharging the bit line and reading data stored in the NAND cell unit by whether or not the NAND cell unit flows a current from the bit line to the source line;
A plurality of latch circuits connected to each bit line and temporarily storing data read from the NAND cell unit;
A data output circuit that outputs data of the latch circuit to the outside,
A non-volatile semiconductor memory device, wherein data from the latch circuit is output from the data output circuit to the outside and data is read from the NAND cell unit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said latch circuit further has a function of sensing a potential of a bit line. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a MOS transistor for controlling connection between said bit line and said latch circuit is provided between said bit line and said latch circuit. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the data of the plurality of latch circuits is output a plurality of times to the outside from the data output circuit. 5.

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