KR101087797B1 - Method for processing wafer - Google Patents

Method for processing wafer Download PDF

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KR101087797B1
KR101087797B1 KR1020100056551A KR20100056551A KR101087797B1 KR 101087797 B1 KR101087797 B1 KR 101087797B1 KR 1020100056551 A KR1020100056551 A KR 1020100056551A KR 20100056551 A KR20100056551 A KR 20100056551A KR 101087797 B1 KR101087797 B1 KR 101087797B1
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layer
silicon wafer
wafer
silicon
abandoned
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박형진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE: A method for processing a wafer is provided to prevent metallic impurities from being diffused to a silicon wafer by forming a porous silicon layer which functions as a diffusion preventing layer in a silicon wafer. CONSTITUTION: A silicon wafer(100) is provided. A stopping layer(105) is formed on the silicon wafer. A trap layer(110) is formed from the rear(100b) of the silicon wafer to the stopping layer. The trap layer is composed of a porous silicon layer. A pad oxide layer(115) is formed on the front(100a) and rear of the silicon wafer.

Description

웨이퍼 가공 방법{METHOD FOR PROCESSING WAFER}Wafer processing method {METHOD FOR PROCESSING WAFER}

본 발명은 웨이퍼 가공 방법에 관한 것이다. 보다 상세하게는 웨이퍼의 후면에 확산 방지막을 포함하는 웨이퍼 가공 방법에 관한 것이다.The present invention relates to a wafer processing method. More specifically, the present invention relates to a wafer processing method including a diffusion barrier on the rear surface of the wafer.

최근 반도체 소자가 고집적화됨에 따라 트랜지스터(Transistor) 및 캐패시터(Capacitor)의 고유 특성이 외부 환경 요소들에 영향을 많이 받게 되었다. 특히, 보호층이 형성되어 있지 않은 실리콘 웨이퍼를 사용하는 경우 금속성 불순물들의 영향을 배제할 수 없다.Recently, as semiconductor devices have been highly integrated, inherent characteristics of transistors and capacitors have been affected by external environmental factors. In particular, when using a silicon wafer in which no protective layer is formed, the influence of metallic impurities cannot be excluded.

예컨대, 구리 배선을 형성하기 위한 전기 도금(Electro Planting) 과정에서 구리 이온들이 실리콘 웨이퍼 전체에 노출되어 있으며, 구리 이온의 확산을 막기 위한 확산방지막이 존재하지 않는 실리콘 웨이퍼의 후면을 통해 구리 이온들이 침투된다. 이렇게 침투된 구리 이온들이 트랜지스터가 형성되어 있는 웰(Well)에 영향을 준다. 상술한 바와 같이, 반도체 소자를 제조하는 공정 중 발생되는 금속성 불순물들이 실리콘 웨이퍼 후면으로 침투되어 소자의 특성을 저하시키는 문제점이 있다. For example, during electroplating to form copper interconnects, copper ions are exposed to the entire silicon wafer, and copper ions penetrate through the back surface of the silicon wafer without a diffusion barrier to prevent diffusion of copper ions. do. The penetrated copper ions affect the well in which the transistor is formed. As described above, metallic impurities generated during the manufacturing process of the semiconductor device penetrate into the back surface of the silicon wafer, thereby deteriorating the characteristics of the device.

본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위한 것으로, 실리콘 웨이퍼 내에 확산 방지막 역할을 하는 다공성 실리콘층을 형성함으로써, 금속성 불순물들이 실리콘 웨이퍼 내로 확산되는 것을 방지하는 웨이퍼 가공 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a wafer processing method for preventing metallic impurities from being diffused into a silicon wafer by forming a porous silicon layer serving as a diffusion barrier in the silicon wafer. It is done.

상기 목적을 달성하기 위해, 본 발명은 실리콘 웨이퍼를 제공하는 단계와, 실리콘 웨이퍼 내에 트랩층(Trap Layer)을 형성하는 단계를 포함하는 것을 특징으로 한다. In order to achieve the above object, the present invention is characterized by comprising providing a silicon wafer, and forming a trap layer in the silicon wafer.

나아가, 트랩층(Trap Layer)은 다공성 실리콘층(Porous Silicon Layer)으로 형성하며, 다공성 실리콘층은 실리콘 웨이퍼 후면으로부터 실리콘 웨이퍼 내측으로 형성하는 것이 바람직하다. Further, the trap layer may be formed of a porous silicon layer, and the porous silicon layer may be formed from the back surface of the silicon wafer to the inside of the silicon wafer.

또한, 다공성 실리콘층은 HF와 에탄올이 혼합된 용액을 이용한 전기 화학 반응(Electro-Chemical Reaction)을 진행하여 형성하며, 이때 HF와 에탄올의 혼합 비율은 4 : 1인 것이 바람직하다. In addition, the porous silicon layer is formed by performing an electrochemical reaction (Electro-Chemical Reaction) using a mixture of HF and ethanol, wherein the mixing ratio of HF and ethanol is preferably 4: 1.

그리고, 트랩층(Trap Layer)은 패키지 공정 이전에 제거하는 것을 특징으로 한다. The trap layer may be removed before the package process.

본 발명의 웨이퍼 가공 방법은 반도체 소자의 제조 공정 중 발생되는 금속성 불순물이 웨이퍼 내부로 확산되는 것을 방지하여 트랜지스터의 특성을 안정화시키는 효과를 제공한다. 또한, 벌크 웨이퍼(Bulk Wafer)의 후면을 가공하여 보호층이 형성된 웨이퍼와 동일한 효과를 얻을 수 있으므로, 보호층이 형성된 웨이퍼 구매 시 소요되는 비용을 절감할 수 있는 효과를 제공한다.The wafer processing method of the present invention provides an effect of stabilizing the characteristics of the transistor by preventing the metallic impurities generated during the manufacturing process of the semiconductor device to diffuse into the wafer. In addition, by processing the rear surface of the bulk wafer (Bulk Wafer) can be obtained the same effect as the wafer with a protective layer, it provides an effect that can reduce the cost required to purchase a protective layer formed wafer.

도 1a 내지 도 1c는 본 발명에 따른 웨이퍼 가공 방법을 도시한 단면도이다.1A to 1C are cross-sectional views showing a wafer processing method according to the present invention.

이하 첨부된 도면을 참조하여 본 발명에 따른 웨이퍼 가공 방법의 일실시예에 대해 상세히 설명하기로 한다.Hereinafter, an embodiment of a wafer processing method according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1c는 본 발명에 따른 웨이퍼 가공 방법을 도시한 단면도들이다. 먼저 도 1a를 참조하면, 실리콘 웨이퍼(100)를 준비한 후 클리닝(Cleaning) 공정을 진행한다. 여기서, 실리콘 웨이퍼(100)는 1 × 1015 dose의 보론(Boron) 이온이 도핑되어 있다. 그리고, 실리콘 웨이퍼(100) 내에 정지막(105)을 형성한다. 정지막(105)은 실리콘 웨이퍼(100) 후면(100b)에 이온 주입을 진행한 후 열처리 공정을 진행하여 형성한다. 이때, 이온 주입은 N 타입인 인(P)이온을 사용하여 진행한다. 실리콘 웨이퍼(100) 상면(100a)의 소자가 형성되어 있는 지점부터 패키지 공정 시 필요한 물리적인 두께만큼 실리콘층을 남겨두어야 한다. 따라서, 실리콘 웨이퍼(100) 상면으로부터 일정두께 내에 정지막(105)을 형성하여 다공성 실리콘층이 일정두께 이상으로 형성되는 것을 방지한다. 즉, 정지막(105)은 후속으로 진행되는 다공성 실리콘층의 형성을 멈추는 역할을 한다. 1A to 1C are cross-sectional views illustrating a wafer processing method according to the present invention. First, referring to FIG. 1A, a silicon wafer 100 is prepared and then a cleaning process is performed. Here, the silicon wafer 100 is doped with 1 × 10 15 doses of boron ions. Then, a stop film 105 is formed in the silicon wafer 100. The stop film 105 is formed by implanting ions into the back surface 100b of the silicon wafer 100 and then performing a heat treatment process. At this time, ion implantation proceeds using an N-type phosphorus (P) ion. From the point where the device on the upper surface 100a of the silicon wafer 100 is formed, the silicon layer should be left as much as the physical thickness required for the packaging process. Therefore, the stop film 105 is formed within a predetermined thickness from the upper surface of the silicon wafer 100 to prevent the porous silicon layer from being formed at a predetermined thickness or more. That is, the stop film 105 serves to stop the formation of the porous silicon layer to be subsequently progressed.

그 다음, 실리콘 웨이퍼(100) 상면(100a)에 패시베이션층(미도시)을 형성한다. 여기서, 패시베이션층(미도시)은 질화막, 비정질 탄소막 및 이들의 조합 중 선택된 어느 하나로 형성하는 것이 바람직하다. 패시베이션층(미도시)은 후속 공정 시 습식 바스(Wet Bath) 내에서 실리콘 웨이퍼(100) 외곽이 손상되는 것을 보호해 주기 위해 형성한다.Next, a passivation layer (not shown) is formed on the upper surface 100a of the silicon wafer 100. Here, the passivation layer (not shown) is preferably formed of any one selected from a nitride film, an amorphous carbon film and a combination thereof. The passivation layer (not shown) is formed to protect the outside of the silicon wafer 100 from damage in a wet bath during subsequent processing.

도 1b를 참조하면, 실리콘 웨이퍼(100) 내에 트랩층(110)을 형성한다. 트랩층(110)은 다공성 실리콘층(Porous Silicon Layer)으로 형성하는 것이 바람직하다. 트랩층(110)은 실리콘 웨이퍼(100) 후면(100b)의 표면으로부터 정지막(105)이 형성된 부분까지 형성된다. 트랩층(110)은 반도체 소자의 제조 과정 중 발생하는 금속성 불순물(Metallic Impurity)에 대한 침투를 방지하는 층이다. 즉, 금속성 불순물이 확산되어 실제 소자가 구현되는 실리콘 웨이퍼(100)에 도달하지 못하도록 중간에서 잡아주는 역할을 한다. 예컨대, 트랩층(110)을 형성하는 과정에서 발생한 실리콘 불포화 결합(Silicon Dangling Bond)들의 농도가 높은 영역이 형성되므로, 구리(Cu), 나트륨(Na), 칼륨(K)을 포함하는 이온들이 침투되어 들어오면 이러한 이온들을 잡아준다.Referring to FIG. 1B, a trap layer 110 is formed in the silicon wafer 100. The trap layer 110 may be formed of a porous silicon layer. The trap layer 110 is formed from the surface of the back surface 100b of the silicon wafer 100 to the portion where the stop film 105 is formed. The trap layer 110 is a layer that prevents penetration of metallic impurities generated during the manufacturing process of the semiconductor device. That is, the metal impurity diffuses and serves to hold in the middle so as not to reach the silicon wafer 100 where the actual device is implemented. For example, since a region having a high concentration of Silicon Dangling Bonds formed during the formation of the trap layer 110 is formed, ions including copper (Cu), sodium (Na), and potassium (K) penetrate. When it comes in, it catches these ions.

이 트랩층(110)은 전기 화학 반응(Electro-Chemical Reaction)으로 형성한다. 전기 화학 반응은 HF와 에탄올을 4 : 1 비율로 혼합된 용액이 담겨진 습식 바스(Wet Bath)에서 진행하는 것이 바람직하다. 그리고, 실리콘 웨이퍼(100)의 상면(100a)에 '+' 전위를 인가하고, 실리콘 웨이퍼(100) 후면(100b)에서 일정거리 떨어져서 구비된 백금(Pt) 전극에 '-' 전위를 인가하여 전계를 형성한다. The trap layer 110 is formed by an electro-chemical reaction. The electrochemical reaction is preferably carried out in a wet bath containing a solution of HF and ethanol in a 4: 1 ratio. The '+' potential is applied to the upper surface 100a of the silicon wafer 100, and the '-' potential is applied to the platinum (Pt) electrode provided at a predetermined distance from the back surface 100b of the silicon wafer 100. To form.

이와 같이 형성된 전계 사이의 HF는 전기분해가 되고, 전기분해된 F- 이온은 전계에 의하여 실리콘 웨이퍼(100)의 후면(100b)쪽으로 이끌린다. 실리콘 웨이퍼(100)의 후면(100b)쪽으로 이끌린 F- 이온이 실리콘 웨이퍼(100)를 식각하여 실리콘 웨이퍼(100)의 실리콘층 내에 미세 기공(Micro Pore)들이 형성된다. 이렇게 미세 기공들이 형성되는 현상을 양극반응이라고 하며, 양극반응은 정지막(105)에서 반응이 정지된다. The HF between the electric fields thus formed is electrolyzed, and the electrolyzed F- ions are led toward the rear surface 100b of the silicon wafer 100 by the electric field. F-ions drawn toward the back surface 100b of the silicon wafer 100 etch the silicon wafer 100 to form micro pores in the silicon layer of the silicon wafer 100. The phenomenon in which the fine pores are formed is called anodic reaction, and the anodic reaction is stopped at the stop layer 105.

도 1c를 참조하면, 실리콘 웨이퍼(100) 상면(100a) 및 후면(100b)에 패드 산화막(115)을 형성한다. 이때, 패드 산화막(115) 형성을 위한 산화 공정 시 실리콘 웨이퍼(100) 후면(100b)의 트랩층(110)은 다수의 미세 기공으로 인해 실리콘 웨이퍼(100) 상면(100a)의 패드 산화막(115) 보다 더 깊은 깊이까지 산화가 진행된다. 즉, 트랩층(110) 표면이 일부 산화된다. 이후, 패드 산화막(115) 상부에 패드 질화막(미도시)을 형성하는 공정을 더 진행할 수 있다. 또한, 반도체 소자의 패키지 공정 이전에 금속성 불순물들을 잡고 있는 트랩층(110) 및 정지막(105)을 제거하여 금속성 불순물들이 소자에 영향을 미치지 않도록 하는 것이 바람직하다. Referring to FIG. 1C, a pad oxide film 115 is formed on the top surface 100a and the back surface 100b of the silicon wafer 100. At this time, during the oxidation process for forming the pad oxide film 115, the trap layer 110 of the back surface 100b of the silicon wafer 100 may have the pad oxide film 115 of the top surface 100a of the silicon wafer 100 due to a plurality of micropores. Oxidation proceeds to deeper depths. That is, the surface of the trap layer 110 is partially oxidized. Thereafter, a process of forming a pad nitride layer (not shown) on the pad oxide layer 115 may be further performed. In addition, it is preferable to remove the trap layer 110 and the stop layer 105 holding the metallic impurities before the semiconductor device package process so that the metallic impurities do not affect the device.

상술한 바와 같이, 실리콘 웨이퍼(100) 후면(100b)에 트랩층(110)을 삽입함으로써, 반도체 제조 공정 시 발생되는 금속성 불순물들이 실리콘 웨이퍼(100)의 후면(100b)을 통해 확산되어 침투되는 경우, 트랩층(110)에서 이들을 트랩하여 실제 소자가 구현되는 실리콘 웨이퍼(100) 영역까지 들어갈 수 없도록 막아주는 효과가 있다. As described above, when the trap layer 110 is inserted into the back surface 100b of the silicon wafer 100, the metallic impurities generated during the semiconductor manufacturing process are diffused and penetrated through the back surface 100b of the silicon wafer 100. By trapping them in the trap layer 110, it is possible to prevent them from entering the region of the silicon wafer 100 where the actual device is implemented.

본 발명은 기재된 실시예에 한정하는 것이 아니고, 본 발명의 사상 및 범위를 벗어나지 않는 한 다양하게 수정 및 변형을 할 수 있음은 당업자에게 자명하다고 할 수 있는 바, 그러한 변형예 또는 수정예들은 본 발명의 특허청구범위에 속하는 것이다.It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

100 : 실리콘 웨이퍼 110 : 트랩층
105 : 정지막 115 : 패드 산화막100 silicon wafer 110 trap layer
105: stop film 115: pad oxide film

Claims (8)

실리콘 웨이퍼를 제공하는 단계;
상기 실리콘 웨이퍼 내에 정지막을 형성하는 단계; 및
상기 실리콘 웨이퍼의 후면으로 부터 상기 정지막이 형성된 부분까지 트랩층(Trap Layer)을 형성하는 단계
를 포함하는 것을 특징으로 하는 웨이퍼 가공 방법.Providing a silicon wafer;
Forming a stop film in the silicon wafer; And
Forming a trap layer from a back surface of the silicon wafer to a portion where the stop film is formed;
Wafer processing method comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 청구항 1에 있어서,
상기 트랩층(Trap Layer)은 다공성 실리콘층(Porous Silicon Layer)으로 형성하는 것을 특징으로 하는 웨이퍼 가공 방법.The method according to claim 1,
The trap layer is a wafer processing method, characterized in that formed of a porous silicon layer (Porous Silicon Layer). 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 청구항 2에 있어서,
상기 다공성 실리콘층은 상기 실리콘 웨이퍼 후면으로부터 상기 실리콘 웨이퍼 내측으로 형성하는 것을 특징으로 하는 웨이퍼 가공 방법.The method according to claim 2,
And the porous silicon layer is formed from the back side of the silicon wafer to the inside of the silicon wafer. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 청구항 2에 있어서,
상기 다공성 실리콘층은 HF와 에탄올이 혼합된 용액을 이용한 전기 화학 반응(Electro-Chemical Reaction)을 진행하여 형성하는 것을 특징으로 하는 웨이퍼 가공 방법.The method according to claim 2,
The porous silicon layer is a wafer processing method characterized in that formed by performing an electro-chemical reaction (Electro-Chemical Reaction) using a mixture of HF and ethanol. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 청구항 4에 있어서,
상기 HF와 에탄올의 혼합 비율은 4 : 1인 것을 특징으로 하는 웨이퍼 가공 방법.The method of claim 4,
The mixing ratio of the HF and ethanol is 4: 1, characterized in that. 삭제delete 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 청구항 1에 있어서,
상기 정지막은 N 타입 이온을 주입하여 형성하는 것을 특징으로 하는 웨이퍼 가공 방법.The method according to claim 1,
And said stop film is formed by implanting N-type ions. 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 청구항 1에 있어서,
상기 정지막 및 트랩층(Trap Layer)은 패키지 공정 이전에 제거하는 것을 특징으로 하는 웨이퍼 가공 방법.The method according to claim 1,
The stop layer and the trap layer (Trap Layer) is removed before the package process.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731671A (en) * 2017-08-24 2018-02-23 长江存储科技有限责任公司 The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451451B1 (en) * 1999-04-01 2004-10-06 인피니언 테크놀로지스 아게 Method of processing a monocrystalline semiconductor disk and partially processed semiconductor disk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451451B1 (en) * 1999-04-01 2004-10-06 인피니언 테크놀로지스 아게 Method of processing a monocrystalline semiconductor disk and partially processed semiconductor disk

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107731671A (en) * 2017-08-24 2018-02-23 长江存储科技有限责任公司 The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion

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